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On 4 Jul 2005 21:26:22 -0700, "PeterC" <peter@geckoaudio.com> wrote:
>I have about a dozen clocks, and I do have non-clock signals connected
>to clk inputs of FFs (not RAM), and only one asynchronous reset which
>is not part of the problem which I'm trying to resolve. I'm very
>confident my gated clocks are not a cause of the problem - they are not
>part of the datapath where I'm seeing glitches.
>I do have muxed clock using a bit-MUX (not using a BUFGMUX), but
>chipscope is telling me the events around the mux'ed clock are fine.
>Specifically, the mux'ed clock is used to control the input and output
>of a shift register - across two clock domains (synchronous but of
>different frequencies). The shift register feeds the coefficient input
>(LD_DIN) port of the DA FIR v9.0 core, and I need to load it at a
>slower rate than the filter core clock frequency. I'm trying to
>determine the cause of the glitches on the FIR output - I'm loading a
>new set of coefficients every few output samples.
I'm going to guess that the wrong coefficients are loaded sometimes
because of the clock domain crossing. It will probably take you a
while to show that this is what is happening, and where and when, or
if this guess is wrong, to find out exactly what is happening.
If this guess is correct, rather than muxing the clock, I'd suggest
using a clock enable for the slower clock domain, so you can run both
using the same (faster) clock. Make the clock enable pulse high for
exactly one faster clock period at the rate of the slower clock. With
all the logic on this path on one low skew clock net, this path should
work much better.
>I do not have full static timing constraints - only two clock period
>constraints on my highest frequency clocks (both approx. 100 MHz).
To make sure the design works, not just once on the bench, but for
every part at every temperature and voltage, even after design
changes, you need full static timing constraints.
>Where would you suggest to include static timing constraints? Any hints
>in this area would be greatly appreciated.
This is what I would do. Open up a shell (command window) where the
.ncd file is generated. Type the following command:
trce -v 100 -u 1000 {your_file.ncd}
Then look at the report file is generated by this command:
{your_file.twr}
There will be groups of unconstrained signals in the report. Most of
these are realistic paths that will need constraints. I suspect that
there will be a lot of constraints needed. I would add these
constraints to the user constraint file, {your_file.ucf}, along with
comments that explain the path, and outline the calculation of the
numbers chosen.
--
Phil Hays
Phil-hays at comcast.com (remove com and add net) should work for
email
Article: 86751Hi, can you compile "smartmodel_wrappers=AD.vhd " stand-alone ? Is that module instantiated somewhere in a top level module ? Rgds Andr=E9Article: 86752
"Jon Beniston" <jon@beniston.com> schrieb im Newsbeitrag news:1120641395.345460.78030@g44g2000cwa.googlegroups.com... > Lattice devices have built in DSP and RAM, but no microprocessor. Their > current range of devices are more comparable to Spartan 3 in terms of > performance and price, than to Virtex 4. > > Cheers, > Jon > the new 'high end' Lattice FPGA's are to be announced soon as well AnttiArticle: 86753
Lattice devices have built in DSP and RAM, but no microprocessor. Their current range of devices are more comparable to Spartan 3 in terms of performance and price, than to Virtex 4. Cheers, JonArticle: 86754
"You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License." It's very much in Altera's interest to adhere to the license! Cheers, JonArticle: 86755
Hallo everyone. I have a simple ( but strange) problem. I am making a PLB interface for a decoder and I would like to implement the readiness of an output as an interrupt. Well, in the MHS file, I have connected the interrupt port of the decoder to the external interrupt port of the PowerPC, added the Interrupt handler routine in the MSS file. And also I tried the dynamic reegistering of the interrupt handler using the Register handler function. But somehow, the interrupt is still not working. XExc_RegisterHandler(XEXC_ID_NON_CRITICAL_INT, (XExceptionHandler)PLB_DECODER_Intr_DefaultHandler,(void *)XPAR_PLB_DECODER_0_BASEADDR); Well I have read somewhere that in the Linker Script file, I have to align the vector table to a 64k boundary and I did it as well. But still its not working. Note: PLB_DECODER_Intr_DefaultHandler() function, I have it in the main program file. Could someone help Joey PS: I am using a VirtexIIPro board from MemecArticle: 86756
Hi Here I would like to need some guidelines. I have a design which takes up 38 out of the 44 BRAMS available in my chip (VirtexIIPro, with one PowerPC). Now I would like to know how I can run the program without using the debugger. Can anybody give me an idea. If there are any tutorials available, I will really happy. Thank you all, JoeyArticle: 86757
I forgot to mention something.. I have 32MB SDRAM and 2 PROMs available on my board !! I have an ACE connector, but no card :( "Joey" <johnsons@kaiserslautern.de> schrieb im Newsbeitrag news:dag8ua$8f5$1@news.uni-kl.de... > Hi > > Here I would like to need some guidelines. I have a design which takes up 38 > out of the 44 BRAMS available in my chip (VirtexIIPro, with one PowerPC). > Now I would like to know how I can run the program without using the > debugger. Can anybody give me an idea. If there are any tutorials available, > I will really happy. > > Thank you all, > Joey > >Article: 86758
Hi, do you want to run the program out of sdram or out of the bram? What is the size of the c-code? Do you use the edk system as top level? Or do you integrate the edk system in your own top level? The tool flow from edk supports the mechanism to fit the c-code -> elf-file in the bram during the bitgen procedure. Then when the fpga is loaded the c-code starts directly.Article: 86759
"Andy Peters" <Bassman59a@yahoo.com> writes: > Peter Alfke wrote: > > Why would an adder be slower than an increment. > > In Xilinx, I see no difference. It's all a matter of carry propagation > > ( and it is pretty fast in either case.) > > Or is this a case of generics and portability? > > My analogy for generics is Fast Food. Throw a coin whether you go to > > McDon or to BurgerKing. it's all the same mediocre or below stuff. > > Same with a design that is fearful of being Xilinx specific. Using only > > the ingredients that everybody has, means lowering yourself to the > > lowest common denominator. > > Have guts and be specific! There is more stuff than Altera ever dreamt > > of. Sorry, couldn't resist the plug. > > Peter, > > I'm rather impressed that you were able to turn a comment about > increment vs adder speed into a dis on both VHDL generics AND Altera. > I'll just chip in, although Peter can comment for himself I'm sure - I read his comments on generics to be referring to "code written in a generic manner not to take advantage of one vendors feature set". I don't think he was referring to generics in the VHDL sense... However, your examples of where VHDL generics can be used are great! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 86760
hi all, since my company is going to buy a board from silica based on the virtex4 fpga (the part number is ADS-XLX-V4LX-EVL25 or ADS-XLX-V4LX-EVL60) i would like to have some comments from someone who is already using it expecially regarding the usb interface, implemented by means of a Cypress EZ-USB FX2 USB Microcontroller, part number CY7C68013-100AC. we need to set up a usb connection to stream data from the board to a pc (troughput 16Mbit/sec) but it is not clear to me the effort that must be done to implement this kind of link, both on the fpga and on the pc. have someone already done this with the board above mentioned? or in general with the usb controller that is mounted on the board? what source code (vhdl/verilog and/or software) comes with the board? is the complete usb protocol stack handled on the cypress usb controller or part of it has to be implemented in the fpga? with the software available from the cypress web site is it easy to write a driver for a pc? thanks in advance, hataArticle: 86761
"hata" <sabatian@libero.it> schrieb im Newsbeitrag news:1120647884.191377.187080@g47g2000cwa.googlegroups.com... > hi all, > > since my company is going to buy a board from silica based on the > virtex4 fpga (the part number is ADS-XLX-V4LX-EVL25 or > ADS-XLX-V4LX-EVL60) i would like to have some comments from someone who > is already using it expecially regarding the usb interface, implemented > by means of a Cypress EZ-USB FX2 USB Microcontroller, part number > CY7C68013-100AC. > > we need to set up a usb connection to stream data from the board to a > pc (troughput 16Mbit/sec) but it is not clear to me the effort that > must be done to implement this kind of link, both on the fpga and on > the pc. > > have someone already done this with the board above mentioned? or in > general with the usb controller that is mounted on the board? what > source code (vhdl/verilog and/or software) comes with the board? is the > complete usb protocol stack handled on the cypress usb controller or > part of it has to be implemented in the fpga? with the software > available from the cypress web site is it easy to write a driver for a > pc? > > thanks in advance, > > hata > the USB controller from Cypress needs to be programmed, its up to you to write the frmware, and yes using the software from cypress is relativly easy. for your task you possible some small IP core in FPGA to connect to the FIFO interface of the USB chip, thats mainly a few handshake signals. I have the same board I think (or similar avnet board with LX25) and there are NO USB examples included at all :( for your complete task you need 1) PC application 2) PC side driver 3) FX2 firmware 4) FPGA 'interface' ==> 1 man-month AnttiArticle: 86762
Hi Dave, > I couldn't find definitive data in the Altera literature about the speed > of the Stratix II parts. Do these parts run at speeds approaching the > Virtex 4 parts? Our latest benchmarking shows that the fastest Stratix II speed grade (the -3 devices) outperform the fastest Virtex-4 speed grade (-12) by 18% on average, with SII outperforming V4 on over 80% of tested designs. See http://www.altera.com/products/devices/performance/high_performance/per-high_performance_fpga.html for details -- there is a link to a whitepaper describing our comparison methodology. You can visit Xilinx's web page to see what they claim for the SII vs. V4 comparison -- as you can imagine the two companies do not see eye to eye :-) One side note: For Altera devices, lower numbers are faster (I believe way back in time the number was related to some path delay in the chip). For Xilinx devices, higher numbers are faster. So a SII -3 is faster than a SII -5, and V4 -10 is slower than V4 -12. Regards, Paul Leventis Altera Corp.Article: 86763
Hi Junaid, What additional information do you need? - PaulArticle: 86764
antti, thanks for your quick reply. do you know if there is some sort of framework or application example available from cypress? i serched on their web site and the only thing i found was a gpif designer (in my understnding needed only to set up the interface with the fpga), the windows driver for the mass storage application (two dll are provided but WITHOUT documentation!) and a some application note. i did not find any compiler or document explaining how to program the usb controller. are these tools provided with the board (compiler/assembler/driver/documentation)? thanks again, hataArticle: 86765
Don't fade away before an answer!Article: 86766
Hi, I want to run the program from SDRAM. The .elf file is almost 117kB in size. And my program (text part) is more than 35kb in size. It will get even bigger later :( By the way, I am using XPS for the synthesis. "Andi" <00andi@web.de> schrieb im Newsbeitrag news:ee8f786.1@webx.sUN8CHnE... > Hi, > > do you want to run the program out of sdram or out of the bram? What is the size of the c-code? Do you use the edk system as top level? Or do you integrate the edk system in your own top level? > > The tool flow from edk supports the mechanism to fit the c-code -> elf-file in the bram during the bitgen procedure. > > Then when the fpga is loaded the c-code starts directly.Article: 86767
> So a SII -3 is faster than a SII -5, and V4 -10 is slower than V4 -12. Do I detect a hint of NLP there? :) Cheers, JonArticle: 86768
No, this is not the best method. Actually, this not a good method at all. Two alternatives: One, general case : you should put a FIFO buffer with pointers and everything... Once a FIFO reaches some depth, you flush it with slow clock. Two, more "special" case : if your data arrives once in a period of time which is more than 3 slow clock cycles, there are some nice things we can do using asynchronous reset of a FF :-) if you really want to go with this one, let me know. It's a nice working solution. What is the data transmission rate & how bursty the transmission is? Vladislav "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:11cnn43fdchjqc8@corp.supernews.com... > Hello group, > > I am attempting to get data (column_in) from a fast > clock domain(clk_wr) to a slow clock domain(clk_rd). > > Is this the best method? > > fast_clock_process: process(clk_wr) > begin > if(clk_wr'event and clk_wr='1') then > if( fast_event='1' and slow_event='1') then > fast_event <= '0'; > elsif( strobe_in='1' ) then > fast_event <= '1'; > fast_column <= column_in; > end if; > end if; > end process; > > slow_clock_process: process(clk_rd) > begin > if(clk_rd'event and clk_rd='1') then > slow_event <= '0'; > if( fast_event='1' ) then > slow_event <='1'; > slow_column <= fast_column; > end if; > end if; > end process; > > Brad Smallridge > > >Article: 86769
If your fast data are coming in a burst you have to use a FIFO. If your fast signal is just one clock cycle high make it longer so that the slower clock domain can sample it. If this sampled signal is used to change for example a state in a FSM (slow clock domain) it is no problem. BUT Question: What if the signal in the slow clock domain should also be one clock cycle high ?=20 Rgds Andr=E9Article: 86770
hello all,
i have some doubt on the timing specs of FF set and rests.
I wrote the folllowing code in verilog.
always @(posedge clk)
if (a == 0) b <= clk;
else b <= 0;
always @(posedge b)
c <= 1;
always @(posedge clk)
c <= 0;
my intention was to momentarly rest the 'c' and if 'a' is true then
turn it back on. But the synthesizer gave error stating that
simultanious assign ment is not possible. How can i achive this . i
though like setting 'b' will take time thus the setting and resiing of
'c' will take place at differnt times. please give me comments on this
issue.
Article: 86771Jim, This is my first time for using usenet, so forgive me, I don't know how to post attachments. However, the schematics and all other documents are located on my website. For convenience, the schematics are located here: http://via.dynalias.org/hw/EthDev/MFG1-0B/doc/Schematic%20Prints.pdf I am interested in running IP cores since Protel by Altium has extremely nice support for FPGA development. They have a lot of IP cores included in their package, the interface is very nice to use compared to Quartus. That, and you can program/debug/simulate multiple FPGA's or even boards at the same time. This is the reason why I have included the ability to chain boards together with an easy header. However, you did mention use of NIOS. Although I have not looked itno the matter with great detail, I briefly read on it today, and it does seem attractive. We used it once in 3rd undergrad, and it was a really nice system to use in general. However, it's native support for SDRAM is convincing me to design around this for my next version which will have SDRAM instead of SRAM. Thank you for your suggestion :) jimgeorge at gmail dot com wrote: > Jai, could you post PDFs of your schematics and boards? I'd like to > know why you're interested in running cores like 8051 and ARM, there > was a recent thread discussing how CPUs designed specifically for FPGAs > like Microblaze and NIOS will make more efficient use of the fabric > compared to "regular" CPUs.Article: 86772
Hi everyone, I recently bought a Spartan II 2s200 PCI Board to use in a project. I programmed it with the Opencores PCI core. The problem is that when I plug it in the PCI slot of the computer the board turn on but the computer doesn't and the computer work well without the PCI board plugged. Any help? Thanks in advance. Regards; JorgeArticle: 86773
Hi, did you call the exception init function (XExc_init() ) which assigns the vectortable to the evpr register? How does you c-code looks like?Article: 86774
Hi, to add the c-code in sdram you need to store it in flash and build a booter that runs in the bram of the fpga to get the code out of the flash into the sdram and start it there. Do you have flash on your board? The biggest "one" section with edk is 125 kb with several block rams. So you can store you whole project also in the bram of the fpga if you want to.
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Compare FPGA features and resources
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