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MAP report file (*.mrp) is the place usually to look for the resources used. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk <nahum_barnea@yahoo.com> wrote in message news:1120994295.239520.89300@f14g2000cwb.googlegroups.com... > > Hi. > > I have a design target to xilinx virtex2pro30 device. > In the map stage I get "ERROR:342 design does not fit in device". > > But although I run "map -detail", the tool does not give me any details > such as how far I am off the device limitation, in what category my > design does not fit (registers or luts) etc ... > > Is there a way to extract this information from the Xilinx ISE tools ? > > ThankX, > NAHUM >Article: 86951
Hi all, does anybody know if a rtl simulator of the wishbone bus exist and, in case it does, if it is available somewhere? I looked on the opencores website but i did not fined anything about it. Thanks in advance, hataArticle: 86952
"hata" <sabatian@libero.it> schrieb im Newsbeitrag news:1121072789.540773.318960@g44g2000cwa.googlegroups.com... > Hi all, > > does anybody know if a rtl simulator of the wishbone bus exist and, in > case it does, if it is available somewhere? I looked on the opencores > website but i did not fined anything about it. > > Thanks in advance, > > hata > there are simulators for RTL and testbenches for the Wishbone, there is no such thing as 'wishbone simulator' you just run your HDL simulator on the wishbone testbench thats it. AnttiArticle: 86953
Hi Paul, You might want to look into directed routing for your application. With this you use FPGA editor to manually route the signals and place the FFs and DCMs exactly where you want them. You then use Tools->Directed Routing (or something like that!) to generate constraints that you add to your UCF file. This makes the P&R tool route the signals the same way every time. (Or at least it should do!) Once you get the hang of it, it's just about bearable! You'll also impress your colleagues with reams of gobbledygook in your UCF file. I recently spent a week or two doing this, and, although my monitor now has several dents, I just about remained sane. Just. YMMV, but be aware that the Synplify/ISE combination that I use has a bad habit of changing the net names, seemingly depending on the day of the week. This screws up your UCF constraints, of course. A friend of mine said he only does directed routing on Mondays, for this very reason! ;-) Cheers, Syms.Article: 86954
ERIC5: So let's hope the C-compiler is ready til september ;-) BTW: I think that LatticeXP is already a good platform for ERIC5. Thomas www.entner-electronics.com "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:dat88k$avo$00$1@news.t-online.com... > just a pre-pre info: > > a press release from Lattice is to be expected this week about some new > products. > > New products are both 'sides' from existing FPGAs, eg to lower end and to > higher end. > (the presse release may announce only part of the new devices I am not > sure > about this). > > The new lowest end FPGAs are well, hmm nice, that I can say - specially as > they have > feature(s) that low end PLDs have never had until now. That feature makes > them really > attractive as target platform for tiny SoftCore processors. > Pricing would be at the same or below Altera MAX2 > > (Yes, Thomas the IDEAL target silicon for ERIC5 will be available from > Lattice in september, at least that was the target date for the > availability > of the member of the new low cost family that would be 'fit' for ERIC5)! > > Antti > PS I think I said about much as can :) and for details I also need to wait > for friday to see the actual press release, etc.. > >Article: 86955
antti, you are right. i wrote the message too fast and my point was not clear at all. what i wanted to ask was the following: i could probably be asked to design an fpga module in order to be wishbone compliant and i wanted to know if somewhere some vhdl procedures, functions, packages or whatever emulating the wishbone timing were available to test my wishbone interface. i am still searching the web but i did not find anything like this yet. regards, hataArticle: 86956
Why are all the data files of the peripherals all postfixed with v2_1_0? At first I thought it was a version number, but then I noticed that ALL peripherals in the EDK have this same number postfixed to their all data filenames, regardless of the actual IP version number given in the directory names... Why is this?Article: 86957
<zoinks@mytrashmail.com> schrieb im Newsbeitrag news:1121080171.982291.240740@g43g2000cwa.googlegroups.com... > Why are all the data files of the peripherals all postfixed with > v2_1_0? > > At first I thought it was a version number, but then I noticed that ALL > peripherals in the EDK have this same number postfixed to their all > data filenames, regardless of the actual IP version number given in the > directory names... > > Why is this? > that is the version number of the specification of the .MPD format being used :) anttiArticle: 86958
Thank you guys. You are right !! The Flash CE pin of the board is connected to the FPGA DONE pin. So in my case, there is no possibility other than bringing the program to the BRAMs. <m.bodenbach@ifen.com> schrieb im Newsbeitrag news:1121007467.969541.92250@g47g2000cwa.googlegroups.com... > > > Joey schrieb: > > > Hi Joey, > > > > > > if your programm don't fit in the BRAMs (i think you have plb/opb BRAM > > > in your PPC design) you have a problem. > > > It sounds like you use a Memex Eval board. Is this right? > > > > > > Best regards, > > > > > > Michael > > > > Hey Michael, you are great !! IT IS a Memec Eval board and my prog is > > defenitely much bigger than what 8 BRAM blocks could ever hold. Are you > > saying that there is no other possibility, other than running it with a > > debugger. Well thats all I know (I give in that I am new in this field :( ) > > > > Joey > > Hi Joey, > > what type of board do yopu have. Can you send me you design? > With Memec boards it isn't possible to store or read user data from > PROMs, cause the CE pin of the PROM are connected to the DONE pin. > > Best regards, > > Michael >Article: 86959
OK. It seems that only when you run 'map' with '-timing' option, there is no area report when the design does not fit in device. "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<3jchrgFpcdd2U1@individual.net>... > <nahum_barnea@yahoo.com> schrieb im Newsbeitrag > news:1120994295.239520.89300@f14g2000cwb.googlegroups.com... > > > > Hi. > > > > I have a design target to xilinx virtex2pro30 device. > > In the map stage I get "ERROR:342 design does not fit in device". > > > > But although I run "map -detail", the tool does not give me any details > > such as how far I am off the device limitation, in what category my > > design does not fit (registers or luts) etc ... > > Are you sure? Usually it clearly says what kind of component is over > thelimit (LUTs, Slices, BRAMS, BUFGs etc.) > Have a closer look again. > > Regards > FalkArticle: 86960
John Adair wrote: > Not so common to find used these days but the older families are still > available if you must have a low rail count. Otherwise you can reduce your > rail count by making the I/O operate at the same as Vccint say 2.5V for a > Spartan-3. I think you mean Spartan 2 here (2.5V) The problem with Spartan 2 is that the small devices don't have much block RAM. With Spartan 3 the small devices are bigger internally and do have more block RAM, but the VccInt is too low for most interfacing to other logic. Adding a small regulator for VccInt is reasonable if you really need a "small" device, i.e. you don't have so many internal nets switching that the power requirements exceeds the regulator's current rating. > > Another way to reduce the pain is to use multi-output regulators. We use TI > parts TPS70402 for exactly this reason and get two rails out of a fairly > small package. You can also consider using a diode drop from 3.2/3.3V to > generate a Vccaux of 2.5V. > > John Adair > Enterpoint Ltd. - Home of MINI-CAN, PCI and CAN Development Board. > http://www.enterpoint.co.uk > > > "Thomas Reinemann" <Thomas.Reinemann@masch-bau.uni-magdeburg.de> wrote in > message news:dat7u2$rtp$1@fuerst.cs.uni-magdeburg.de... > > Hello, > > > > I'm looking for a small FPGA which needs only one voltage source and has > > about 10 kByte internal RAM.Since we have experience with Xilinx, I > > would prefer a Spartan, but they need three voltages. That's right? > > > > Bye Tom.Article: 86961
I want to build an easy decode-logic in VHDL. My problem is that the value I write to the output isn't stored till it should change :-( Here my simplified code: testprocess : PROCESS (IN1,IN2) BEGIN IF (IN1 = '1') AND (IN2 = '0') THEN OUT0 <= '1'; ELSIF (IN1 = '0') AND (IN2 = '1') THEN OUT0 <= '0'; END IF; END PROCESS testprocess; The Logic works like: If IN1=1 and IN2=0 the Output is 1 -> OK :-) If IN1 and IN2 are both 0 the value of the Output is not stored (like I want) but it goes to zero :-(((( but it should store the 1 till IN1=0 and IN0=1 !!!! My Design Software Altera Quartus II 5.0 shows this warnings: Warning: VHDL Process Statement warning at block_name.vhd(54): signal or variable "OUT0" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "OUT0" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design. Critical Warning: Design Assistant warning: Design should not contain combinational loops. Found 1 combinational loop(s) related to this rule. If I use a clock in the Process it works like a want it to do, but I don't want to use a clock! What I want is a latch (an RS-latch, actually). Unfortunately i heared, FPGAs don't have latches, they only have flip-flops so Quartus II tries to implement this using combinatorial logic. But how can I realize the needed function in an Altera MAX 7000 ??? please help, ManfredArticle: 86962
I see at least one problem here. The code doesn't really describe an RS latch because it holds its state with either both inputs high or both inputs low. A real RS latch would only hold in one of these two states. If you want the latch inputs to be active high you could leave out "AND (IN2 = '0')" in the first IF statement to describe a RS latch where IN1 has priority over IN2 if both are asserted. However I'm not sure if quartus will properly infer a latch from this. Manfred Balik wrote: > I want to build an easy decode-logic in VHDL. > My problem is that the value I write to the output isn't stored till it > should change :-( > Here my simplified code: > > testprocess : PROCESS (IN1,IN2) > BEGIN > IF (IN1 = '1') AND (IN2 = '0') THEN > OUT0 <= '1'; > ELSIF (IN1 = '0') AND (IN2 = '1') THEN > OUT0 <= '0'; > END IF; > END PROCESS testprocess; > > The Logic works like: > If IN1=1 and IN2=0 the Output is 1 -> OK :-) > If IN1 and IN2 are both 0 the value of the Output is not stored (like I > want) but it goes to zero :-(((( > but it should store the 1 till IN1=0 and IN0=1 !!!! > > My Design Software Altera Quartus II 5.0 shows this warnings: > > Warning: VHDL Process Statement warning at block_name.vhd(54): signal or > variable "OUT0" may not be assigned a new value in every possible path > through the Process Statement. Signal or variable "OUT0" holds its previous > value in every path with no new value assignment, which may create a > combinational loop in the current design. > Critical Warning: Design Assistant warning: Design should not contain > combinational loops. Found 1 combinational loop(s) related to this rule. > > If I use a clock in the Process it works like a want it to do, but I don't > want to use a clock! > > What I want is a latch (an RS-latch, actually). Unfortunately i heared, > FPGAs don't have latches, they only have flip-flops so Quartus II > tries to implement this using combinatorial logic. > But how can I realize the needed function in an Altera MAX 7000 ??? > > please help, ManfredArticle: 86963
Oops I meant Vccaux at 2.5V. I was thinking along the line that most people now have 3.3V already as a supply and you need to generate 2 more rails. The TPS70402 will generate 1 x 2amp and 1 x 1amp outputs. It takes a lot of very fast logic to drag 2 amps into a Spartan-3 on the Vccint rail. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Gabor" <gabor@alacron.com> wrote in message news:1121090368.354955.142800@g43g2000cwa.googlegroups.com... > > > John Adair wrote: >> Not so common to find used these days but the older families are still >> available if you must have a low rail count. Otherwise you can reduce >> your >> rail count by making the I/O operate at the same as Vccint say 2.5V for a >> Spartan-3. > > I think you mean Spartan 2 here (2.5V) > The problem with Spartan 2 is that the small devices don't have > much block RAM. With Spartan 3 the small devices are bigger > internally and do have more block RAM, but the VccInt is too > low for most interfacing to other logic. Adding a small regulator > for VccInt is reasonable if you really need a "small" device, > i.e. you don't have so many internal nets switching that the > power requirements exceeds the regulator's current rating. > >> >> Another way to reduce the pain is to use multi-output regulators. We use >> TI >> parts TPS70402 for exactly this reason and get two rails out of a fairly >> small package. You can also consider using a diode drop from 3.2/3.3V to >> generate a Vccaux of 2.5V. >> >> John Adair >> Enterpoint Ltd. - Home of MINI-CAN, PCI and CAN Development Board. >> http://www.enterpoint.co.uk >> >> >> "Thomas Reinemann" <Thomas.Reinemann@masch-bau.uni-magdeburg.de> wrote in >> message news:dat7u2$rtp$1@fuerst.cs.uni-magdeburg.de... >> > Hello, >> > >> > I'm looking for a small FPGA which needs only one voltage source and >> > has >> > about 10 kByte internal RAM.Since we have experience with Xilinx, I >> > would prefer a Spartan, but they need three voltages. That's right? >> > >> > Bye Tom. >Article: 86964
hata wrote: > antti, > > you are right. i wrote the message too fast and my point was not clear > at all. what i wanted to ask was the following: i could probably be > asked to design an fpga module in order to be wishbone compliant and i > wanted to know if somewhere some vhdl procedures, functions, packages > or whatever emulating the wishbone timing were available to test my > wishbone interface. i am still searching the web but i did not find > anything like this yet. > > regards, > > hata There are several wishbone master and slave modules floating around on opencores. You can use those to validate your implementation. Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis ****** Certified USB 2.0 HS OTG and HS Device IP Cores ******Article: 86965
Nju Njoroge wrote:
> Thanks for the suggestion. I tried this below:
> $display("NUM_COUNTER_CYCLES=%d", 2 ** `NUM_COUNTER_BITS);
>
> and it does print out "NUM_COUNTER_CYCLES=256" in ModelSim. However, in
> the actual waveform, the value is still 5 and the logic uses that
> incorrect value.
$display("NUM_COUNTER_CYCLES=%d", 2 ** `NUM_COUNTER_BITS);
isn't the same as:
$display("NUM_COUNTER_CYCLES=%d", NUM_COUNTER_CYCLES);
so maybe there's something else going on in your code?
> The main reason I want to use `define directive is because I'm using a
> `include file since this constant is used in many other modules.
Yeah, I've fought (and lost) that battle.
Another thing you could do is simply put the parameters on your tool's
command line. The two arguments against this are:
a) Some tools (like Xilinx XST) don't support setting parameters on the
command line, and
b) It's convenient to have the definitions for the particular build
available as a source file, rather than buried in a script somewhere.
The ideal is to be able to build different versions of your chip from
source without modifying the source. Sometimes practical issues get in
the way.
-a
Article: 86966Peter, I understand that FT256 is a more complicated package than TQ144. But why does it (the FT256 package) have a very heavier price impact on XC3S400 than on XC3S200? Can I expect the same for Spartan3E? Andrew, "Who knows how Xilinx do their pricing," Yes, but I don't feel good when something looks illogical to me! Luiz CarlosArticle: 86967
Manfred Balik wrote on 11/07/05 16:00: > testprocess : PROCESS (IN1,IN2) > BEGIN > IF (IN1 = '1') AND (IN2 = '0') THEN > OUT0 <= '1'; > ELSIF (IN1 = '0') AND (IN2 = '1') THEN > OUT0 <= '0'; > END IF; > END PROCESS testprocess; > > If I use a clock in the Process it works like a want it to do, but I don't > want to use a clock! Maybe you can force Quartus to generate a latch by adding an "ELSE"-condition, like ... ELSE OUT0 <= OUT0; END IF; Don't know if this will work with Quartus, but trying won't hurt. I think XST would infer a latch from your description, maybe Quartus aims to avoid latches and uses a default instead... cu, SeanArticle: 86968
Does anyone have any good Scope/LogicAnalyzer module/addon solutions that decode the physical 8b/10b signals on the Rocket IO interfaces? I perfer to see the output as hex values + some timing info. I work on the software side of the system. It will be very nice if it can help debug the 1g/10g Rocket IO implementations, auto-negotiation, traffic lockup issues, etc. Thanks in advance. -TonyArticle: 86969
<tony.p.lee@gmail.com> schrieb im Newsbeitrag news:1121108087.721442.149670@o13g2000cwo.googlegroups.com... > Does anyone have any good Scope/LogicAnalyzer module/addon solutions > that decode the physical 8b/10b signals on the Rocket IO interfaces? > I perfer to see the output as hex values + some timing info. I work > on the software side of the system. > > It will be very nice if it can help debug the > 1g/10g Rocket IO implementations, auto-negotiation, > traffic lockup issues, etc. > > Thanks in advance. > > -Tony > its fairly simple to add customized modules to Chipscope to generate addition trigger signal's etc.. the output can be displayed in what ever values you want, hex AnttiArticle: 86970
Hello. I want to control an ADSP-TS201S EZ-KIT Lite from a PC by connecting it to an Avnet evaluation kit which contains a Spartan 3 on a PCI form factor through one of the EZ-KIT link ports pairs. My application data throughput is not very demanding so it=B4s my understanding I can program the SPD bits to divide the 500MHz CCLK by 4 giving me a transfer clock of 125MHz (transfer rate of 250Mbps) wich is much higher than I need (I wish I could reduce it even more - 100 or even 50MBps would do just fine). So my first question is if Spartan 3 (-4 grade to stay in the worst case) would allow such a rate reliably. May I clock the receiving side at a lower rate then the trasmitter? I also would like to know if somebody could indicate resources other than Xilinx=B4s xapp634/xapp635, including commercial cores. Google hasn=B4t been of much help unfortunately. I am also considering other ways (Bittware=B4s ASIC, AMCC=B4s Matchmaker etc.) to do the final design but the scheme above seems to be the simplest that would allow me to develop with TS before I have a workable prototype (I may be missing something though and would appreciate your inputs.) If it works fine I may even use it in the final design as it=B4s going to have a FPGA (much likely a Spartan 3) anyway. Thank you very much in advance for your insights. Elder.Article: 86971
Specs: Altera Cyclone EP1C12Q240C8 FPGA chip 32 MB SDRAM SD/MMC card slot MSX Cartridge slot 2 mono audio outputs Composite video output VGA output PS/2 keyboard connector USB connector MSX Joystick port FPGA I/O pin (40 pins and 10 pins) Short instruction manual 110/220V AC power supply Info: http://www.bazix.nl/onechipmsx.html Cheers, Sander Zuidema -------------------------------------- Bazix VOF Hoge der A 30-2 9712 AE Groningen T: +31(0)50-3112518 I: www.bazix.nl --------------------------------------Article: 86972
Sander Zuidema wrote: > Specs: > > Altera Cyclone EP1C12Q240C8 FPGA chip > 32 MB SDRAM > SD/MMC card slot > MSX Cartridge slot > 2 mono audio outputs > Composite video output > VGA output > PS/2 keyboard connector > USB connector > MSX Joystick port > FPGA I/O pin (40 pins and 10 pins) > Short instruction manual > 110/220V AC power supply > > Info: http://www.bazix.nl/onechipmsx.html > > Cheers, > > Sander Zuidema > Wonder why it took 2 years to arrive in Europe from Japan (o; rickArticle: 86973
> Wonder why it took 2 years to arrive in Europe from Japan (o; Errr... although the first steps of the 'MSX revival' were taken more than 2 years ago in Japan, the One Chip MSX is a new product that still has to go into production, even in Japan ;) Cheers, Sander -------------------------------------- Bazix VOF Hoge der A 30-2 9712 AE Groningen T: +31(0)50-3112518 I: www.bazix.nl --------------------------------------Article: 86974
"Sander Zuidema" <s.zuidema@bazix.nl> schrieb im Newsbeitrag news:11d5p85ajdt5p5e@corp.supernews.com... > > > Wonder why it took 2 years to arrive in Europe from Japan (o; > > Errr... although the first steps of the 'MSX revival' were taken more > than 2 years ago in Japan, the One Chip MSX is a new product that still > has to go into production, even in Japan ;) > > Cheers, > > Sander > > -------------------------------------- > Bazix VOF > Hoge der A 30-2 > 9712 AE > Groningen > > T: +31(0)50-3112518 > I: www.bazix.nl > -------------------------------------- so I copy a bitrstream to the sd card and new computer is ready to go? how come? I dont see an intelligent configuration controller, only the serial config eprom :( and sd card that is connected to the FPGA, ah ok well yes its actually doable, if ALL bitstreams include the spi reflasher and some config selection then, but still its not very easy.. http://www.hydraxc.com is truly reconfigurable everything comes (or can) from removable media. the onechipmsx just promises lots of configs, anything ready ? commodore64 is 100% working ??? or is it just someone wishful thinking? Antti
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