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Messages from 86625

Article: 86625
Subject: Re: PROM Generation question
From: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?= <xjohbex@xfoix.se>
Date: Fri, 01 Jul 2005 09:24:24 +0200
Links: << >>  << T >>  << A >>
jimgeorge at gmail dot com wrote:
> OK, thanks all, I found the mistake (this happens because Impact seems
> to maintain several "current directory" entries internally, and I was
> picking up a bit file for an XC2V1000)

That explains... =)

> 
> BTW, this is out of curiosity, if I have a board with an FG676
> footprint, designed to use either an XC2V3000-FG676 or an
> XC2V1000-FG456, and I have three XC18V04 PROMs, what should I do if I
> have an XC2V1000-FG456 soldered onto the board? I'm guessing Johan's
> suggestion may work then, but correct me if I'm wrong. Thanks!
> 


Yep, that's exactly my case. I.e. you use the PROMs closest to the FPGA.

-- 
-----------------------------------------------
Johan Bernspång, xjohbex@xfoix.se
Research engineer

Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems

www.foi.se

Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------

Article: 86626
Subject: Re: init ProASIC3 Ram from spi
From: Jedi <me@aol.com>
Date: Fri, 01 Jul 2005 07:33:06 GMT
Links: << >>  << T >>  << A >>
Neill A wrote:
> Jedi wrote:
> 
>>Hello...
>>
>>Wasn't there once an application note on Actel.com
>>for initialising internal RAM from an SPI memory?
>>
>>
>>rick
> 
> 
> Yes, and it is still there:
> 
> http://www.actel.com/documents/EmbeddedSRAMInit_AN.pdf
> 


Right..thanx...thought it was SPI and not I2C (o;

nice weekend
rick

Article: 86627
Subject: Re: Clock buffering in VirtexE FPGA
From: "vssumesh" <vssumesh_asic@yahoo.com>
Date: 1 Jul 2005 02:49:28 -0700
Links: << >>  << T >>  << A >>
hello Alfke..
  will that be a problem if the push button switch does have a
capacitor filter to reject switching noise. It have a filter with 10K
resistor 10uF capacitor two 74V04 buffer stages and a diode protection
at the input side. I am using this output to trigger a four bit
counter.
Will the bounce cause any damage to the sytem FPGA. Please advice me...


Article: 86628
Subject: Re: Direct audio output from FPGA pins
From: "Martin Schoeberl" <mschoebe@mail.tuwien.ac.at>
Date: Fri, 1 Jul 2005 12:12:33 +0200
Links: << >>  << T >>  << A >>
> So you would have one pin driving a High into the 8 Ohm speaker, while
> the other pin sinks a Low.
> No pin would ever be negative, but you have the drive impedance plus
> the sink impedance in series with the speaker. Each of the three might
> be around 8 Ohm, for a total of 24 Ohm, and a peak current closer to
> 100 mA.
> If you pick the strongest output standard, you still will have limited
> aplitude.
> I agree with the suggestion of a low-cost Clas-D amplifier instead.

OK, I forgot the output resistance. So let's suppose Imax of 100mA:

    Peff = (Imax/2)^2*R = 20mW

That's perhaps enough for a head phone.

However, the question if I will burn my FPGA still remains. Two issues:
The maximum current: There is no maximum rating in the data sheet of
the Spartan-3, in the Cyclone data sheet the absoulte maximum rating is
25mA.

The second: A speaker is an inductive load. When we switch the output
the energy stored in the L will still drive the current resulting in
high voltage peaks until the 'current finds it's way'. Will this damage
the output driver? Shall I use external diodes to VCC and GND like
the self-induction recuperation diode used on a relay?

Martin 



Article: 86629
Subject: Re: Clock buffering in VirtexE FPGA
From: "Ben Jones" <ben.jones@xilinx.com>
Date: Fri, 1 Jul 2005 11:33:47 +0100
Links: << >>  << T >>  << A >>
>   will that be a problem if the push button switch does have a
> capacitor filter to reject switching noise. It have a filter with 10K
> resistor 10uF capacitor two 74V04 buffer stages and a diode protection
> at the input side. I am using this output to trigger a four bit
> counter.

That's a very elaborate circuit for a humble push-button.

> Will the bounce cause any damage to the sytem FPGA. Please advice me...

The device will be fine. Just please don't use this signal as a clock. If
you want to count events on it, then sample it, edge-detect it, turn it into
a single-cycle pulse in your system clock domain and use it as an enable to
your four-bit counter. Anything else is asking for trouble.

        -Ben-



Article: 86630
Subject: Re: Direct audio output from FPGA pins
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 1 Jul 2005 03:38:38 -0700
Links: << >>  << T >>  << A >>
"Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> wrote in message 
news:42c51713$0$12384$3b214f66@tunews.univie.ac.at...
>
> However, the question if I will burn my FPGA still remains. Two issues:
> The maximum current: There is no maximum rating in the data sheet of
> the Spartan-3, in the Cyclone data sheet the absoulte maximum rating is
> 25mA.
>
I used most of the Xilinx FPGAs over the years, and never broke any of them 
with a short to ground or Vcco. They just warm up a bit!
>
> The second: A speaker is an inductive load. When we switch the output
> the energy stored in the L will still drive the current resulting in
> high voltage peaks until the 'current finds it's way'. Will this damage
> the output driver? Shall I use external diodes to VCC and GND like
> the self-induction recuperation diode used on a relay?
>
Provided you never tri-state the output pins, there's always a path for the 
current. However, as you switch, this happens:-

Immediately before switching
Output_1    =>   Vout1   --this one is driving high
Output_2    =>   Vout2   --this one is driving low

Immediately after switching (current in speaker remains constant)
Output_1    =>   -Vout2          --this one now driving low
Output_2    =>   2Vcco - Vout1   --this one now driving high

Where Vcco is the IO supply. This assumes that the output resistance of the 
positive driving and negative driving IO pins stays constant with voltage. 
You could simulate with (or just read) the IBIS files to get exact answers. 
So, I reckon an 8 ohm speaker is gonna break your pins, unless you use a 
awful lot of them so that Rout << 8 ohms.
HTH, Syms. 



Article: 86631
Subject: Re: Linux 2.6 on the Xilinx ML310 board
From: "Sven Gowal" <sgowal@gmail.com>
Date: 1 Jul 2005 04:15:12 -0700
Links: << >>  << T >>  << A >>
Thanks a lot, I could finally make it work yesterday. If anyone needs
help on that, just mail me.


Article: 86632
Subject: Avnet V4 - XC4VLX25
From: "des00" <diod2003@list.ru>
Date: 1 Jul 2005 05:18:59 -0700
Links: << >>  << T >>  << A >>
Could somebody help me about this board? My company bought this
Evaluation Kit and in User Guide in user information wrote
"Configuration data can come from the following sources: the on-board
configuration PROM, an external download cable or the on-board USB
controller".
But I did not find anything more about configuration possibility by
on-board USB controller in documentation.
I ack Avnet Tech Support and send them my ack, but they don't answer my
letter yet. Thats why i decided to ack here :)
Could somebody say me : may I configurate XC4VLX25-FF668 via USB or
not? If i can do it, which software shall i use ?


Article: 86633
Subject: Re: Good FPGA for an encryptor
From: "Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl>
Date: Fri, 1 Jul 2005 14:44:12 +0200
Links: << >>  << T >>  << A >>
Hello,

vbetz@altera.com wrote:

> Not sure if this would meet your needs or not, but MAX II has on-chip
> flash where you could store the key.

Unfortunately MAXes are too small and I need many banks of RAM... :-(

    Best regards
    Piotr Wyderski


Article: 86634
Subject: interpolation in FPGA
From: "amko" <sinebrate@yahoo.com>
Date: 1 Jul 2005 05:55:42 -0700
Links: << >>  << T >>  << A >>
Hello!

I like to know if anybody have done any interpolation (e.g quadrature)
in FPGA
or where I can get application note or any literature about it.

I know delta (slope) of signal (pulse) and duration which FPGA must
generate.  Intermediate points must be calculate with quadrature or
polynomial functions. I must send data from FPGA on 16 bit parallel bus
trough an DAC.
It is not possible to store this signals inside FPGA and then
regenerate because  shapes of these signals is changed dynamically
(slope, duration, shape..) 

thank you and regards, 

Amir


Article: 86635
Subject: Re: Avnet V4 - XC4VLX25
From: "Antti Lukats" <antti@openchip.org>
Date: Fri, 1 Jul 2005 15:01:10 +0200
Links: << >>  << T >>  << A >>
I have the same board and no USB software

guess its wishfull thinking, oh we will implement this by the time board is
ready.
but they never did it. so there is no usb download as far as I know.

bug them more, they should actually provide the utility if it was
'advertized'

antti

"des00" <diod2003@list.ru> schrieb im Newsbeitrag
news:1120220339.294058.242330@g44g2000cwa.googlegroups.com...
> Could somebody help me about this board? My company bought this
> Evaluation Kit and in User Guide in user information wrote
> "Configuration data can come from the following sources: the on-board
> configuration PROM, an external download cable or the on-board USB
> controller".
> But I did not find anything more about configuration possibility by
> on-board USB controller in documentation.
> I ack Avnet Tech Support and send them my ack, but they don't answer my
> letter yet. Thats why i decided to ack here :)
> Could somebody say me : may I configurate XC4VLX25-FF668 via USB or
> not? If i can do it, which software shall i use ?
>



Article: 86636
Subject: Re: interpolation in FPGA
From: "jerzy.gbur@gmail.com" <jerzy.gbur@gmail.com>
Date: 1 Jul 2005 06:52:23 -0700
Links: << >>  << T >>  << A >>
Are you sure you can't use FIR?

regards

Jerzy Gbur


Article: 86637
Subject: Re: V4 and DDR2 666
From: Austin Lesea <austin@xilinx.com>
Date: Fri, 01 Jul 2005 07:49:06 -0700
Links: << >>  << T >>  << A >>
Jeremy,

I saw a photo of a demo pcb from Japan with an LX60 which has 333MHz DDR 
RAM chips on it.  I was looking at it for the power disctribution system 
performance, not the DDR interface.

It looked very nice.

If interested, please email directly, and I can give you the contact. 
That is all I know.

Austin

Jeremy Stringer wrote:

> fortiz80@gmail.com wrote:
> 
>> Hi all,
>>
>> Xilinx has announced support for DDR2 up to 533 MHz. Are there any
>> physical limitations that won't allow higher frequencies to be used?
> 
> 
> Umm..  That's 533M*bit* (267MHz).
> 
> You could try:
> a) Working through the app notes (I know at least some of them have 
> timing budget calculations)
> b) Attempting to build a simple design using something like the memory 
> interface generator, and targeting it to a specific chip.
> 
> These might provide you with more information..  My guess would be that 
> losing 350 ps odd off the timing budget would be the killer - the 
> question of why could probably be answered by examining it in the above 
> fashion.
> 
> I'd be curious myself actually - particularly if you ran through these 
> and came to the conclusion that it could be done...
> 
> Jeremy

Article: 86638
Subject: re:Problem for xilinx!!!
From: dejavu99@hotmail-dot-it.no-spam.invalid (damidar)
Date: Fri, 01 Jul 2005 11:16:55 -0500
Links: << >>  << T >>  << A >>
Help me please.....It's the same.....ever...... :oops: 

ERROR: iMPACT:583 - '1': The idcode read from the device does not
match the idcode in the bsdl File.

INFO:iMPACT:1578 - '1':  Device IDCODE :       
01001001011000000010000010010011

INFO:iMPACT:1579 - '1': Expected IDCODE:   
00001001011000000010000010010011

'1': Check to make sure if version '0100' is supported.

PROGRESS_END - End Operation.
Elapsed time =      1 sec.


Thanks a lot.........


Article: 86639
Subject: Re: APEX 20K PLL
From: "alpha" <zhg.liu@gmail.com>
Date: 1 Jul 2005 10:01:41 -0700
Links: << >>  << T >>  << A >>
Problem solved. Quartus II V3 's issue. Plus SP1 works. 
Thanks

--ZL


Article: 86640
Subject: Re: Direct audio output from FPGA pins
From: "Andy Peters" <Bassman59a@yahoo.com>
Date: 1 Jul 2005 10:39:24 -0700
Links: << >>  << T >>  << A >>
Martin Schoeberl wrote:
> I'm playing around with sigma-delat ADC and DAC for audio. It's amazing
> how good this works without any active components. Just Rs and Cs.
>
> The question now is: Can I hook a speaker direct to the output pins of
> an FPGA?

FWIW, we did a pattern generator based on an FPGA.  Some of the outputs
ran through RS-422 drivers.  As a goofy test, we cooked up a pattern
that would use PWM to play music through the diff output.  We used caps
between the diff driver and the speaker as a DC block.

It sounded like an AM radio, but it worked.

-a


Article: 86641
Subject: vhdl source code cross reference tool
From: "geoffrey wall" <wallge@eng.fsu.edu>
Date: Fri, 1 Jul 2005 14:01:24 -0400
Links: << >>  << T >>  << A >>

Is anyone aware of a software package that can cross reference vhdl language 
components and
instantiations of those components?
For instance if I see a name of something in a piece of code and I don't 
know where it is defined (or what it does)
I can then click on that name and be linked to the code where it is defined.
another thing that would be helpful is some kind of graphical hierarchy of 
entities, components
and the like (I don't mean a schematic). something like what is available in 
visual c++ and other
software design entry tools where object oriented concepts/relationships can 
be represented graphically.
I am dealing with a large set of unfamiliar vhdl with alot of component 
hierchies. I'd like to quickly understand
and parse through this could with some kind of  tool like i have described 
above.


thanks

-- 
Geoffrey Wall
Masters Student in Electrical/Computer Engineering
Florida State University, FAMU/FSU College of Engineering
wallge@eng.fsu.edu
Cell Phone:
850.339.4157

ECE Machine Intelligence Lab
http://www.eng.fsu.edu/mil
MIL Office Phone:
850.410.6145

Center for Applied Vision and Imaging Science
http://cavis.fsu.edu/
CAVIS Office Phone:
850.645.2257 



Article: 86642
Subject: Re: Direct audio output from FPGA pins
From: "Peter Alfke" <peter@xilinx.com>
Date: 1 Jul 2005 11:14:52 -0700
Links: << >>  << T >>  << A >>
No need for capacitors if your digital signal is dc-balanced, i.e. on
average the same length of time High as Low. That's the beauty of the
bridge output.
Peter Alfke

Andy Peters wrote:
> Martin Schoeberl wrote:
> > I'm playing around with sigma-delat ADC and DAC for audio. It's amazing
> > how good this works without any active components. Just Rs and Cs.
> >
> > The question now is: Can I hook a speaker direct to the output pins of
> > an FPGA?
>
> FWIW, we did a pattern generator based on an FPGA.  Some of the outputs
> ran through RS-422 drivers.  As a goofy test, we cooked up a pattern
> that would use PWM to play music through the diff output.  We used caps
> between the diff driver and the speaker as a DC block.
> 
> It sounded like an AM radio, but it worked.
> 
> -a


Article: 86643
Subject: Re: Clock buffering in VirtexE FPGA
From: "Peter Alfke" <peter@xilinx.com>
Date: 1 Jul 2005 11:30:11 -0700
Links: << >>  << T >>  << A >>
Back to basics: (Experienced designers please ignore this).
Any mechanical switch bounces, i.e. a switch closure is followed by a
rapid sequence of open-close-open-close sequences (and a similar thing
usually happens when the switch opens).
This switch bounce can last for several milliseconds.
If you have a single-pole-double-throw (SPDT) switch, you can easily
circumvent the bounce, but with a simple switch you have to find a way
to suppress it.
Timing is the only differentiation between a single switch closure
(with bounce) and an intentional sequence of switch operation.
So you need a millisecond timing element to suppress the bounce, and
milliseconds are hard to come by in a 100 MHz-clocked digital chip. But
there is no alternative.

As I mentioned earlier, you can share one delay circuit between
multiple switches, and you can also create the delay with external RC
components, but you have to find some way to reliably differentiate
between unavoidable bounce and intentional repetitive operation.
Luckily, there are a few orders of magnitude of time in between.
Peter Alfke


Article: 86644
Subject: Foundation 3.1 in WinXP machine Problems!
From: "Tony" <nicemanYep@yahoo.co.uk>
Date: 1 Jul 2005 11:48:38 -0700
Links: << >>  << T >>  << A >>
Hi,

I have tried today to install Foundation 3.1 in my windows xp machine.
I have not done any FPGA design for 4 years and i have the new version
of xilinx tool but need to complete then convert some of my old
schematic based projects which are not supported any more by the
current version of xilinx tools.

keep getting this error: Error: XIE32.exe is unable to locate
libbasxi.dll:" the implementation button is greyed out, i.e. i can't
synthesis my projects anymore (i need to do this to complete some old
projects using old chips)

I have tried the solution suggested at this link:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10791


but simply it is not working. I am using windows XP with SP2. could
this be the reason?

if anyone has any suggestion, i'll be extremely delighted as xilinx
technical support does not handle f 3.1 related issues 

Cheers


Article: 86645
Subject: Re: Foundation 3.1 in WinXP machine Problems!
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 1 Jul 2005 20:52:05 +0200
Links: << >>  << T >>  << A >>

"Tony" <nicemanYep@yahoo.co.uk> schrieb im Newsbeitrag
news:1120243718.479899.301280@g14g2000cwa.googlegroups.com...
> Hi,
>
> I have tried today to install Foundation 3.1 in my windows xp machine.

> if anyone has any suggestion, i'll be extremely delighted as xilinx
> technical support does not handle f 3.1 related issues

I wouldnt mess around with this stuff, waste of time. Get a computer with
Win95 or Win2K, install it there and you are done.

Regards
Falk






Article: 86646
Subject: Re: Foundation 3.1 in WinXP machine Problems!
From: "Gabor" <gabor@alacron.com>
Date: 1 Jul 2005 12:28:41 -0700
Links: << >>  << T >>  << A >>
I'm running Foundation 4.1i on Windows XP SP1.  I believe there are
issues with 16 bit applications under XP service pack 2.  I don't think
there are significant differences between Xilinx releases 3.1i and 4.1i
that would cause your problems.  If you have an XP machine that hasn't
been updated to SP2 yet I would try that.

Good luck,
Gabor

Tony wrote:
> Hi,
>
> I have tried today to install Foundation 3.1 in my windows xp machine.
> I have not done any FPGA design for 4 years and i have the new version
> of xilinx tool but need to complete then convert some of my old
> schematic based projects which are not supported any more by the
> current version of xilinx tools.
>
> keep getting this error: Error: XIE32.exe is unable to locate
> libbasxi.dll:" the implementation button is greyed out, i.e. i can't
> synthesis my projects anymore (i need to do this to complete some old
> projects using old chips)
>
> I have tried the solution suggested at this link:
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10791
>
>
> but simply it is not working. I am using windows XP with SP2. could
> this be the reason?
>
> if anyone has any suggestion, i'll be extremely delighted as xilinx
> technical support does not handle f 3.1 related issues 
> 
> Cheers


Article: 86647
Subject: Re: Clock buffering in VirtexE FPGA
From: "Gabor" <gabor@alacron.com>
Date: 1 Jul 2005 12:49:06 -0700
Links: << >>  << T >>  << A >>


Peter Alfke wrote:
> Back to basics: (Experienced designers please ignore this).
> Any mechanical switch bounces, i.e. a switch closure is followed by a
> rapid sequence of open-close-open-close sequences (and a similar thing
> usually happens when the switch opens).
> This switch bounce can last for several milliseconds.
> If you have a single-pole-double-throw (SPDT) switch, you can easily
> circumvent the bounce, but with a simple switch you have to find a way
> to suppress it.
> Timing is the only differentiation between a single switch closure
> (with bounce) and an intentional sequence of switch operation.
> So you need a millisecond timing element to suppress the bounce, and
> milliseconds are hard to come by in a 100 MHz-clocked digital chip. But
> there is no alternative.
>
> As I mentioned earlier, you can share one delay circuit between
> multiple switches, and you can also create the delay with external RC
> components, but you have to find some way to reliably differentiate
> between unavoidable bounce and intentional repetitive operation.
> Luckily, there are a few orders of magnitude of time in between.
> Peter Alfke

All that being said, you can use any input pin as a clock, not just the
global clock inputs.  This is O.K. as long as you don't have tight
timing
constraints for hold after the clock.  In your case you probably don't
want to do this, but you can always instantiate an input buffer and
use the output of the IBUF as your clock source.  This will be treated
by the tools as any other internal signal made into a clock, so you
shouldn't get the mapping errors (these come from an attempt to place
an IBUFG in the non-global IOB).  If you want you can also instantiate
the BUFG after the IBUF, or if you're only clocking a single flip-flop
for example and don't want a BUFG, you can attach a CLOCK_BUFFER
constraint to the net (and set it to "none").

By the way, milliseconds may be "hard to come by", but not expensive
in terms of CLB's.  There were some very good posts on building long
counters using SRL16's. see:

http://groups-beta.google.com/group/comp.arch.fpga/msg/ce00d2e88b7865b8?hl=en

Which shows a very slick way to divide by 2^37 in just 3 slices.


Article: 86648
Subject: Re: Direct audio output from FPGA pins
From: christopher.saunter@durham.ac.uk (c d saunter)
Date: Fri, 1 Jul 2005 19:57:55 +0000 (UTC)
Links: << >>  << T >>  << A >>
Martin Schoeberl (mschoebe@mail.tuwien.ac.at) wrote:
: I'm playing around with sigma-delat ADC and DAC for audio. It's amazing
: how good this works without any active components. Just Rs and Cs.

: The question now is: Can I hook a speaker direct to the output pins of
: an FPGA?

Others have commented on the mismatched driver and speaker resistance which will 
limit power transfer - you might get better results from a single raw IO pin using 
a piezo sounder, as found in 'novelty' cards and crystal earpieces - I don't have 
any numbers to hand but I'm guessing these will have a higher capacitance, lower 
inductance and higher resistance, so will still provide low pass filtering, but 
will represent better power transfer from the FPGA.

After all you can build an AM reciever using one of these that is audiable where 
the only powre source is 15 meters antanna wire...

---

cds

Article: 86649
Subject: Re: vhdl source code cross reference tool
From: "Jim Wu" <nospam@nospam.com>
Date: Fri, 1 Jul 2005 16:37:19 -0400
Links: << >>  << T >>  << A >>
Most of the simulators such as modelsim or vcs can do what you just
described.

HTH,
Jim

"geoffrey wall" <wallge@eng.fsu.edu> wrote in message
news:da40ed$3ea$1@news.fsu.edu...
>
> Is anyone aware of a software package that can cross reference vhdl
language
> components and
> instantiations of those components?
> For instance if I see a name of something in a piece of code and I don't
> know where it is defined (or what it does)
> I can then click on that name and be linked to the code where it is
defined.
> another thing that would be helpful is some kind of graphical hierarchy of
> entities, components
> and the like (I don't mean a schematic). something like what is available
in
> visual c++ and other
> software design entry tools where object oriented concepts/relationships
can
> be represented graphically.
> I am dealing with a large set of unfamiliar vhdl with alot of component
> hierchies. I'd like to quickly understand
> and parse through this could with some kind of  tool like i have described
> above.
>
>
> thanks
>
> -- 
> Geoffrey Wall
> Masters Student in Electrical/Computer Engineering
> Florida State University, FAMU/FSU College of Engineering
> wallge@eng.fsu.edu
> Cell Phone:
> 850.339.4157
>
> ECE Machine Intelligence Lab
> http://www.eng.fsu.edu/mil
> MIL Office Phone:
> 850.410.6145
>
> Center for Applied Vision and Imaging Science
> http://cavis.fsu.edu/
> CAVIS Office Phone:
> 850.645.2257
>
>





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