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> I was wondering is there is anyway to code this in verilog so that this is > only written once and I could have the number of itterations, (or > repetitions in this case for the unrolled pipeling) as a parameter? Sure, yes, do it in VHDL! :) The fun part asides, you can only do it in Verilog 2001 (yet I find the VHDL way more elegant) but be sure to check your toolset as not all of them support Verilog 2001, yet.Article: 87026
Yes and no. The real questions is: "safe from what?". State machines just don't go wild out of blue. In fact, this question is very hard to answer. Consider this: you detect an invalid code in the middle of some complex situation, should you only reset the module? Reset your chip? Reset the whole board? Reset the system? In your module, go to a default state? What can you do in the default state? What about the state of all of the output ports in your module just before the failure? Can you just set them back to a default state? What about the other modules that are connected these outputs? What about their internal state?.... It all depends on the situation, the objectives of the whole system design, the probabilities of such failures and the cost you're willing to pay to protect your system from them. Sometimes it is going to be very complex and in some simpler cases, a reset would do the trick... <jjlindula@hotmail.com> wrote in message news:1121201390.616999.306910@o13g2000cwo.googlegroups.com... > Hello, I was curious if anyone can comment on writing safe state > machines in AHDL. I often use One-hot encoding in my state machines and > am curious how safe it is. I set the State Machine setting in Quartus > for One-hot Encoding, does this force all my state machines to be safe. > If I just add the line to my state machine: > > When Others => StateMachine = StateA; -- go back to start > > will the state machine be considered safe? > > thanks, > joeArticle: 87027
Well, I think you should forget about simulating with such testbenches in Quartus. Quartus does not support file i/o and other things you need to do in simulation with a testbench. You said you have access to ModelSim, that's great! There is a toolbox in Matlab that makes a bridge between ModelSim and Matlab (I think it is called "Link for ModelSim"). Write your testbench in Modelsim and call needed functions in Matlab. You can read the docs in the mathsoft webpage. Consider doing the whole thing first in RTL (i.e. before the synthesize). In many occasions you don't need to such a complex simulation for the post-place and route gate-level models of your design if you have done a good job in simulating the RTL version and have followed a good design practice. All you'd need to do in the gait level would be to run a different testbench to catch timing problems and such. Personally, I like those DSP in FPGA designs very much. Well, wish you good luck :) "Paul Solomon" <psolomon@tpg.com.au> wrote in message news:42d30531$1@dnews.tpgi.com.au... > Hi All, > > I am using Quartus and I have acess to Modelsim, and I have been working > on a project that is RF based containing lots of filters and other > demodulation elements. As I have been going along writing each filter etc, > I have been testing it by downloading the finished code to my board and > then looking at the output of a filter etc on a spectrum analyser and > deciding (subjectively) if it looks right or not. I dont feel this is the > right way to go however and I wanted some advise on how you would do test > benching on such a project. I have little experience here so I am sure > that any advise would be helpful. > > I have seen examples using all the testbench directives such as $DISPLAY > etc, but I dont think that Quartus likes these directives being in its > final code. Also I have writted simulation models for Matlab to confirm > the concepts before I write the verilog modules, so if there was someway > of comparing a Matlab module to a Verilog module then that would be > fantastic. > > If anyone could give any advise then that would be most appreciated. > > Regards, > > Paul Solomon >Article: 87028
Antti Lukats wrote: > "Jedi" <me@aol.com> schrieb im Newsbeitrag > news:VC3Be.40$k51.11@read3.inet.fi... > >>Huomenta (o; >> >>Looks like Altera listened to me and released the NIOS2 >>toolchain sources on their ftp server finally (o; >> >>Details for login here, although not up2date: >> >>http://www.altera.com/support/kdb/2000/11/rd11272000_7307.html >> >> >>rick > > > Huomenta > > you are greeting in finnish? jedi aka Richard? Are you from Finnland or? > Name doesnt sound like finnish (mine does). Exactly (o; Just happened I moved here 3 years ago from Switzerland..but flying today back for a job interview in my other field...cisco/juniper (o; > > Altera HAD TODO this. Thats the way it is with open source licenses, you > must agree to them or withdraw all your products that are using them, what > Altera of course can not do, so they are forced to keep the nios tool > sources available as that is the requirement of the licenses they are bound > too. > > > Antti > soovib head päeva köigile (not in Finnish, but in Estonian) > And how does an Estonian end up in Germany? (o; rickArticle: 87029
Hi George, I do the same thing in my designs as you do but when I am out of pins, I use the "Virtual pin = 0n" attribute in quartus. These pins can be imported in Modelsim like a physical device pin. Greetings Markus GMM50 schrieb: > The approach I've taken is to add pins to get the desired signals to > appear as module ports. This works great if I'm simulating sub sets of > the final design. And in the total design these pins will eventually > get optomized away. > > If you get to the top level and need to see pins then you need to get > then to output pins on the device. If you're out of pins I put them > into a mux and this will keep the signals available for viewing. > > This all works great for functional simulatins. > > Good Luck. > george >Article: 87030
http://www.justfuckinggoogleit.com/search.pl?query=edif First link. Cheers, JonArticle: 87031
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:db0h5t$upa$03$1@news.t-online.com... > why is it so that whatever I do, I am stuck with (Xilinx) problems?! I need > urgently, within 2 days to implement a programming solution for XCF08P, > unfortunatly the only devices for whicht the IEEE1532 BSDL files are not > available are exactly the XCFxxP series Platform Flash !!! > > Allmost all other devices have proper ieee1532 files available. For XCF08P > impact is able to generate the .ISC file ok, but when I try to generate a > SVF file from ISC (in order to reverse the ISC commands) then of course > impact complains about missing bsdl files, giving an error, and soon after > that there comes C asserition error > > FATAL_ERROR: WinAPP.C:710 > > then of course follows quick self termination!!! > > nice! thats 3 days after the release of 7.1 SP3 > > Antti > if anyone (in or outside Xilinx) can help in either obtaining the ieee1532 > BDSL files or proper programming specs for XCFP platform flash, I would be > very glad :) > I really dont wanna go reverse engineerinf the SVF files in order to get the > programming algorithm. > http://wiki.openchip.org/index.php/Xilinx:PlatformFlash there are some findings about the Platform Flash - I did think I did damage the chip by using inproper programming sequence, but it happened to be known silicon bug described in confidential Xilinx documents DS123-E03 !!! but I am still unsure if I managed to damage the xcf08p by software as it is failing on verify when programmed with impact as well the programming algorithm (reverse engineered from .SVF files!) works ok for readback and erase, still having problems with actual programming... AnttiArticle: 87032
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:db33me$u8v$05$1@news.t-online.com... > "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag > news:db0h5t$upa$03$1@news.t-online.com... > > why is it so that whatever I do, I am stuck with (Xilinx) problems?! I > need > > urgently, within 2 days to implement a programming solution for XCF08P, > > unfortunatly the only devices for whicht the IEEE1532 BSDL files are not > > available are exactly the XCFxxP series Platform Flash !!! > > > > Allmost all other devices have proper ieee1532 files available. For XCF08P > > impact is able to generate the .ISC file ok, but when I try to generate a > > SVF file from ISC (in order to reverse the ISC commands) then of course > > impact complains about missing bsdl files, giving an error, and soon after > > that there comes C asserition error > > > > FATAL_ERROR: WinAPP.C:710 > > > > then of course follows quick self termination!!! > > > > nice! thats 3 days after the release of 7.1 SP3 > > > > Antti > > if anyone (in or outside Xilinx) can help in either obtaining the ieee1532 > > BDSL files or proper programming specs for XCFP platform flash, I would be > > very glad :) > > I really dont wanna go reverse engineerinf the SVF files in order to get > the > > programming algorithm. > > > > http://wiki.openchip.org/index.php/Xilinx:PlatformFlash > > there are some findings about the Platform Flash - I did think I did damage > the chip by using inproper programming sequence, but it happened to be known > silicon bug described in confidential Xilinx documents DS123-E03 !!! > > but I am still unsure if I managed to damage the xcf08p by software as it is > failing on verify when programmed with impact as well > > the programming algorithm (reverse engineered from .SVF files!) works ok for > readback and erase, still having problems with actual programming... > > Antti > uups! the DS123-E03 is confidential! but I did not include here any info what i obtained from it, only said that the errata that I am seeing is described there, this information is available from the public 'title' of the document as well public info (non conf) : "A test escape has been discovered with the devices named above which for some applications results in device failure during "Power on Reset Activation." Devices that have a VCCint ramp during "Power on Reset Activation" that takes longer than 1ms to reach 1.6V may see failures." the FFFFFFFF as idcode and other erratic behavior are things I discovered myself and made public BEFORE I ever did read the DS123-E03, so that information is NOT derived from the confidential document. I hope this explanation is not necessary, but I just figured out, that I have made public pretty much the info that is also described in a conf. document, again I really have not said anything what I did learn in the DS123-E03, except that this document applies to the problem I have, and this is something that could be guessed from the document title already. The DS123-E03 document is not marked as confidential inside the document itself, and it is FREELY available from xilinx website, but before download there is 'agree' to the confidential statements, hence my long commentary to the issue. Antti PS i personally dont understand this kind of confidentiality clauses. If I have a product that doesnt work properly then I have the right to know why, if the vendor knows it this information should be made available, without the 'Agree' to conf clause. If I would have elected not to agree I would have never known that it was me who did burn the chip, but the chip was having silicon errata known to the chip vendor.Article: 87033
Anyone done a JTAG controller in VHDL or Verilog? I want to use an FPGA to program another JTAG device. Cheers, IrishArticle: 87034
"irish" <decalternate@hotmail.com> schrieb im Newsbeitrag news:1121267183.940988.167760@o13g2000cwo.googlegroups.com... > Anyone done a JTAG controller in VHDL or Verilog? > > I want to use an FPGA to program another JTAG device. > > Cheers, > > Irish sure, but well its 'application dependant' in most cases. if you have a softcore cpu, then TAP master is in simplest form 4 bit wide GPIO port and all the rest is software. without specifics its not possible to help you to choose the solution some sort of TAP master is in somewhere in product support zip files in the www.mesanet.com but its not useable standalone, and when you already have a procesor and speed is not so critical you can just use bit bang GPIO, so there would be no need for the TAP master in hardware AnttiArticle: 87035
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:db34cg$2mu$00$1@news.t-online.com... > "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag > news:db33me$u8v$05$1@news.t-online.com... > > "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag > > news:db0h5t$upa$03$1@news.t-online.com... > > > why is it so that whatever I do, I am stuck with (Xilinx) problems?! I > > need > > > urgently, within 2 days to implement a programming solution for XCF08P, > > > unfortunatly the only devices for whicht the IEEE1532 BSDL files are not > > > available are exactly the XCFxxP series Platform Flash !!! > > > > > > Allmost all other devices have proper ieee1532 files available. For XCF08P > > > impact is able to generate the .ISC file ok, but when I try to generate > a > > > SVF file from ISC (in order to reverse the ISC commands) then of course > > > impact complains about missing bsdl files, giving an error, and soon after > > > that there comes C asserition error > > > > > > FATAL_ERROR: WinAPP.C:710 > > > > > > then of course follows quick self termination!!! > > > > > > nice! thats 3 days after the release of 7.1 SP3 > > > > > > Antti > > > if anyone (in or outside Xilinx) can help in either obtaining the > ieee1532 > > > BDSL files or proper programming specs for XCFP platform flash, I would > be very glad :) its all working now, no thanks to anyone. my issues where somehow related to the V4 in the chain, yes the ES with JTAG errata. Not sure how but it makes some of the commands not working.. when I did see that bsdebug -irscan 1111111111111111 did not return proper values in the impact batch mode I did come suspisious and tested my XCF08P programming algo on different board with newer revision of the XCF08P silicon and no other devices in chain, the non working algo started to work immediatly. AnttiArticle: 87036
>>I think XST would infer a latch from your description, maybe Quartus >>aims to avoid latches and uses a default instead... > > How would a default value differ from a latch? Latch = keep last value, default value = always set to 0 (or 1) if none of the conditions is met (which seems to be what is happening to the OP). Maybe Quartus aims to avoid latches at all costs and adds logic to make the output go to 0 if none the conditions is met. So if you're really absolutely sure you need a latch, then you have to either instantiate it as a primitive or describe it in a way that leaves no doubt it's supposed to be a latch. But, as I said, only speculation... never worked with Quartus, and I know zilch about Altera-FPGAs in general, so I'm guessing here. cu, SeanArticle: 87037
I am having problems programming the FPGAs I have on board. Well I have two FPGAs on board a XC3s400 (Spartan 3) and xc2s200e (Spartan 2e) on board. I have no problems creating the .mcs form the 2 bit files and then using the impact to program......Its just that the FPGAs are not getting programmed.The Done pin remains low.... What could be the reason behind this... Prompt reply appreciated.... Regards, - ShaileshArticle: 87038
"Shai" <shailesh.radhakrishnan@gmail.com> schrieb im Newsbeitrag news:1121281980.936959.244210@g49g2000cwa.googlegroups.com... > I am having problems programming the FPGAs I have on board. Well I have > two FPGAs on board a XC3s400 (Spartan 3) and xc2s200e (Spartan 2e) on > board. I have no problems creating the .mcs form the 2 bit files and > then using the impact to program......Its just that the FPGAs are not > getting programmed.The Done pin remains low.... > > What could be the reason behind this... > > Prompt reply appreciated.... > > Regards, > - Shailesh > something is wrong obviously, can be many reasons.. can you program the FPGA over jtag? does the done pin go high ok? ...then read all the docs about the chain config all over one more and check that everything is ok done not high, is generic error, can be wiring, wrong mode, wrong mcs file anything.. anttiArticle: 87039
i'm just starting out with fpgas and i'm having what's probably a basic
newbie problem. i have the following simple entity:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test1 is
Port ( clk : in std_logic);
end test1;
architecture Behavioral of test1 is
begin process (clk) is
variable i : integer := 0;
begin
if clk = '1' and clk'event then
i := i + 1;
end if;
end process;
end Behavioral;
and i have ISE webpack set to xc2vp2-6ff672 and in the ucf file i have:
NET "clk" LOC = "g14" ;
which i believe is the correct clock pin. when i synthesize that code,
i get the following warning:
Synthesizing Unit <test1>. Related source file is
"C:/temp/test1/test1.vhd". WARNING:Xst:647 - Input <clk> is never used.
Unit <test1> synthesized.
what am i doing wrong?
thanks!
Article: 87040"jeff murphy" <jeff.murphy@gmail.com> schrieb im Newsbeitrag news:1121283762.840799.174370@g47g2000cwa.googlegroups.com... > i'm just starting out with fpgas and i'm having what's probably a basic > newbie problem. i have the following simple entity: > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity test1 is > Port ( clk : in std_logic); > end test1; > > architecture Behavioral of test1 is > begin process (clk) is > variable i : integer := 0; > begin > if clk = '1' and clk'event then > i := i + 1; > end if; > end process; > end Behavioral; > > and i have ISE webpack set to xc2vp2-6ff672 and in the ucf file i have: > > NET "clk" LOC = "g14" ; > > which i believe is the correct clock pin. when i synthesize that code, > i get the following warning: > > Synthesizing Unit <test1>. Related source file is > "C:/temp/test1/test1.vhd". WARNING:Xst:647 - Input <clk> is never used. > Unit <test1> synthesized. > > what am i doing wrong? > > thanks! > 1 designs with outputs are optimized to nothing, its empty ! 2 do not use variable but signals if you can anttiArticle: 87041
Hi as I dont have access to the IEEE1532 original specification unfortunatly I am unable to confirm an potential issue - Xilinx devices are almost all IEEE1532 compliant, the special BSDL files are available for download, only for Platform Flash XCFxxP the IEEE1532 files are missing. I was assuming its only a minor issue and somebody did forgot to upload them, but after succesfully implementing read, erase, programming algos for XCFxxP devices I found that new silicon revisions of XCF08P require the JTAG IDLE state to be defined as IRPAUSE inside the ISC_ERASE command, if the JTAG TAP goes tru RTI state then devices is not erased. to my understanding this special requirement makes the XCFxxP devices non programmable with standard IEEE1532 compliant tools. which of course means that Xilinx will not upload the XCFxxP IEEE1532 files as they can not be made. maybe i am wrong, but I really dont see how the SVF ENDIR IRPAUSE could be incorporated inside the IEEE1532 BDSL file !? could someone with access to IEEE1532 specification clarify the issue? Thanks! Antti PS the SVF files generated by impact 7.1SP3 for the XCF08P, they dont work properly when executed by impact. the JTAG commands are correct but I guess some timimg makes problems.Article: 87042
As far as I remember, Lattice has a reference design on multiple boundary scan port linker, see http://www.latticesemi.com/products/devtools/ip/refdesigns/index.cfm I think this can be used to program other devices through one centralised device. Please correct me if I'm wrong. Luc On 13 Jul 2005 08:06:24 -0700, "irish" <decalternate@hotmail.com> wrote: >Anyone done a JTAG controller in VHDL or Verilog? > >I want to use an FPGA to program another JTAG device. > >Cheers, > >IrishArticle: 87043
Hi, I know virtex-4 has 32 global clock lines and there is a requirement that from any clock region, I can use up to 8 glock lines. Is there any visualized way so that I can see what is the coverage of each clock region for a particular chip? Or some table kind of listing each clock region covering which IO pins? Thanks.Article: 87044
"Luc" <lb.edc@pandora.be> schrieb im Newsbeitrag news:a0uad1psrtooqcvemivkqrbu3hh3svv5e5@4ax.com... > As far as I remember, Lattice has a reference design on multiple > boundary scan port linker, see > http://www.latticesemi.com/products/devtools/ip/refdesigns/index.cfm > > I think this can be used to program other devices through one > centralised device. Please correct me if I'm wrong. > > Luc > > On 13 Jul 2005 08:06:24 -0700, "irish" <decalternate@hotmail.com> > wrote: > > >Anyone done a JTAG controller in VHDL or Verilog? > > > >I want to use an FPGA to program another JTAG device. > > > >Cheers, > > > >Irish > there are only JEDEC files for the those boundary scan linker designs, not much useful at all and I think OP was not looking for this type of thing but TAP master AnttiArticle: 87045
<linq936@hotmail.com> schrieb im Newsbeitrag news:1121287062.568826.315390@g49g2000cwa.googlegroups.com... > Hi, > I know virtex-4 has 32 global clock lines and there is a requirement > that from any clock region, I can use up to 8 glock lines. > > Is there any visualized way so that I can see what is the coverage of > each clock region for a particular chip? Or some table kind of listing > each clock region covering which IO pins? > > Thanks. > look at the docs, for Spartan 3E the global clocks are explained pretty nicely, with color pictures and charts the clocks are not bound to (covering) IO pins, rather there are 8 BUFG muxs that drive 8 lines that enter a single clock quadrant. there are of course limitations of what clock sources can be routed to those BUFGs anttiArticle: 87046
jeff murphy wrote: > i'm just starting out with fpgas and i'm having what's probably a basic > newbie problem. i have the following simple entity: > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; #include <obligatoryDontUseStdLogicArithUseNumericStdInstead.h> > entity test1 is > Port ( clk : in std_logic); > end test1; > > architecture Behavioral of test1 is > begin process (clk) is > variable i : integer := 0; > begin > if clk = '1' and clk'event then > i := i + 1; > end if; > end process; > end Behavioral; > > and i have ISE webpack set to xc2vp2-6ff672 and in the ucf file i have: > > NET "clk" LOC = "g14" ; > > which i believe is the correct clock pin. when i synthesize that code, > i get the following warning: > > Synthesizing Unit <test1>. Related source file is > "C:/temp/test1/test1.vhd". WARNING:Xst:647 - Input <clk> is never used. > Unit <test1> synthesized. > > what am i doing wrong? Well, you've declared i as a variable, and I doesn't get used anywhere, so my guess is that XST optimized it away. XST figures that you weren't doing anything useful with your counter. -aArticle: 87047
surprise surprise, all documents where the name of the new (to be announced this friday?) Lattice non volatile FPGA like PLD device carry a 'confidential' notice, but running google search on machXO there are 2 hits already, one chinese, and one from Aldec who claims that the new update to their tools include support for Lattice machXO already !! I guess its already friday at the place where Aldec HQ is located :), or maybe they just dont care about the confidential clause. good PR for Aldec, I would never had any thoughs about evaluation their tools, now I may even do so! AnttiArticle: 87048
tns wrote: > Mike Treseler wrote: > > > tns1 wrote: > > > >> Many of the nodes I want to probe seem unavailable in the simulation. > >> They are either optimized away, or refuse to show up in the simulation > >> window even when selected in the vwf. > > > > > > For complex designs, it is common practice > > to write HDL source and simulate *that* using > > a vhdl simulator, before running Quartus. > > > > -- Mike Treseler > > Sounds like a good thing to do. Which tools provide this 'source level' > simulation? Any free ones? You should be able to download a free version of ModelSim from Altera's web site. -aArticle: 87049
tns1 wrote: > GMM50 wrote: > > > The approach I've taken is to add pins to get the desired signals to > > appear as module ports. This works great if I'm simulating sub sets of > > the final design. And in the total design these pins will eventually > > get optomized away. > > > > If you get to the top level and need to see pins then you need to get > > then to output pins on the device. If you're out of pins I put them > > into a mux and this will keep the signals available for viewing. > > > > This all works great for functional simulatins. > > > > Good Luck. > > george > > > OK, but what about when the signal looks OK in the sim, but it does not > appear on the chip? Maybe it got optimized away for a reason? -a
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