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abgoyal@gmail.com wrote: > Hi, > > I have been trying to implementa a 256-deep, 8-bit wide ROM as a BRAM > in Xilinx Virtex 4 and Spartan 3(ISE7.1sp2). Prefering to have it > inferred instead of instantiating a macro, i wrote it out as a case > statement in verilog. ISE correctly infers a block RAM for it. > > My problem is i want to do two simultaneous reads from the same ROM > (the reads are done on independent clocks). If i implement this as two > seperate case statements, even with the exact same data, ISE infers two > blockRAMs for them, leaving the second port of each unused. > [...] > I know i can work around it by instantiating a dualport BRAM, i was > just wondering if there was a way to have ISE infer it. Howdy Abhishek, You've asked an age-old question. The short answer is maybe, depending on the synthesis tool and if you can find the magic word. You'll notice from the numerous previous discussions that it is not exactly clear-cut on how to do it: http://groups.google.com/groups?q=infer+dual+port In general, the answer seems to be that doing anything more than one read and one write on a single BRAM can't be inferred reliably, although Synplify's latest literature seems to imply they can handle a bit more than that: http://www.synplicity.com/literature/pdf/inferring_blockRAMs.pdf By searching the web or Xilinx's site, we find that Xilinx documents a recommended way to code up a dual-port RAM with independent read clocks for XST: http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/xst/xst0027_5.html#wp422120 or http://tinyurl.com/dk55f If you scroll down a little, you'll find ways to initialize the BRAM. I see that it says you can't infer the initialization in XST when using Verilog for some reason - you'll have to do so using the INIT_xx property in the .ucf file (or some other way). Hmmm... except that the constraints guide for INIT_xx does point out a way to initialize a BRAM in Verilog, so maybe it is just XST that can't: http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/cgd/cgd0103_64.html#wp240143 or http://tinyurl.com/c9cru As you can see, there isn't just one place to go to find the answer. The chances that these structures are portable across synthesis tools (much less device vendors) seems exceedingly low. Good luck, MarcArticle: 88751
I found a way to make an 35 x 35 signed multiplier with four MULT18X18 in the application note XAPP467 (on page 6). I'm going to test that. "Thomas Entner" <aon.912710880@aon.at> skrev i meddelandet news:43103ac1$0$27168$91cee783@newsreader01.highway.telekom.at... > As far as I know, this should be possible with 4 multipliers, if everything > is unsigned. I could imagine that you also get away with 4 signed > multipliers, if you cut a bit or two from your a and b. > > Regards, > > Thomas > > www.entner-electronics.com > > "Bubba" <blabla@bredband.net> schrieb im Newsbeitrag > news:431037f6$0$18636$14726298@news.sunsite.dk... > > Multiplier > > > > > > > > Is there a good algorithm (small) to multiply two 36 bit "signed" numbers > > to > > get a 72 bit result. > > > > > > > > Is it possible to divide the 36 bit numbers into 18 bit parts and multiply > > them separately and after some shifting add the results? > > > > > > > > I would like to instantiate the MULT18X18 in the Spartan3 for this. > > > > > > > > When I write it strait like this without any specific instantiation: > > > > > > > > library IEEE; > > > > use IEEE.STD_LOGIC_1164.ALL; > > > > use IEEE.STD_LOGIC_ARITH.ALL; > > > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > > > > > > entity test is > > > > Port ( a : in std_logic_vector(35 downto 0); > > > > b : in std_logic_vector(35 downto 0); > > > > q : out std_logic_vector(71 downto 0)); > > > > end test; > > > > > > > > architecture Behavioral of test is > > > > > > > > begin > > > > q <= signed(a)*signed(b); > > > > > > > > end Behavioral; > > > > > > > > > > > > It uses 9 MULT18X18!!!!! > > > > > > > > > > > > > > > >Article: 88752
Matthew Plante wrote: > I just upgraded to ISE 7.1.03i. My old 6.3i design used some DCMs in a > "not so legal" fashion, where I had CLKFX_DIVIDE = 33, and CLKFX_MULTIPLY = > 32. My old version of ISE (6.3i) would actually accept the divide value and > produce a working bit stream. 7.1 on the other hand actually complains > during the mapping phase. Is there a way to disable the checking of this > and force it to accept those values? Howdy Matthew, Assuming 31/32 isn't an option instead, and assuming this just for lab use, and assuming you can't go back to using 6.3i (are you noticing any better results with 7.1i?), you might open a webcase with Xilinx and see if they'll tell you the hidden command line switch or environment variable to bypass the CLKFX range checking, or if they have some other way that they might let you do it. If you manage to get past MAP (and PAR), you may have to disable the DRC checking in bitgen as well - just have to try it and see. Good luck, MarcArticle: 88753
Rob wrote: > I'm trying to implement a SERDES interface within a Cyclone device. I've > set it up using a PLL, DDIO, a couple of shift registers, and some output > DFF's. I'm seeing some timing issues. How do you compensate for shift > (between the data clock and the serial data) that is caused due to the time > the PLL takes to lock to the incoming clock? > [...] Howdy Rob, Your question doesn't make sense to me. The clock should be running continuously while you want to transfer data, so it only has to lock once (or at least, once in a blue moon). And once it is locked, the PLL generally removes any "shift" (aka propagation delay) associated with using the PLL or global clock network, creating the proper alignment to sample incoming data. I'm sure Altera has some appnotes on doing stuff like this. Ah, here is but one: http://www.altera.com/literature/an/an356.pdf Also, what do you mean that you're seeing timing issues? Timing issues, to me, invokes images of having too many levels of logic to fit within a clock period (or in some cases on a V4, any levels of logic :-). That is a completely independent issue from the PLL alignment or locking. Have fun, MarcArticle: 88754
Hello Everyone,
I am new to Xilinx and the whole FPGA thing and this might be a very
stupid problem that I am facing. Anyways Here it goes. I am trying to
write a simple counter program using ISE Webpack 7.1. I write the code
using language templates (verilog)then I check the syntax and
everything is fine till this point.
Then I make a testbench wave form and I can also see the expected
results dialog box. Next step is I use ModelSim XE starter free version
to simulate behavioural model. It opens up ModelSim automatically and
this is where after running for a few seconds it stops. Below are the
few messages that I am posting.......
Basically in the tfw window in ModelSim it stops at $stop;. Please see
below.
Is there something that I am missing. Thanks a lot in advance.
THIS IS TBCounter.tfw WINDOW
module TBCounter_3try;
reg CLOCK = 1'b0;
reg DIRECTION = 1'b0;
wire [3:0] COUNT_OUT;
parameter PERIOD = 40;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 200;
initial // Clock process for CLOCK
begin
#OFFSET;
forever
begin
CLOCK = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) CLOCK = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
counter UUT (
.CLOCK(CLOCK),
.DIRECTION(DIRECTION),
.COUNT_OUT(COUNT_OUT));
integer TX_ERROR = 0;
initial begin // Open the results file...
#2040 // Final time: 2040 ns
if (TX_ERROR == 0) begin
$display("No errors or warnings.");
end else begin
$display("%d errors found in simulation.",
TX_ERROR);
end
$stop;
end
initial begin
// ------------- Current Time: 290ns
#290;
DIRECTION = 1'b1;
THIS IS IN THE TRANSCRIPTS WINDOW
# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
# do TBCounter_3try.fdo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vlog 6.0a Compiler 2004.11 Nov 10
2004
# -- Compiling module counter
#
# Top level modules:
# counter
# Model Technology ModelSim XE III vlog 6.0a Compiler 2004.11 Nov 10
2004
# -- Compiling module TBCounter_3try
#
# Top level modules:
# TBCounter_3try
# Model Technology ModelSim XE III vlog 6.0a Compiler 2004.11 Nov 10
2004
# -- Compiling module glbl
#
# Top level modules:
# glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps
TBCounter_3try glbl
# Loading work.TBCounter_3try
# Loading work.counter
# Loading work.glbl
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
# .main_pane.workspace
# .main_pane.signals.interior.cs
# No errors or warnings.
# Break at TBCounter_3try.tfw line 55
# Simulation Breakpoint: Break at TBCounter_3try.tfw line 55
# MACRO ./TBCounter_3try.fdo PAUSED at line 14
Article: 88755Hello , It was a simple error from my side. I included the Unisim libraries between synthesis translate_off and translate_on. Once I remvoed those it works fine ThanksArticle: 88756
$stop is a command to halt the simulation and thats the reason your simulation halts.Article: 88757
But I am not giving it anything. Once I say simulate behavioural model it automatically opens up ModelSim, Starts simulation and then tells me that simulation stopped. So I dont know whats the problemArticle: 88758
Hallo, after I have added a software application project into edk, I can choose the option: "mark to initialize bram". If I check it, the software would be located into bram, so after updating bitstream it is loaded as soon as bitstream is downloaded into fpga. But which bram is initialized? the bram connected to ilmb controller? or if I add opb bram controller, the bram connected to opb controller? or a free resource external to project? Many Thanks MarcoArticle: 88759
Since you are using the ISE waveform editor to create the testbench it automatically inserts that statement. Probably there would be some option in the simulation properties where you can change it.Article: 88760
learnfpga wrote:
> But I am not giving it anything.
The testbench generator is writing the code for you.
Writing your own testbench code makes these
things easier to debug.
-- Mike Treseler
Article: 88761There is another thing that I wanted to ask. I have installed ISE Webpack 7.1. Doesn't it come with ISE simulator? Becasue I when I look in Process View window I only see ModelSim. Is there something I have to do to invoke ISE simulator? ThanksArticle: 88762
Marc Randolph wrote:
> In general, the answer seems to be that doing anything more than one
> read and one write on a single BRAM can't be inferred reliably,
True. The advantage of using separate read
and write ports is that you don't have
to think about handling the case of
simultaneous writes to the same address.
The reason synthesis punts on dual write ports
is that the template model would have to
exactly describe the BRAM arbitration scheme
as well as the RAM array. Otherwise sim
would not match synthesis in all cases.
The OP actually wants a ROM with two read ports.
The choices are:
1. Instance the vendor dpram and tie off
the write controls.
2. Infer two roms from the vendor template
using a constant vector array. If you
have BRAM to spare, this is the easy way out.
-- Mike Treseler
Article: 88763http://www.xilinx.com/ise/products/webpack_config.htmArticle: 88764
I am a newbie in Xilinx FPGA and am trying to prototype my own architecture. I tried the tutorial about stopwatch. Everything is OK. Then I tried a simple design "3-bit counters". The behavioral model and translate model works. But the post-map model doesn't work. I don't know why? Here I did't use DCM. I have the clk pin feed to my counter directly. Could this cause a problem?Thanks,Article: 88765
Dear All, After I take a look at the schematic view of post-map RTL code, it seems "reset" signal is connected to the "clk" of FF and "clk" signal is connected to the "reset" of FF. What is wrong there?How can I fix this problem?Thanks,Article: 88766
Dear all, In ASIC design, clock skew can be solved by using Clock tree generation. How does FPGA solve it?Use the clock tree too?How? Thanks, EthanArticle: 88767
Hi ,I've been working on this for three days and I got lost in the sea of XST warnings and errors .... I'm really lost.. In short ,what I want is to design a combinational module that will interface between the datapath of a cpu with blockram's bidirectional datalines..the module should include an input port and outport both connected to register file's read and write ports, and a bidirectional port connected to the ram's datalines... Target device is Spartan 3. PLZ HELP!Article: 88768
Hi, I am going to do a research project which needs to cancel feedback data signal of an amplifier. The data signal frequency is 10MHz which is not audio type. I have searched the internet that most of the feedback algorithm are for audio signal, which allows a little distortion in the output signal. However, as the input data type is not audio, the output data must not be distorted in any way. I have an idea, but not known whether the direction is OK. Could someone give me advices? Firstly, I need to make a matched filter of length n to match the input signal at a defined time, which is the time after sending out nth-tap data. Because of high frequency and long path reflection, the feedback signal should have a phase change, so I need also check the matching within one period of the signal. If I employ 40MHz sampling, I need to take into account 4 sampling points more (40/10). The matching amplitude is then used to calulate attentuation factor of matching signal, which is used to substract the input signal to retrieve the real input signal. The algorithm should be implemented using FPGA as DSP chip can not handle such fast signal.Article: 88769
To all,
Is it possible to create a user defined logic that is both a master
and a slave peripheral? What I want to implement is a Master peripheral
which makes a request to this so-called "Master/Slave" peripheral that
requests for data from the SRAM. This master peripheral first requests
for an address pointer to where the data is to be retrieved from SRAM
from the "Master/Slave" peripheral and this same peripheral is then
responsible for fetching the information from the SRAM controller slave
and then reporting the retrieved data back from the original master
which made the request. Is it possible to do this, or does SOPC
builder always assume a peripheral is always a slave or a master? Any
pointers would be helpful
Cheers,
Pino
Article: 88770On 27 Aug 2005 15:46:02 -0700, "yijun_lily@yahoo.com" <yijun_lily@yahoo.com> wrote: >In ASIC design, clock skew can be solved by using Clock tree >generation. How does FPGA solve it?Use the clock tree too?How? In FPGAs the clock tree is already in the design. You don't have to do anything extra to use it as long as you feed the clock into the clock tree correctly. This alas precludes interesting clock manipulation tricks like clock gating etc except at a very global level.Article: 88771
You need a better description than this in order for someone to help. You might want to consider sending the VHDL or verilog. but you probably haven't coded it correctly with the right 'always @ (posedge clk)' Simon <yijun_lily@yahoo.com> wrote in message news:1125177858.566707.241190@g47g2000cwa.googlegroups.com... > Dear All, > > After I take a look at the schematic view of post-map RTL code, it > seems "reset" signal is connected to the "clk" of FF and "clk" signal > is connected to the "reset" of FF. What is wrong there?How can I fix > this problem?Thanks, >Article: 88772
Good posts, Proabably the best thread I've read through in a long while. Serious stuff, with real numbers. Thanks for all who posted. I still claim that by instantiating more than one core in an FPGA, they still win oven even the best uP, however. Massive parallelism is of course nearly impossible to use effectively, as there is no language that preserves if operations could be done in parallel. We are stuck with a "paper tape" programming mentality in a flash memory age. Austin gantlord wrote: > Oops, forgot to say where I'm getting this from: > > Keith Underwood from Sandia Labs has been looking at this sort of > stuff. I'm just parroting it out here for you guys (I wouldn't anyone > thinking I'd been guilty of an original thought). > > R >Article: 88773
well you can parallel ifs if you have enough gates... just do every possible combination and pick the correct one... Isn't that how they cracked DES ? I would have to agree with Austin about the rest... being both a programmer and a hardware engineer... I know what's good for what.. you can't beat hardware for shear grunt... it doesn't matter how fast the processor is.. clock for clock the dedicated hardware will beat it.. sometime even not clock for clock... the hardware can be dedicated to a single task which is extremely efficient, Processors by nature aren't... Processors may be able to do 50 million FLOPS, but they also need to be able to get the instructions and data from memory. and then they have loops and if your running Linux or windows... they are trying to do so much work that they get bogged down. In saying this, there are FPU's up to the grade even if they are specialized ... your average 3D graphics processor will leave an x86 for dead FPU wise... they are by far the most impressive floating point units in mass production today (The X800 does 200 billion FLOPS). Simon "austin" <austin@xilinx.com> wrote in message news:derheh$b5t2@cliff.xsj.xilinx.com... > Good posts, > > Proabably the best thread I've read through in a long while. > > Serious stuff, with real numbers. > > Thanks for all who posted. > > I still claim that by instantiating more than one core in an FPGA, they > still win oven even the best uP, however. > > Massive parallelism is of course nearly impossible to use effectively, > as there is no language that preserves if operations could be done in > parallel. > > We are stuck with a "paper tape" programming mentality in a flash memory > age. > > Austin > > gantlord wrote: > > > Oops, forgot to say where I'm getting this from: > > > > Keith Underwood from Sandia Labs has been looking at this sort of > > stuff. I'm just parroting it out here for you guys (I wouldn't anyone > > thinking I'd been guilty of an original thought). > > > > R > >Article: 88774
Hallo, I need to run a small software into bram. The trouble is with function: XUtil_MemoryTest32 It increases software size too much. There is something similar, but size optimized? There are compiler parameters to reduce size? Many Thanks Marco
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Threads starting:
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