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BobJ wrote: > which is your primary FPGA supplier? I cant go back to Xilinx again. We're a purely Xilinx shop, I'm afraid :) (Sorry about the late reply - I've been overseas for a few days) JeremyArticle: 84851
Hi -
Every once in a while, someone on this group asks about FSM design
tools, and invariably StateCAD is mentioned. Xilinx bought this
graphical FSM entry tool a while back, and continues to offer it as
part of ISE. I've never been terribly enthusiastic about the tool,
mostly because coding an FSM in Verilog just isn't that hard.
But after years of hand-coding FSMs, then drawing FSM bubble diagrams
with Visio, I decided to take another look at StateCAD, to see if I
could eliminate the need to make two sets of revisions--Verilog and
Visio--every time I modify an FSM. And after a couple of hours of
fooling around with the latest incarnation of StateCAD, I found that I
could produce an FSM with the features I wanted in a fairly
straightforward way.
But there is one significant problem: the Verilog code emitted by
StateCAD is wrong.
When I generate a one-hot FSM from a StateCAD drawing, the state
register portion looks something like this:
always @(posedge clk_50 or posedge ga_reset)
begin
if ( ga_reset ) STATE1 = 0;
else STATE1 = next_STATE1;
end
always @(posedge clk_50 or posedge ga_reset)
begin
if ( ga_reset ) STATE2 = 0;
else STATE2 = next_STATE2;
end
always @(posedge clk_50 or posedge ga_reset)
begin
if ( ga_reset ) STATE3 = 0;
else STATE3 = next_STATE3;
end
...and so on. (Aside: The asynchronous reset is intentional and OK.
There's also a synchronous reset that you can't see in this code
fragment.)
Note that each state bit is updated in its own always block, using
blocking assignments.
Synthesis-wise, no problem: any synthesis tool will recognize these
constructs and produce the correct logic. But a simulation tool can
evaluate these always blocks in any order, meaning there's no
guarantee that the state FFs will be updated in a race-free fashion.
This is exactly the kind of coding faux pas that every novice Verilog
writer is instructed to avoid.
Xilinx Answer Record 16616 admits to the simulation problem. But it
also says, "...Verilog State Machine code generated by StateCAD might
not be optimal." That's putting it kindly. I'm not 100% sure that
Xilinx realizes the tool is broken in any flow that includes
functional simulation, which these days includes just about any flow
for a non-trivial design. I guess I could tell them, but it looks
like someone already did, almost two years ago.
I'm probably going to write a Python script to correct the emitted
code. Anyone have a better solution? And you can assume that "Don't
use StateCAD" is already at the top of the list of fixes being
considered.
Thanks,
Bob Perlman
Cambrian Design Works
Article: 84852Hi Alan, > I've just moved from Quartus 4.0 to 5.0, re-generated a Nios design > under SoPC Builder, and run the design through Quartus. > The timing has gone from almost 90Mhz before to 72Mhz now. > Anyone experienced similar speed-downs? By any chance, did you set an aggressive timing constraint? If not, then Quartus (as of some version between 4.0 and 4.2 -- I forget which) will automatically stop working hard on timing once it sees that your design (a) meets timing and (b) will likely be able to route. This saves you compile time, but also means that push-button compilation without a tight constraint may show a slowdown. If this is not the issue, please provide some more information, such as what Nios options you selected and what device you are targeting. Thanks, Paul Leventis Altera Corp.Article: 84853
Ankit Raizada wrote: > My two cents are that i like to do breakup up my design in to modules > first and come up with their interfaces and a rough schematic diagram > then the deeper design and implementation is done in HDLs each module > simulated tested etc then i fit them in the original schematic design. > In this way i get a birds eye view of the whole design and the beauty > of the schematic diagrams as well as abstraction of HDLs. > I draw a block diagram of the major components as well before putting stylus to papyrus & generating HDL code.Article: 84854
Hi Symon, Sorry for taking so long to reply. > I want to send bits a_1, a_2, a_3, a_4 etc. on I/O LVDS_A > I want to send bits b_1, b_2, b_3, b_4 etc. on I/O LVDS_B > I use the serdes to do this. Can I ensure that a_n appears at (more or > less) > the same time as b_n? I.e. that the shift registers in the two serdes are > aligned? That's what the SERDES block is for. You just need to instantiate a altlvds_rx (receiver) or altlvds_tx (transmitter) with the number of channels you want in the link. Each of the channels will share a common PLL. Therefore, they share a common clock, and the enable pulses derived from that clock. And if you want to give the manual another stab ;-), I've been told that volume 2, chapter 5 of the Stratix II handbook, "High-Speed Differential I/O Interfaces with DPA in Stratix II Devices" http://www.altera.com/literature/hb/stx2/stx2_sii52005.pdf is helpful. Figures 5-2, 5-11 and 5-12 are most applicable in this case. Regards, Paul Leventis Altera Corp.Article: 84855
Does the VHDL spaghetti exist? I do see many ugly schematic drawings. Well anyway, learning the hardware description language is not that hard if you are the schematic guru, for ones with such experience it may take 1-2 weeks to get the basic and more...and that's enough to do the rocknroll :)Article: 84856
Hi *, I keep coming across answer records and script files containing the setting of undocumented environment variables, such as XIL_ROUTE_ENABLE_DATA_CAPTURE, XIL_BITGEN_VIRTEX2ES, XIL_XST_HIDEMESSAGES and so on. Is there a complete list of these hidden cheat codes? Any "official" documentation at all? Whenever I'm stuck in a design, and find out that some magical environment variable just fixes my problem, I wonder if maybe there is something like the Holy Grail... something like the "Answer to Life, the Universe and Everything", as in a "XIL_MAKE_EVERYTHING_WORK"- or "XIL_42"-variable or something. Haven't found it but thought I could ask. cu, SeanArticle: 84857
Sean Durkin <smd@despammed.com> wrote: > Hi *, > I keep coming across answer records and script files containing the > setting of undocumented environment variables, such as > XIL_ROUTE_ENABLE_DATA_CAPTURE, XIL_BITGEN_VIRTEX2ES, > XIL_XST_HIDEMESSAGES and so on. > Is there a complete list of these hidden cheat codes? Any "official" > documentation at all? > Whenever I'm stuck in a design, and find out that some magical > environment variable just fixes my problem, I wonder if maybe there is > something like the Holy Grail... something like the "Answer to Life, the > Universe and Everything", as in a "XIL_MAKE_EVERYTHING_WORK"- or > "XIL_42"-variable or something. Haven't found it but thought I could ask. One first step to know about all variables: > cd ise-7.1/bin/lin > strings * | grep ^XIL_ 607 hits! Also some are error messages... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 84858
Uwe Bonnes wrote: > One first step to know about all variables: > >>cd ise-7.1/bin/lin >>strings * | grep ^XIL_ > > 607 hits! Also some are error messages... Not bad! Should've thought about that... Looks like the variable I'm supposed to set doesn't even exist in ISE6.3, even more fun... ;) cu, SeanArticle: 84859
Hi, Has anyone got NIOS software to boot from Flash? I'm working on a Stratix II-based design with onboard NIOS and peripherals (16MB flash, Ethernet, SDRAM etc). The Flash, Ethernet, and SDRAM components are wired to the Stratix-II via an Avalon tri-state bus, similar to the design on the Stratix Edition Nios development kit. A single Nios CPU core is running at 50MHz.on the Stratix II. I plan to have both the FPGA firmware and NIOS software stored in Flash in our end application. So far the FPGA firmware appears to load fine, on boot up a CPLD configures the FPGA with data stored in Flash. I can then execute my NIOS application by loading in software using Quartus II. To boot up my application software from Flash I had previously set the Nios's reset address to "ext_flash" with an appropriate address offset. I then write into Flash my software application's "ext_flash.flash" file which is generated after software compilation. I assert and keep the Nios in CPU reset, run Signal Tap, and deassert CPU reset. What I see happening is that the CPU does appear to read the software application data from Flash at the correct address. The data looks correct too, at least to the extent of the small period of time covered by Signal Tap. My software application does not execute properly, as I see the Nios then reading from roughly 0x380000 to perhaps the end of the flash device and repeating continually. I have attempted to use elf2flash to manually create my own software flash file, specifying the flash boot loader from " ../componenta/altera_nios2/boot_loader_cfi.srec" but this produced the same result. Is this the correct boot loader? In my software application's system library, I have set the Program memory (.text), Read-only data memory (.rodata), and Read/write data memory (.rwdata) to sdram. I intend for this code to actually execute in SDRAM after being copied from Flash by the bootloader. I'd like to hear from anyone if there is a problem with this set up. Cheers, Joseph TanArticle: 84860
Hi, thanks to the kind people on this group, I finally got a simulation of the ML310 board going. But I have another problem: I used the simulation process described in the Platform Studio User guide. I generated and executed the sim-environment from XPS and ran a behavioural simulation in the ModelSim simulator. The design I am simulating is a standard generated design from XPS. (no caching and only DSOCM enabled) The problem is that I don't see any bus activity during the simulation. All the registers seem to be set to the right values (dsarcvalue, dscntlvalue etc.), but the DSOCM,PLB and OPB buses don't do anything. I forced the system/sys_clk_pin and the system/sys_rst_pin as stimuli. (Not the sys_clk and sys_reset as stated in the manual, these signals do not exist in the design) I was under the impression that with this simulation system, I should see the program being executed. Is this at all possible, and if so, any ideas of what I should do to get some action going? Any help would really be appreciated, Jim TuilmanArticle: 84861
I have a custom board with an altera EP1C12, a flash memory and a
MT48LC4M32B2 SDRAM memory.
Timings I set in SOPC builder are the default timings for this part.
When I set the value 0x00000000 to a particular location (it doesn't
matter which location I choose), if I read back the same location after
5 ms (milliseconds!) I find 0x00000000; after 10ms some of the bits go
to value 1; incrementally all the bits go to 1, and if I read it after
15ms, I read 0xffffffff.
I tried increasing the refresh frequency (from 15.625us to 3us) with no
success.
here is the test code, run from on-chip memory:
#include <io.h>
#include <stdio.h>
#include "system.h"
int main()
{
long i,j,k;
long test,last;
long values[32];
long times[32];
for(i=0;i<32;i++)
{
values[i]=0;
times[i]=0;
}
for(i=0;i<10;i++)
printf("Hello From Nios\n\n");
IOWR_32DIRECT(SDRAM_BASE, 3578, 0x00000000);
last=0;
i=0;
j=0;
while(1)
{
//test=sdram[3578];
test=IORD_32DIRECT(SDRAM_BASE, 3578);
if(test!=last)
{
times[j]=i;
values[j]=test;
last=test;
j++;
}
if (test==0xffffffff)
{
for(k=0;k<32;k++)
printf("\nTime:%8ld us Value: %8x",times[k],values[k]);
break;
}
usleep(i);
i+=1; //INCREMENT x us
}
return 0;
}
here is the output:
Time: 175 us Value: 8
Time: 180 us Value: 400008
Time: 184 us Value: 40000c
Time: 187 us Value: c0000c
Time: 189 us Value: c4000c
Time: 190 us Value: 40c4000c
Time: 191 us Value: 44c4200c
Time: 194 us Value: 44d4202c
Time: 195 us Value: 44d4203c
Time: 196 us Value: 44f5203c
Time: 199 us Value: 54f7203c
Time: 202 us Value: 54f7223c
Time: 203 us Value: 74f7223c
Time: 204 us Value: 7cf7223c
Time: 205 us Value: 7cf72a7c
Time: 206 us Value: 7cf7aa7d
Time: 209 us Value: 7cf7ea7d
Time: 210 us Value: 7df7ea7d
Time: 215 us Value: 7df7ee7d
Time: 219 us Value: fdf7ee7d
Time: 228 us Value: fdf7eefd
Time: 242 us Value: fdf7eeff
Time: 253 us Value: fdf7efff
Time: 254 us Value: fdffffff
Time: 255 us Value: ffffffff
Time: 0 us Value: 0
Time: 0 us Value: 0
Time: 0 us Value: 0
Time: 0 us Value: 0
Time: 0 us Value: 0
Time: 0 us Value: 0
Time: 0 us Value: 0
if instead I using a delay increment of 100us at a time (see line "i+=1;
//INCREMENT x us") , the problem appears later than when I use an
increment of 1us:
Time: 2500 us Value: 8
Time: 2600 us Value: 40000c
Time: 2700 us Value: 44f4203c
Time: 2800 us Value: 7cf7227d
Time: 2900 us Value: 7df7ea7d
Time: 3000 us Value: fdf7ee7d
Time: 3100 us Value: fdf7eefd
Time: 3300 us Value: fdf7efff
Time: 3400 us Value: ffffffff
Time: 0 us Value: 0
Time: 0 us Value: 0
Time: 0 us Value: 0
...
Another important thing that should be taken into account is that I can
run no software from SDRAM since its content changes (to 0xFFFFFFFF)
Any clue?
Thanks in advance,
BQ
Article: 84862Hi, I'm implementing a ddr-fifo buffer and when viewing the synthesis report on the ddr-fifo buffer by itself the timing summary is: --------------- Speed Grade: -10 Minimum period: 6.976ns (Maximum Frequency: 143.343MHz) Minimum input arrival time before clock: 6.546ns Maximum output required time after clock: 4.543ns Maximum combinational path delay: No path found When adding a 5 bit counter and 4 if statements that changes the values of wr_en and rd_en on the ddr-fifo the timing summary is: --------------- Speed Grade: -10 Minimum period: 13.964ns (Maximum Frequency: 71.611MHz) Minimum input arrival time before clock: 6.546ns Maximum output required time after clock: 4.543ns Maximum combinational path delay: No path found The maximum frequency is about half of the original! Is this due to the fact that it take some time before the wr_en and rd_en pins in the fifo is effective? So there might be some error on the first and last bits of data. For me it's okay that the head and tail is corrupt, it is the bits in beteween that are important to my project. Could I then forget about this timing summary and run the system at the higher clock frequency? CheersArticle: 84863
I plan to run it at 100 MHz... using a DCM to generate 250 MHz and IDDR memories that can receive data at 500 MHz..Article: 84864
Some of these variables come and do go. Usually it comes in as a quick fix then gets properly incorporated into the tools on the next release. When incorporated they support gets dropped. It can be a pain to script lovers but as I am not one of those I don't usually find this as an issue. John Adair Enterpoint Ltd. - Home of MINI-CAN. CAN Bus Development Board. http://www.enterpoint.co.uk "Sean Durkin" <smd@despammed.com> wrote in message news:429c20ad$1@news.fhg.de... > Uwe Bonnes wrote: >> One first step to know about all variables: >> >>>cd ise-7.1/bin/lin >>>strings * | grep ^XIL_ >> >> 607 hits! Also some are error messages... > Not bad! Should've thought about that... > > Looks like the variable I'm supposed to set doesn't even exist in > ISE6.3, even more fun... ;) > > cu, > SeanArticle: 84865
Joseph Tan wrote: > Hi, > > Has anyone got NIOS software to boot from Flash? > > I'm working on a Stratix II-based design with onboard NIOS and > peripherals (16MB flash, Ethernet, SDRAM etc). The Flash, Ethernet, and > SDRAM components are wired to the Stratix-II via an Avalon tri-state > bus, similar to the design on the Stratix Edition Nios development kit. > A single Nios CPU core is running at 50MHz.on the Stratix II. > > I plan to have both the FPGA firmware and NIOS software stored in Flash > in our end application. So far the FPGA firmware appears to load fine, > on boot up a CPLD configures the FPGA with data stored in Flash. I can > then execute my NIOS application by loading in software using Quartus > II. > > To boot up my application software from Flash I had previously set the > Nios's reset address to "ext_flash" with an appropriate address > offset. I then write into Flash my software application's > "ext_flash.flash" file which is generated after software compilation. I > assert and keep the Nios in CPU reset, run Signal Tap, and deassert CPU > reset. > > What I see happening is that the CPU does appear to read the software > application data from Flash at the correct address. The data looks > correct too, at least to the extent of the small period of time covered > by Signal Tap. My software application does not execute properly, as I > see the Nios then reading from roughly 0x380000 to perhaps the end of > the flash device and repeating continually. I have attempted to use > elf2flash to manually create my own software flash file, specifying the > flash boot loader from " > ../componenta/altera_nios2/boot_loader_cfi.srec" but this produced the > same result. Is this the correct boot loader? > > In my software application's system library, I have set the Program > memory (.text), Read-only data memory (.rodata), and Read/write data > memory (.rwdata) to sdram. I intend for this code to actually execute > in SDRAM after being copied from Flash by the bootloader. > > I'd like to hear from anyone if there is a problem with this set up. Never used the NIOS2 IDE though...just normal Linux/OSX environment for this (o; So is the .data segment also in your flash and do you copy it to SDRAM after reset? Do you also clear .bss section? I normally generate code for run from SDRAM/SRAM for better performance and relocate the whole code to RAM after reset. Setup initial SP and just call main() in RAM (o; You might want to look at u-boot source code how it is done there... jediArticle: 84866
Kalle wrote: [reformatted to make original readable]: > Hi, I'm implementing a ddr-fifo buffer and when viewing the synthesis > report on the ddr-fifo buffer by itself the timing summary is: > > --------------- Speed Grade: -10 > Minimum period: 6.976ns (Maximum Frequency: 143.343MHz) > Minimum input arrival time before clock: 6.546ns > Maximum output required time after clock: 4.543ns > Maximum combinational path delay: No path found > > When adding a 5 bit counter and 4 if statements that changes the values > of wr_en and rd_en on the ddr-fifo the timing summary is: > > --------------- Speed Grade: -10 > Minimum period: 13.964ns (Maximum Frequency: 71.611MHz) > Minimum input arrival time before clock: 6.546ns > Maximum output required time after clock: 4.543ns > Maximum combinational path delay: No path found > > The maximum frequency is about half of the original! > > Is this due to the fact that it take some time before the > wr_en and rd_en pins in the fifo is effective? So there might > be some error on the first and last bits of data. If you open up timing analyzer, it should tell you what is causing the timing violation. Doing anything except that is just making guesses. Guesses like: Do you have a PERIOD constraint set in your .ucf file? It's kinda strange that your input and output delays are as high as they are. Are the IOB FF's being used? Without seeing the VHDL or timing analyzer report for this path, it is impossible to say what is wrong. It seems safe to say that you added a level of logic, but doing so should probably not have slowed things down as much as it looks like it did - so something else is probably up. > For me it's okay that the head and tail is corrupt, it is the > bits in beteween that are important to my project. Are you sure about that? > Could I then forget about this timing summary and run the system > at the higher clock frequency? You generally don't want to ignore the timing summary unless you have a very good reason to do so. Although the numbers it provides are generally conservative, you can't rely on anything except what the timing reports give you. > I plan to run it at 100 MHz... using a DCM to generate 250 MHz and > IDDR memories that can receive data at 500 MHz.. I think you mean that your input clock is 100 MHz, but you want to run your logic at 250 MHz, with the data running effectively at 500 MHz (250 MHz DDR) - correct? That should all be doable, although 250 MHz DDR requires attention to board layout, clock delays, etc. Good luck, MarcArticle: 84867
In what way could I connect opb bram controller with a customized dual port ram? EDK does it automatically, but I'm not able to view or edit ram hdl file and I can't customize it with logic block for syncronization. Thanks MarcoArticle: 84868
Which C function should I use to perform read or write into block ram (connected to opb bus with opb bus controller)? Xio_in8 and Xio_out8 ? Thanks MarcoArticle: 84869
Hi,
Sorry I can't solve your problem regarding why the SDRAM is breaking -
but there is a little bug in the code - which may explain why the time
to failure is different for different time increment values:
the lines:
usleep(i);
i+=1; //INCREMENT x us
should be:
usleep(inc_val)
i+=inc_val;
as for an inc-val of 1 the first few loops this happens:
loop real_time value of i=usleep time
1 1 1
2 2 2
3 4 3
4 7 4
etc...
The real time is incorrect versus what i is saying it is. Maybe if you
change the code, you may see that the time to failure is the same for
different inc-values.
good luck!
Cheers,
John
Article: 84870BQ wrote: > I have a custom board with an altera EP1C12, a flash memory and a > MT48LC4M32B2 SDRAM memory. > Timings I set in SOPC builder are the default timings for this part. > > When I set the value 0x00000000 to a particular location (it doesn't > matter which location I choose), if I read back the same location after > 5 ms (milliseconds!) I find 0x00000000; after 10ms some of the bits go > to value 1; incrementally all the bits go to 1, and if I read it after > 15ms, I read 0xffffffff. > > > I tried increasing the refresh frequency (from 15.625us to 3us) with no > success. > At first glance it would look as if your refresh is not happening at all however... > > if instead I using a delay increment of 100us at a time (see line "i+=1; > //INCREMENT x us") , the problem appears later than when I use an > increment of 1us: > > This seems to point to data corruption happening as you read the memory. I would check that you're meeting the timing on CS, RAS, CAS and (especially) WE.Article: 84871
John McGrath wrote: > Hi, > Sorry I can't solve your problem regarding why the SDRAM is breaking - > but there is a little bug in the code - which may explain why the time > to failure is different for different time increment values: > the lines: > usleep(i); > i+=1; //INCREMENT x us > should be: > usleep(inc_val) > i+=inc_val; > > as for an inc-val of 1 the first few loops this happens: > > loop real_time value of i=usleep time > 1 1 1 > 2 2 2 > 3 4 3 > 4 7 4 > etc... > > The real time is incorrect versus what i is saying it is. Maybe if you > change the code, you may see that the time to failure is the same for > different inc-values. > > good luck! > Cheers, > John > Hello John, thank you for spending time for my problem :-) In fact, successive tests show that you are right, the time to failure is not dependent on the time between reads. Cheers MarcoArticle: 84872
Gabor wrote: > > At first glance it would look as if your refresh is not happening at > all however... > We checked with an oscilloscope and it appears the refresh signal is ok... > > > This seems to point to data corruption happening as you read the > memory. > I would check that you're meeting the timing on CS, RAS, CAS and > (especially) > WE. > I'm asking myself whether slowing down the SDRAM clock can be a solution... THhank you very much, BQArticle: 84873
Hi, I try to find some information about the internal structure of the configuration-frames for Xilinx Virtex-II (Pro) architecture. On Xilinx websites I just find informations about the configuration-memory-addressing for these architectures and some informations for the Virtex architecture, but i`m intressted in the meaning of the bits in the frames. Can anybody help me? At the moment I plan to use JBits and analyze the bitstream(s) afterwards, but this won`t be the best way. thx, SvenArticle: 84874
Hi all, I am looking at some FPGA related jobs and am finding that very few involve 100% FPGA design. Typically I am finding that current jobs will involve additional activities such as DSP processor programming as well. I was wondering if you guys would be able to comment on whether your jobs or jobs of people you know involve mostly (or 100%) FPGA design? Or are you required to do other stuff as well? Many thanks for your time, Dave
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