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Hi all, I'm happy to see Xilinx is releasing their WebPack for Linux, and with a couple of minor tweaks, it actually works on everyday versions of Linux like Debian. Problem is, its missing the simulation and verfication tools shipped with the Windows version. I'm namely thinking about ModelSim, and the version that is downloadable from the Xilinx WebPack homepage - what are people doing on Linux for (Free) simulation and verification? Cheers Tim -- "Linux... because rebooting is for adding new hardware!" http://home.swiftdsl.com.au/~tmccoy MSN: timsy_01@hotmail.com ICQ: 160341067Article: 85126
My unit went down and but the LCD & battery were working condition, so I opened them and hoping to use in my hobby projects. Anyone has the datasheet for this LCD? Thanks in advance.Article: 85127
Hi All, I used EDK7.1i to do some projects(Microblaze core), in the projects there are many floating point computing, so I want to use FPU in EDK7.1 to speed up. However, there are some mistakes of the results, so I would like to know (1)how to use the FPU step by step? (2)should I have to set some parameters in order to use FPU? (3)should I add #include "stdlib.h" #include "math.h" .... or other .h files in my programmes to do the floating point? Thank you! LinaArticle: 85128
thanks a lotArticle: 85129
SK wrote: > Praveen, > > It depends on what you want to do in case of multiple key press event. > In case of single bit key press, send some encoded information (max. 6 bits) > instead of transmitting all the 36 bits. The encoded bit transmission is > quite good if you don't want to take any action in case of multiple key > press event, or if you want to display some extended character in case of > multibit key press. I need to sense multiple key presses , how will you do this with a 6-bit word. > > hope that helps. > Sunil > > > <praveen.kantharajapura@gmail.com> wrote in message > news:1117770846.122441.301610@g47g2000cwa.googlegroups.com... > > Hi all, > > > > I am implementing a 6x6 matrix keypad scanner in CPLD. > > My requirment is i should detect multiple key presses also. > > What i am planning to do is , i will scan the rows (6 of them > > sequentially) , when all the 6 rows are scanned i will send the 36 bit > > output(each bit corresponds to each individual key .'0' indicates > > pressed)to the controller.The scan rate for each row is approximately > > 32 msec , so every 32x6=192 msec i will be sending the 36 bit code to > > controller(HCS12). > > > > I want your comments on this implementation in CPLD. > > > > Regards, > > Praveen > >Article: 85130
Peter Alfke wrote: > I do not know why you are so slow, you could easily be a thousand times > faster. I agree with you i can be still faster. > Since you can only detect a single closure, you could encode the scan > into a 6-bit word. > In my key board i have a "shift" key which works in conjuction with keys"1" , "2" and "3". for ex: when shift -> "1" is pressed do some operation, how will you detect this with a 6-bit approach, whereas this can be easily done in a 36-bit approach. waiting for u r reply > I am glad you realized that you cannot detect multiple simultaneous key > closures, without inserting iolation non-linearities (diodes) into the > array. > Peter AlfkeArticle: 85131
Falk Brunner wrote: > "Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag > news:1117771436.575914.41260@o13g2000cwo.googlegroups.com... > > > I do not know why you are so slow, you could easily be a thousand times > > faster. > > Why hurry withou a need? By scanning so low you > > a) consere power > b) do a debounce > > > Since you can only detect a single closure, you could encode the scan > > into a 6-bit word. > > > > I am glad you realized that you cannot detect multiple simultaneous key > > closures, without inserting iolation non-linearities (diodes) into the > > array. > > ??? Been there, done that? > > I worked on this topic not too long ago, you CAN easyly detect multiple > pressed keys withOUT having diodes in the matrix. > All you need is a "walking one" scan. falk, as you know i am implementing this in a CPLD. In my application i need multiple(two) key press detection. As many of them are opposing my 36-bit approach for detecting two keys pressed simultaneously, my question is how will u achieve multiple key detection with a 6-bit approach. > > Regards > FalkArticle: 85132
Hey,
I have USB1.1 hard IP and i want to interface this with ARM
processor using AMBA AHB Specification 2.0 for high speed operation.
The vendor of USB core is not supporting us becoz we have bought it
long back. We have only USB datasheet nothing else. Now you please tell
me is there any document to refer.
Rgds...
Joe
Article: 85133
Hey,
First start writing small designs and try to simulate and verify
them using some free simulations tools in the web. Xilin also offering
some evaluation versions of simulation tools. Then you should
synthesize your and design followed by place & route and Static timing
analsys (STA). Then you require hardware to actually verify your design
in FPGA. Until STA you can manage with free web tools but to test your
design in FPGA you need hardware and no company is provinding hardware
for free.
--Joe
Article: 85134If previousaly, you were using one BRAM to run both the FIR, then you have to use two different dual port BRAM for dynamic coefficients, one for each FIR filter engine. Use one port for writing co-efficents and the other port for reading. Configure your BRAM to 'read before write' to avoid reading new coefficients in case of address conflicts. Cheers, Sunil "bijoy" <pbijoy@rediffmail.com> wrote in message news:ee8eb30.-1@webx.sUN8CHnE... > Hi > > I have used Coregnerator FIR filter in my desing. Initially i have used > fixed coefficients, which is stored in BRAM area. and the design is > working fine > > Now i want to have the flexiility to change the filter coefficient in the > BRAM dynamically, but how do i write to that BRAM used by that particular > FIR filter ? > > (i have one more FIR running in parllalel with fixed coefficients loaded > to another BRAM area) > > Thanks > > bijoyArticle: 85135
As far as I know there are no plans to release a ModelSim XE starter for Linux. Most folks use command line simulators and GTKwave. Icarus Verilog is the most popular Verilog sim. http://www.icarus.com/eda/verilog/ GHDL is probably the most popular VHDL sim. http://ghdl.free.fr/ GPL-Cver is also good from what I hear (Verilog). http://www.pragmatic-c.com/gpl-cver/ Of course if you have money to burn, commercial sims will give you better performance and (arguably) a better UI than GTKwave, but I'm guessing you're not looking for commercial so the above should do the trick. Good luck, ArlenArticle: 85136
Piotr Wyderski wrote: > Big Boy wrote: > >> So, you can not supply Windows CE for a bare FPGA CPU core. At least, >> if you design a specific SoC, with CPU, Memory, IO, Display, ..., that >> Windows CE will have to be customized for that specific arrangment. >> This meen writing a lot of drivers. > > > That's obvious. > >> I don't say that it's not possible to do the thing, but I seriously >> doubth Altera would release such OS (bare) with their cores. > > > I think we should terminate this thread, because I didn't know > that NIOS2 is not free. I've seen (and downloaded) a free version > of the NIOS2 Evaluation Package, but it seems it is very limited. > And since $1000 is way too much for amateur purposes, I > have just forgotten about NIOS... > >> However, if you desire to have an OS > > > Currently I would like to have a free and efficient 32-bit CPU... ;-) > > Best regards > Piotr Wyderski > You want a "free and efficient" cpu, yet you want a Windows port for it?? If $1000 for a Nios2 development kit (includes all licenses and a powerful development board) is too much for you, then I'd recommend looking elsewhere for your OS. As you say, $1000 is a lot for amateur purposes, but so is WinCE - in real life, it is outside the range of most professional purposes. There are, as pointed out by another poster, a number of cpu cores on opencores, and some of these have supporting operating systems (typically linux or ucLinux).Article: 85137
"gallen" <arlencox@gmail.com> wrote in message news:1118040696.932870.241010@f14g2000cwb.googlegroups.com... > As far as I know there are no plans to release a ModelSim XE starter > for Linux. Most folks use command line simulators and GTKwave. > > Icarus Verilog is the most popular Verilog sim. > http://www.icarus.com/eda/verilog/ > > GHDL is probably the most popular VHDL sim. http://ghdl.free.fr/ > > GPL-Cver is also good from what I hear (Verilog). > http://www.pragmatic-c.com/gpl-cver/ > > Of course if you have money to burn, commercial sims will give you > better performance and (arguably) a better UI than GTKwave, but I'm > guessing you're not looking for commercial so the above should do the > trick. Symphony EDA is very good, and runs under Linux as well as Windows. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 85138
Hi all, I wanted to use a 32/16 divider circuit in one of my designs. I found Synopsys designware provides Pipelined dividers and decided to use it. I synthesised DW-divider and found a 3-stage pipeline required to meet my timing requirement of 20MHz(50ns) in TSMC .13u technology. Since I wanted to FPGA prototyping for my asic, I thought of using Core generator divider while synthesising for Xilnx FPGA.. Now the Interesting fact I found is, a 32/16 divider from Xlinx core genrator can be synthesised(using XST synthesis)to 150Mhz easily for a Virtex-2 (Xc2v2000)FPGA with just one stage pipeline.. At the same time DC-ultra 2004.06-1 is struggling with Designware foundation divider for meeting a timing of 20MHz with 3 stage pipeline.... I am confused.......... I always thought ASIC synthesis gives more frequency for an RTL code... What I can assume is SYNOPSYS Designware divider is a very bad implementation of divider... Any comments/Clues are welcome.. Thanks Deepu JohnArticle: 85139
Hi help - please could somebody confirm if the latest uclinux kernel would work with EDK 7.1 made system using MicroBlaze 4.0 ? I do have some problems, the 7.1 built hardware only works with ancient 2003 made image, with any newer images I get errors and there is never any bootmessage coming I was sure that 4.0 is OK as Gregs V4LX25 demo is made with EDK 7.1 but then I checked the .MHS and there was still microblaze 3.0 used so I am wonder why wasnt the MB upgraded to 4.0 ? thanks AnttiArticle: 85140
Forgot to mention that, I use Xlinix ISE version 7.1i for FPGA synthesis...Article: 85141
Hi I am a first time user of QuartusII + SOPC builder. After I create a design and map the different memories (external flash, external RAM and onchip ram) onto different address ranges, is there a way of automatically generating a linker script which I can use for linking my software? I am using Quartus II. For debugging I am using Accelerated Technologies' Codelab Debug for Nios II. I am using Codelab EDE as development environment instead of the Nios II IDE supplied by Altera. TIA SunnyArticle: 85142
> Now i want to have the flexiility to change the filter coefficient in the > BRAM dynamically, but how do i write to that BRAM used by that particular > FIR filter ? As far as I can see (and I may be wrong), you cannot easily do this since the core does not expose any control/update signals to halt the filtering operation and take new coefficients a la the distributed arithmetic core. It may be possible to disable the filter, and then update the coefficients in the pertinent BRAM, then reset the filter and ignore the transient output samples from the previous coefficient config but I have never done this? Anyone that has?Article: 85143
Sean Durkin <smd@despammed.com> writes: > Hi *, > > I keep coming across answer records and script files containing the > setting of undocumented environment variables, such as > XIL_ROUTE_ENABLE_DATA_CAPTURE, XIL_BITGEN_VIRTEX2ES, > XIL_XST_HIDEMESSAGES and so on. > > Is there a complete list of these hidden cheat codes? Any "official" > documentation at all? > > Whenever I'm stuck in a design, and find out that some magical > environment variable just fixes my problem, I wonder if maybe there is > something like the Holy Grail... something like the "Answer to Life, the > Universe and Everything", as in a "XIL_MAKE_EVERYTHING_WORK"- or > "XIL_42"-variable or something. Haven't found it but thought I could ask. > No help for you Sean, just a small rant: I've never understood this approach to things - it makes version control a bit of a nightmare! Surely there's a better way, even if it's a file called enable-budges.txt in the project directory! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 85144
...much appreciated! Cheers Tim -- "Linux... because rebooting is for adding new hardware!" http://home.swiftdsl.com.au/~tmccoy MSN: timsy_01@hotmail.com ICQ: 160341067Article: 85145
David Brown wrote:
> You want a "free and efficient" cpu, yet you want a Windows port for it??
Yes. :-) Thanks to MS Academic Alliance it is possible. Of course
the device will not be produced (i.e. there will exist a single specimen
of it, used by myself).
Best regards
Piotr Wyderski
Article: 85146The NIOS II IDE generates link scripts for you. Cheers, JonArticle: 85147
I would imagine that the Xilinx core takes multiple cycles to perform the divide (and thus is not pipelined), whereas with the Synopsys divider, you can probably start one divide per cycle, each having a latency of 3 cycles. Don't know though, never used them. Cheers, JonArticle: 85148
Uwe Bonnes wrote: > Sean Durkin <smd@despammed.com> wrote: > > Hi *, > > > I keep coming across answer records and script files containing the > > setting of undocumented environment variables, such as > > XIL_ROUTE_ENABLE_DATA_CAPTURE, XIL_BITGEN_VIRTEX2ES, > > XIL_XST_HIDEMESSAGES and so on. > > > Is there a complete list of these hidden cheat codes? Any "official" > > documentation at all? > > > Whenever I'm stuck in a design, and find out that some magical > > environment variable just fixes my problem, I wonder if maybe there is > > something like the Holy Grail... something like the "Answer to Life, the > > Universe and Everything", as in a "XIL_MAKE_EVERYTHING_WORK"- or > > "XIL_42"-variable or something. Haven't found it but thought I could ask. > > One first step to know about all variables: > > cd ise-7.1/bin/lin > > strings * | grep ^XIL_ > 607 hits! Also some are error messages... Don't forget the PAR_ and PL_ variables! I'm with Martin on this one... there is really no excuse for them using environment variables. In fact, I've complained about it, exactly for source control reasons. The two main responses I got: 1. Something along the lines of "variables are used on a temporary basis for ES parts, or for bugs that will be fixed in the next SW release" - which completely ignores the source control issue, and the fact that some of their customers may be stuck using or supporting ES parts forever, or unable to upgrade to the next SW release. 2. Something like that it was "difficult" to pass the variables read from a UCF file from one program to the next. I was flabbergasted by that response - there are so many different ways this could be done. Not only that, but Xilinx already does it with the CONFIG_STEPPING variable, that you can put in your UCF! This ranks right up there with the binary project file they've just introduced. MarcArticle: 85149
hello, When I tried to use Chipscope Pro Analyzer for programming the V2Pro fpga . I was able to succesfully connect the cables from PC to board. But when I tried to add a bit stream file created using jtag clk as start clk(and other settings that were given in the chipscope pro demo), I got the following error message. ERROR: Wrong configuration stream for device INFO: Found 0 Core Units in the JTAG device Chain. Please suggest me the solution for the above problem. Regards, Kishore
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