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I use ARM9
I had tried not stepping thru also.
What does coelessing mean ?
thanks
Article: 82426Thank you very much,I will learn to do it,and will do it better. > Antti Lukatswrote: "strayblue" <strayblue2003@yahoo.com-dot-cn.no-spam.invalid> schrieb im > Newsbeitrag news:iZmdnTJmKoW5n8ffRVn_vg@giganews.com... > I am new to the JTAG MASTER.Could you give me some example or > document? > > Dear Chinese Student, there are 3 kinds of people 1) those who go to school because "they teach in school" - those people learn nothing 2) those who go to school because they want to learn - whatever they learn is outdated info by the day they finish the school 3) those who learn that whatever there is to learn is up to them, those quit the school and start doing things and learn on the way of doing if you dont want to be in category [1] then start learning! JTAG master as standalone doesnt make much sense, if there is no application SW supporting it. implementing JTAG MASTER in SW by any small microcontroller is very simple, and there is NO special hardware needed, all you need is 4 general purpose I/O pins. As example in http://www.hydraxc.com there is a special JTAG controller implemented in small Microcontroller, by using regular MCU IO pins the this Processors achives JTAG data transfer rate up to 4Mbit per second, at 8MHz processor clock, and this without any special hardware. Any processor with higher clock rate can get even higher JTAG clock rates. If simple JTAG MASTER hardware speed up is required, then please take a look at http://gforge.openchip.org/projects/jisp/ there is verilog implementation of JISP byte code player, if Bytes are written to it, then it converts them to JTAG, well it requires a specially prepared (tokenized) bytestream. When using this JISP player connected to some CPU via small fifo then very high sustained JTAG TCK speeds can be achived http://www.mesanet.com/software/parallel/jtag.zip and there is JTAG is your JTAG TAP master in VHDL but my bet is that this info does not help you to pass your exam, you need to start LEARNING and most important DOING things yourself. Antti[/quote:10dea36cf8]Article: 82427
"strayblue" <strayblue2003@yahoo.com-dot-cn.no-spam.invalid> schrieb im Newsbeitrag news:lt6dnd2PNq8vYcbfRVn_vg@giganews.com... > Thank you very much,I will learn to do it,and will do it better. thats better attitude, I belive that if you do, you can do it. better. The links I provided do not give anything quite ready to use, just those starting points known to me. Hopefully there was some usefulness in it. And hope you didnt mind my writing style, I am very open, so I say what I think. So get a Smile and start doing. And try keep smiling :) Antti BTW I am at the moment quite engaged with JTAG from different aspects, both from master and slave side and also in supporting software, so if you make something better, please keep me posted, or better would be if there would be some result from your work that could be used by others. > > Antti Lukatswrote: > "strayblue" <strayblue2003@yahoo.com-dot-cn.no-spam.invalid> > schrieb im > > Newsbeitrag news:iZmdnTJmKoW5n8ffRVn_vg@giganews.com... > > I am new to the JTAG MASTER.Could you give me some example or > > document? > > > > > Dear Chinese Student, > > there are 3 kinds of people > > 1) those who go to school because "they teach in school" - those > people > learn nothing > 2) those who go to school because they want to learn - whatever they > learn > is outdated info by the day they finish the school > 3) those who learn that whatever there is to learn is up to them, > those quit > the school and start doing things and learn on the way of doing > > if you dont want to be in category [1] then start learning! > > JTAG master as standalone doesnt make much sense, if there is no > application > SW supporting it. > > implementing JTAG MASTER in SW by any small microcontroller is very > simple, > and there is NO special hardware needed, all you need is 4 general > purpose > I/O pins. As example in > > http://www.hydraxc.com > > there is a special JTAG controller implemented in small > Microcontroller, by > using regular MCU IO pins the this Processors achives JTAG data > transfer > rate up to 4Mbit per second, at 8MHz processor clock, and this without > any > special hardware. Any processor with higher clock rate can get even > higher > JTAG clock rates. > > If simple JTAG MASTER hardware speed up is required, then please take > a look > at > > http://gforge.openchip.org/projects/jisp/ > > there is verilog implementation of JISP byte code player, if Bytes > are > written to it, then it converts them to JTAG, well it requires a > specially > prepared (tokenized) bytestream. When using this JISP player connected > to > some CPU via small fifo then very high sustained JTAG TCK speeds can > be > achived > > http://www.mesanet.com/software/parallel/jtag.zip > > and there is JTAG is your JTAG TAP master in VHDL > > but my bet is that this info does not help you to pass your exam, you > need > to start LEARNING and most important DOING things yourself. > > Antti[/quote:10dea36cf8] >Article: 82428
Ben Twijnstra wrote: > Hi Andrew, > >>> Blank that sample and see what happens ;-) >> >> How do I do that? Is there an option in Quartus for this? I >> couldn't see anything .... > > Wups... I don't have an actual EPM7128S device lying around here, but > from the command line try "quartus_pgm --operation=R". If you need > more help, type "quartus_pgm --help=operation". This is what I'm getting: C:\>quartus_pgm -c "ByteBlasterMV [LPT1]" -m JTAG --operation=R Error: Programming option string R is illegal. Refer to --help for legal programming option formats. The help says: <options> must be one of the following combinations: P, V, B, S, E, L, PVBL, PBL, PVB, PVL, PL, VL where P = Program V = Verify B = Blank-check L = Lock/Security Bit S = Skip/Bypass* E = Examine* (* Cannot be used in combination with other options) There doesn't appear to be an R option. I'm using Quartus II Programmer Version 4.1 Build 181 06/29/2004 SJ Web Edition Does this version have an erase option?Article: 82429
I am looking for some information about how "real" this soft CPU technology is. I'm working with someone who has become enamored with the "soft CPU" concept from the FPGA vendors. I have a number of what seem to me to be "gotta know" questions about this technology, and I don't know how to get them answered. There are big picture questions like: - What are the compelling reasons to go this route? - If we take this path, can it be made to *really* work, i.e. never fail from one in a billion type errors? - How much longer will it take to do it this way compared to the "old" way of using a separate processor and FPGA? Then I have small picture questions like: - If you need to add peripherals (like UARTs, PWM contoller, etc., etc.) how well does this work? - Is the whole development environment reasonable? I looked around on the web, and there sure is a lot of marketing material, especially from Xilinx and Altera, but that's not what I'm looking for. Do you know anywhere I could get a description of how a real commercial project has gone for somebody, so that I can get some of my questions answered? Thanks! SteveArticle: 82430
Hi Steve,
The Nios Community Forum can provide you answers to your question
on the Nios II, Nios processors, their associated development
environment, tool chain support, RTOS's and peripherals from Altera
Corp. You can access it at www.niosforum.org.
Hope this helps.
Subroto Datta
Altera Corp.
Steve wrote:
> I am looking for some information about how "real" this soft CPU
> technology is. I'm working with someone who has become enamored with
> the "soft CPU" concept from the FPGA vendors. I have a number of
what
> seem to me to be "gotta know" questions about this technology, and I
> don't know how to get them answered. There are big picture questions
> like:
>
> - What are the compelling reasons to go this route?
> - If we take this path, can it be made to *really* work, i.e. never
> fail from one in a billion type errors?
> - How much longer will it take to do it this way compared to the
"old"
> way of using a separate processor and FPGA?
>
> Then I have small picture questions like:
>
> - If you need to add peripherals (like UARTs, PWM contoller,
> etc., etc.) how well does this work?
> - Is the whole development environment reasonable?
>
> I looked around on the web, and there sure is a lot of marketing
> material, especially from Xilinx and Altera, but that's not what I'm
> looking for. Do you know anywhere I could get a description of how a
> real commercial project has gone for somebody, so that I can get some
> of my questions answered?
>
> Thanks!
> Steve
Article: 82431Hey Antti, Thanks a ton, the paper was too helpful. This kind of a design will improve my system performance by alot. Thanks MORPHEUSArticle: 82432
"Steve" <smkraft@pacbell.net> schrieb im Newsbeitrag news:1113327700.042531.314340@l41g2000cwc.googlegroups.com... > I am looking for some information about how "real" this soft CPU > technology is. I'm working with someone who has become enamored with > the "soft CPU" concept from the FPGA vendors. I have a number of what > seem to me to be "gotta know" questions about this technology, and I > don't know how to get them answered. There are big picture questions > like: > > - What are the compelling reasons to go this route? 1) no obsolence 2) build your system with the peripherals and functions you need 3) design hardware after its has been manufactured to speed up time to market, the hardware is only bitstream and can be updated softly, also you can rework early design errors without the PCB changes 4) flexibility, design to be future safe, new hardware features can be added after product hardware is manufactured 5) etc.. > - If we take this path, can it be made to *really* work, i.e. never > fail from one in a billion type errors? almost nothing is failsafe, and extenal CPU and FPGA are possible evenso likely to fail > - How much longer will it take to do it this way compared to the "old" > way of using a separate processor and FPGA? not longer, but how much faster would be appropriate. get some Eval board for either NIOS-II or EDK, and you are writing normal C programs as soon as you the board and installed software > Then I have small picture questions like: > > - If you need to add peripherals (like UARTs, PWM contoller, > etc., etc.) how well does this work? a few mouse clicks. the environment builds the C include files and libraries for you > - Is the whole development environment reasonable? depends on your understanding of reasonable :) yes its ready and useable, but one could wish more.. > I looked around on the web, and there sure is a lot of marketing > material, especially from Xilinx and Altera, but that's not what I'm > looking for. Do you know anywhere I could get a description of how a > real commercial project has gone for somebody, so that I can get some > of my questions answered? > > Thanks! > Steve > there are quite a many commercial products aroung actually I think, but there is no list of them. I started with new job at www.eubus.net Jan 2005, and after that Microblaze has been used in two different redesigns (both defenetly commercial products), besides those http://www.hydraxc.com is full product line totally oriented to the use of SoftCore CPU's even though there are may be not so many references to the commercial use of soft to core CPUs yet I am very positive that they are used more widely as you may guess (from what is visible and public), I think the FPGA vendors actually have some feadback about how many FPGA designs use softcore CPUs, and this % is gorwing FAST, very FAST. AnttiArticle: 82433
Hey John, Thanks, the suggestions are quite helpful Thanks MORPHEUSArticle: 82434
"morpheus" <saurster@gmail.com> schrieb im Newsbeitrag news:1113328506.304806.220330@z14g2000cwz.googlegroups.com... > Hey Antti, > Thanks a ton, the paper was too helpful. This kind of a design will > improve my system performance by alot. > Thanks > MORPHEUS > :) thanks, I hoped it would be! It makes always sense to read very carfully all the stuff Ken Chapman writes! Tons of stuff to learn. I actually used that technique in 'digital carrier frequency amplifier' for SG bridge and LVDT sensors. It was using XC2S200E and microblaze and some digital path and simple filter etc.. AnttiArticle: 82435
Steve wrote: > I am looking for some information about how "real" this soft CPU > technology is. I'm working with someone who has become enamored with > the "soft CPU" concept from the FPGA vendors. I have a number of what > seem to me to be "gotta know" questions about this technology, and I > don't know how to get them answered. There are big picture questions > like: > As real as anything else one might want to put into an FPGA. > - What are the compelling reasons to go this route? There are some reasons that drive this, depending on developer though Control, previuosly I used ARM7TDMI external, as the FPGA got more capability & did more work, the system was stuck with same external cpu that was starting to become a bottleneck. Soft core cpus allow for the EE to get control of the system and insert cpu power where it's needed rather than depending on the ASIC supplier to help out. The worlds greatest cpu isn't much use on the ouitside if you want it inside for fine grain control. Some cpus are so tiny (PicoBlaze) they are hardly recognizeable to a manager, but they may be perfectly fine for doing some odd job FSMs. More interesting soft cpus may be just as capable as many external cpus (<< 200MHz that is), but you get some options that aren't possible on the outside. You could hide the soft cpu deeply, not mention it it to marketing or the competition, and the binary that runs on it can be merged into the FPGA bitfile, both the design, the start up code and initial data. Downsides include less well developed tools but thats improving with the gcc kit being everywhere, less big companies to hold hands, less training etc. Also the game has really just started, as FPGAs replace ASICs, I think we will see less opportunites for MIPs/ARM the traditional embedded suppliers. PPC though gets it both ways since it can be an external part or available as internal hard core for Xilinx (and to a lesser extent ARM with Altera). Upside usually no serious licence fee, you may even get permission to ASIC if you want for a smidgeon compared to dealing with ARM. Some other possibilities also include customizing the instruction set with new opcodes that might have a huge performance boost over doing it purely in SW even in an external much faster cpu. Or do same with a bit more distance hook up your engines to cpu ports or links or busses. There will come a time when people will think nothing of it and why should the cpu be on the outside with so little access to the internals. But there may still be use for an external cpu to hook up with other system components. > - If we take this path, can it be made to *really* work, i.e. never > fail from one in a billion type errors? > - How much longer will it take to do it this way compared to the "old" > way of using a separate processor and FPGA? > If you forbid the use of soft core cpus, some projects may well take longer if thats what they need. > Then I have small picture questions like: > > - If you need to add peripherals (like UARTs, PWM contoller, > etc., etc.) how well does this work? > - Is the whole development environment reasonable? > > I looked around on the web, and there sure is a lot of marketing > material, especially from Xilinx and Altera, but that's not what I'm > looking for. Do you know anywhere I could get a description of how a > real commercial project has gone for somebody, so that I can get some > of my questions answered? > > Thanks! > Steve just my opinions regards johnjakson at usa dot com transputer2 at yahoo dot comArticle: 82436
Steve wrote: > I am looking for some information about how "real" this soft CPU > technology is. I'm working with someone who has become enamored with > the "soft CPU" concept from the FPGA vendors. I have a number of what > seem to me to be "gotta know" questions about this technology, and I > don't know how to get them answered. There are big picture questions > like: > > - What are the compelling reasons to go this route? That depends very much on your product, market, and definition process. There are both advantages and disadvantages in SoftCPU. +You can roll almost anything that marketing dreams up [if you can keep up with their changes :) ] +Systems that need high bandwidth, sepecialised peripheral coupling can work very well in soft-cpu +SoftCPUs cover a very wide range: Some of the tiny ones, can run from block ram, and can be very good INIT and handshake problem solvers. -You will quite often need "next size" FPGA to include the CPU. [The FPGA vendors love this feature.. ] -It is not actually a single chip solution : You need the loader PROM, and some form of code execution memory. That can mean wide.high speed data busses, and many EMC issues. It is also not trivial to select and source that execution memory. Again, you can "next size" the FPGA, to get enough Block Ram to run all code on chip. -Power consumption can take quite a hit. Static Icc on newest FPGAs is terrible, when compared with Std Microcontrollers. You can, of course, have more than one controller in a design. You might use a small uC for WDOG, Init, ADC, BrownOut, and power save tasks, and a larger SoftCPU, or choose one of the new larger FLASH uC, and load the (now smaller) FPGA from that. For uC <-> FPGA interface you can choose parallel, or the newer faster serial interfaces. > - If we take this path, can it be made to *really* work, i.e. never > fail from one in a billion type errors? This is what I'd call mature technology. Field reliability is another area in itself... > - How much longer will it take to do it this way compared to the "old" > way of using a separate processor and FPGA? > > Then I have small picture questions like: > > - If you need to add peripherals (like UARTs, PWM contoller, > etc., etc.) how well does this work? Very well, if the peripheral mix is outside the typical uC. If you want 64 PWM channels, or special serials etc. Just don't try and add ADCs as peripherals, or 32KHz clock oscillators, or Brownout detectors..... :) -jgArticle: 82437
Hi Andrew Holme, > Ben Twijnstra wrote: >> Hi Andrew, >> >>>> Blank that sample and see what happens ;-) >>> >>> How do I do that? Is there an option in Quartus for this? I >>> couldn't see anything .... >> >> Wups... I don't have an actual EPM7128S device lying around here, but >> from the command line try "quartus_pgm --operation=R". If you need >> more help, type "quartus_pgm --help=operation". > > This is what I'm getting: > > C:\>quartus_pgm -c "ByteBlasterMV [LPT1]" -m JTAG --operation=R > Error: Programming option string R is illegal. Refer to --help for legal > programming option formats. > > The help says: > > <options> must be one of the following combinations: > P, V, B, S, E, L, PVBL, PBL, PVB, PVL, PL, VL > where > P = Program V = Verify > B = Blank-check L = Lock/Security Bit > S = Skip/Bypass* E = Examine* > (* Cannot be used in combination with other options) > > There doesn't appear to be an R option. > > I'm using Quartus II Programmer Version 4.1 Build 181 06/29/2004 SJ Web > Edition > > Does this version have an erase option? Hmmm... I'm using a beta of version 5.0 (only available under NDA), which does have the option available. Will try 4.2 tomorrow - that's the oldest workable version I have laying around (I also have a copy of 3.0 and the initial 1996 release, but I don't count those as current). Best regards, BenArticle: 82438
I want a FF in my EPM7128S project to be '0' at power-up; be later set by an external input; and never subsequently reset. I placed an SRFF with S to the external input; clock to the clock; and R to ground. I assumed it would power-up at '0' but I got analysis and synthesis errors: "Info: Power-up level of register inst is not specified -- using unspecified power-up level" and "output pins are stuck at VCC or GND" - so I created an assignment: set_instance_assignment -name POWER_UP_LEVEL LOW -to inst I was surprised it needed this, but it seems to work. That sorted, I placed an inverter between the Q output of the SRFF and an external output pin - I want the FF to drive an external active-low signal. This doesn't work in the simulator or the real silicon: the output is permanently asserted. But, if I connect another output directly to q - so I have both q and /q output pins - then it works! I'm guessing that Quartus can't invert the signal between the macrocell FF and output pin, so it needs to use another macrocell just for the inverter, but something goes wrong with the optimisation. Am I warm? Is this a known bug? Is there some option I need to set, or must I dedicate an output pin for the unwanted true q - just to make the /q output work?? I'm using Quartus II 4.1 Web Edition. You can download a Quartus archive of this from http://www.holmea.demon.co.uk/Misc/Test.qar Try it first as-is, then delete the true output and re-run the simulation. TIAArticle: 82439
Hi all,
I'm trying to implement a filter switch. I have two different filters
(filter30 and filter5, realized with the MacFir Xilinx Core), I have to
use only one of them at time, so I'm trying to use a multiplexer
(filter_mux) to multiplex the outputs of the filters.
I'm experimenting a strange problem, the filters are not working
correctly they always produce the same outputs, but they shouldn't, It
seems to be related to wich filter I generate first, if I launch
"regenerate core" on the filter in the order filter30,filter5, then the
outputs of the two filters will be equal to the output of filter5, if I
invert the "regenerate core" order, then I get the output of filter30 on
both filters.
That's driving me crazy, I can't use the "Multiple coefficients sets" of
MacFir ver5.0 because I'm using ISE6.1 and the core version is 3.0.
When I "Synthesize" the design (implemented as a toplevel schematic) I
get this warnings:
WARNING:Xst:766 - C:/Xilinx/progetti/ddc/filter.vhf line 66: Generating a
Black Box for component <filter30>.
WARNING:Xst:766 - C:/Xilinx/progetti/ddc/filter.vhf line 71: Generating
a Black Box for component <filter5>.
And a lot of this:
WARNING:Xst:382 - Register BU2000 is equivalent to BU1318
WARNING:Xst:382 - Register BU2689 is equivalent to BU1318
WARNING:Xst:382 - Register BU3631 is equivalent to BU1318
And I don't know what this means.
Here is a little piece of filter.vhf
-----------------------------filter.vhf---------------------------------
66 XLXI_1 : filter30
67 port map (CLK=>CLK, DIN(13 downto 0)=>DIN(13 downto 0), ND=>ND,
68 RESET=>RESET, DOUT(33 downto 0)=>XLXN_9(33 downto 0), RDY=>XLXN_10,
69 RFD=>XLXN_11);
70
71 XLXI_2 : filter5
72 port map (CLK=>CLK, DIN(13 downto 0)=>DIN(13 downto 0), ND=>ND,
73 RESET=>RESET, DOUT(33 downto 0)=>XLXN_12(33 downto 0),
74 RDY=>XLXN_13, RFD=>XLXN_14);
75
76 XLXI_3 : filter_mux
77 port map (CLK=>CLK_DIV, DOUT_IN_A(33 downto 0)=>XLXN_9(33 downto 0),
78 DOUT_IN_B(33 downto 0)=>XLXN_12(33 downto 0), RDY_A=>XLXN_10,
79 RDY_B=>XLXN_13, RFD_A=>XLXN_11, RFD_B=>XLXN_14, SEL=>SEL_OUT,
80 DOUT(23 downto 0)=>DOUT(23 downto 0), RDY=>RDY, RFD=>RFD);
-----------------------------filter.vhf---------------------------------
Reading filter.vhf (created automatically) seems that everything is ok,
but when I launch "View RTL Schematic" I see that the inputs and outputs
ports of the filters seems disconnected.
--
If I feel like exercise, I lie down until it passes.
|\ | |HomePage : http://nem01.altervista.org
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Article: 82440In message <ACF6e.561771$w62.481540@bgtnsc05-news.ops.worldnet.att.net>, Delbert Cecchi <dcecchi_nospam@worldnet.att.net> writes >Doing what the chinese >probably did to that crypto equipment on something modern is way beyond >my scope. Any references to the story? > >del > > -- Clint SharpArticle: 82441
From www.fpgaarcade.com / pacman. 2 bit x 2 bit mul element.
4 inputs fit into one LUT, so you can use a case statement to make it easier
to read without a performance hit. This should take 4 luts total. There are
much better ways to do bigger multipliers, search this group as it has been
discussed many times.
Cheers,
Mike.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PACMAN_MUL_PARTIAL is
port (
A : in std_logic_vector(1 downto 0);
B : in std_logic_vector(1 downto 0);
R : out std_logic_vector(3 downto 0)
);
end;
architecture RTL of PACMAN_MUL_PARTIAL is
begin
p_lut_comb : process(A,B)
variable ip : std_logic_vector(3 downto 0);
begin
ip := A & B;
case ip is
when "0000" => r <= x"0";
when "0001" => r <= x"0";
when "0010" => r <= x"0";
when "0011" => r <= x"0";
when "0100" => r <= x"0";
when "0101" => r <= x"1";
when "0110" => r <= x"2";
when "0111" => r <= x"3";
when "1000" => r <= x"0";
when "1001" => r <= x"2";
when "1010" => r <= x"4";
when "1011" => r <= x"6";
when "1100" => r <= x"0";
when "1101" => r <= x"3";
when "1110" => r <= x"6";
when "1111" => r <= x"9";
when others => null;
end case;
end process;
end architecture RTL;
<xiibweb@hotmail.com> wrote in message
news:1113308406.925190.136610@l41g2000cwc.googlegroups.com...
> thnx a lot... problem is solved
>
Article: 82442Austin, Maybe you can give me more insight to a problem I have with xapp646. The note states that "Since the device is a set of series-connected NMOS transistors, any voltage larger than a few hundred millivolts below the VCC pin voltage will be cut off." From reading the IDT appnotes and what I'm seeing on a circuit board, the output will always be limited to less than VCC-1. With VCC at 3.3v as shown in xapp646, under light loading, the output voltage is about 2.3v, and with a 10k load, it's closer to 2v which means essentially no noise margin for TTL. Look at figure 4 of http://www1.idt.com/pcms/tempDocs/AN_11.pdf or figure 5 of http://www1.idt.com/pcms/tempDocs/quickswitch_basics.pdf Do you think that I should be seeing around 2 to 2.3v output with the ckt shown in xapp646? Dr, take a look at TI's sn74cb3t3384 or sn74cbtd3384c as well as some appnotes on their site. gja "Austin Lesea" <austin@xilinx.com> wrote in message news:d3gogs$lr91@cliff.xsj.xilinx.com... > Dr, > > Spartan 2 will be around a long time. That we have demoted it from the > limelight is a marketing issue (just so much shelf space for the new > products to showcase). > > As you may be aware, we still provide the 3100A series of FPGAs, which are > still supporting designs done 15 years ago! > > We discontinue devices once they are not able to be manufactured and sold > economically. This means that there is little business, and the process > used to make the chips has become obsolete at the fabrication facilities. > We also may discontinue a particular part/package combination when that > package is running at extremely low volumes or becomes difficult to > procure. > > Since we are still making almost all of our FPGA products, I don't think > you have anything to worry about with Spartan II. > > The original Virtex, and Spartan II are a lot like classic Coca-Cola -- > they may never go away. > > However, the cost/function of newer devices is so much better than the > older devices, that you may want to consider designing with the latest > devices (at some point). > > The app notes we have published for 5V PCI details all of the tricks to > make the latest 90nm devices work on the 5V PCI bus. (Xapp 646, 311) > > I hope this helps, > > AustinArticle: 82443
Would he be able to apply some timing constraints to the flops in block C and maybe the clock to block C to guarantee that the clock skew is acceptable. gja "Marc Randolph" <mrand@my-deja.com> wrote in message news:1113311589.903268.83150@z14g2000cwz.googlegroups.com... > > g. giachella wrote: >> In my design (in a Virtex II) there are 2 clocks, each of them on >> global buffer and feeding 2 sets of distinct registers (block A and >> block B). The clocks then feed a clock switching circuit (not a >> BUFGMUX) and the resulting clock feeds another part of the design >> (block C). > [...] >> I suppose this message warns about a potentially unacceptable skew >> between blocks A/B and block C , but the skew inside block A or block >> B is still guaranteed to be low. >> >> Am I right ? > > Howdy, > > Depending on how you are getting signals between blocks A/B and C, > there is the potential for trouble - but the MUCH bigger problem is > that you will have unacceptable skew *within* block C. Unless you > floorplan the flops within block C (and do so VERY intelligently), > you're asking for trouble. Even if you do the muxing with LUTs, send > the output of the LUT to a global clock. > > And yes, the skew within blocks A and B should be fine. > > Marc >Article: 82444
Hey Antti, I was wondering if this circuit works well with 2's complement data also 'coz I implemented it and it doesnt seem to work. For 2's complement data, the subtractor at the begining of the ckt needs to be an adder...right? Thanks MORPHEUSArticle: 82445
"gja" <geeja@hotmail.com> wrote in message news:luY6e.1145$FQ.507@fe10.lga... [snip] > Dr, take a look at TI's sn74cb3t3384 or sn74cbtd3384c as well as some > appnotes on their site. Will do. Thanks for the tip! DJ --Article: 82446
Hi Clemens, To use a package in multiple projects, the user must explicitly include the file containing the package in each project separately. (Quartus II does not auto-discover package files, only entity files.) The package file must be listed prior to its first use because Quartus II links VHDL design units during parsing. In Quartus II 5.1, we'll remove the requirement that VHDL source files be listed in the correct order. That way, users can simply add all their VHDL source files in any order, and we'll still process the design correctly. Now, as for VHDL libraries: Prior to Quartus II 4.2, all user VHDL source files were compiled into the WORK library. In 4.2, we still compile VHDL source files into WORK by default, but we also added several mechanisms that allow the user to specify a different destination library. These mechanisms are described in the Quartus II Handbook, Chapter 6: http://www.altera.com/literature/hb/qts/qts_qii51008.pdf Hope this helps, Subroto Datta Altera Corp. Clemens Hermann wrote: > Hi, > > with the latest quartus II software I created two VHDL packages. After > testing the packages I wanted to combine them in a custom VHDL library > with no success. My goal is to have a directory that contains the > library (preferrably precompiled) so that I can pass it around and it > could be used by others as simple as the standard VHDL libraries (e.g. > ieee) like > > LIBRARY my_lib; > USE my_lib.package1.all; > USE my_lib.package2.all; > > without adding each single VHDL file the packages are based on. > > Any pointer to information or hints how I could get things up and > running would be a great help. > > thanks in advance, > > /chArticle: 82447
"Clint Sharp" <clint@clintsmc.demon.co.uk> wrote in message news:kUhgPzAOwDXCFw+A@clintsmc.demon.co.uk... > In message <ACF6e.561771$w62.481540@bgtnsc05-news.ops.worldnet.att.net>, > Delbert Cecchi <dcecchi_nospam@worldnet.att.net> writes > >Doing what the chinese > >probably did to that crypto equipment on something modern is way beyond > >my scope. > Any references to the story? > > > >del > > > > > > -- > Clint Sharp I was referring to the US Electronic Intelligence or something plane that got kidnapped out of international airspace near china and forced to land. Got the crew back in a while. As I recall we got the airframe back in boxes. It was rumored the crew didn't have enough time to destroy all. Probably within last 10 or so years. Google should turn it up. EC137 may have been the aircraft type. I don't know what happened to the electronics but I can guess. del cecchiArticle: 82448
Thank you guys for the answers. I took Gary's approach to emphasize on PCB layout first and still all the timing were met. vax, 9000Article: 82449
Antti Lukats wrote: > "Steve" <smkraft@pacbell.net> schrieb im Newsbeitrag > news:1113327700.042531.314340@l41g2000cwc.googlegroups.com... > >>I am looking for some information about how "real" this soft CPU >>technology is. I'm working with someone who has become enamored with >>the "soft CPU" concept from the FPGA vendors. I have a number of what >>seem to me to be "gotta know" questions about this technology, and I >>don't know how to get them answered. There are big picture questions >>like: >> >>- What are the compelling reasons to go this route? > > > 1) no obsolence > 2) build your system with the peripherals and functions you need > 3) design hardware after its has been manufactured to speed up time to > market, the hardware is only bitstream and can be updated softly, also you > can rework early design errors without the PCB changes > 4) flexibility, design to be future safe, new hardware features can be added > after product hardware is manufactured > 5) etc.. As a practical matter, don't all of these points also apply to an external uC with an FPGA as a peripheral? Also, I'm a little perplexed by point 1 - no obsolescence - don't FPGAs families become obsolete just like anything else? Or do you mean something else? -Jeff
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