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> > fpgavhdl@gmail.com wrote: > > > Can an FPGA have two JTAG ports for programming an FPGA chip? > > > > > > One is conected thro XCf02s to the FPGA and the other is directly > > > connected to the FPGA (XC3S400). > > > > > > What is the significance of having two ports? > > > > > > What files are used for programming this FPGA thro each of those > ports? > > > > similar case is used in Altium livedesing, there a special 2 port Xilinx compatible cable is used the xilinx JTAG pins go the FPGA normal JTAG pins the secondary JTAG goes to 4 general purpose pins on the FPGA, those 4 pins are connected to JTAG TAP controller ip core inside the FPGA (made from logic resources), this secondary 'soft TAP' is used to control the on chip logic analyzer and that kind of stuff not sure if that was the answer you wanted anttiArticle: 82076
Hello all, I am doing a literature survey on SEFIs in Xilinx FPGAs. Unfortunately, there are not many papers on this. It might either be because this is not a major issue or because there is not really much work done. Did you encouter SEFIs in your design? If yes, what mitigation methods did you use? I would appreciate any of your feedback. Thank you.Article: 82077
Go to the TechXcusives paper at http://support.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=al_soft_vs_hard Peter Alfke, Xilinx ApplicationsArticle: 82078
In article <1112717515.013523.275140@o13g2000cwo.googlegroups.com>, Karl <karlIGNORETHISPART@chello.nl> wrote: >Here is a solution for your noise, > >http://www.zalman.co.kr/eng/product/view.asp?idx=151&code=020 > >The cost could not be the issue if you start using Altera devices :-) This is probably both troll-bait and an FAQ, but what's the Altera equivalent of something like the Xess $199 XC3S1000 or $349 Avnet XC4VLX25? (that is, a cheap board with a chip on it as large as the free tools support, and some quick-win peripherals) Counting LUTs, multipliers, memories and general performance claims, the LX25 board is a remarkable capability for the price of three weeks' rent. Chip/Board cost/# LUTs/# flipflops/# multipliers | # 512bit/# 4kbit/# 16kbit/# 512kbit XC4VLX25 $349 21504 21504 48 | 0 0 72 0 XC3S1000 $199 15360 15360 24 | 0 0 24 0 EP1C12 $295 12060 12060 0 | 0 52 0 0 EP2S15 12480 12480 48 | 104 78 0 0 EP1S10 $395 10570 10570 24 | 94 60 0 1 Parallax do a $395 bare-bones board with an EP1S10, and there's the Nios II Eval Board for $295 with Ethernet. I suppose the Stratix 2 series is new enough that it's unfair to expect cheap hobbyist boards already, but Google isn't giving me any useful hit on +EP2S15 +board. TomArticle: 82079
In article <d5200104.0504060757.5cff81fb@posting.google.com>, Keith_eng_fyp <keith.lumsden@gmail.com> wrote: >Hi All, >I was wondering is there any way to synthesis a design of mine on an >FPGA using the ISE tool so that I can get results for area speed, >xpower and such. It is a partial prooduct summation tree that adds 13 >12-bit numbers in a weighted manner. The tool tries to assign its >input and output ports to pins and i get a worning to say that more >than 100% of the device is used up even though it only uses 8% of the >gates. I was wondering is there a way to unbond the ports from the >pins. Build a little (13*12)-step shift register taking input from one of the pins, and with its stages connected to the inputs of your summation tree; I imagine that'll be small enough not to make a nonsense of the area/speed/power results. You probably do want to take all the outputs to pins, otherwise the optimiser will be clever. TomArticle: 82080
Hi, thank you for your message. > 1 the M0,M1,M2 no need to connect at all, the JTAG is enabled anyway Ok, I've also read this in the datasheet. > 2 PROG_B doesnt matter as long as you try to identify the chain, however > configuration over JTAG may fail if there is no pullup on PROG_B > 3 INIT_B pullup I have a pullup on PROG_B and another on INIT_B, but have seen that if I connect PROG_B to GND I can read 0x803 as device ID on iMPACT. Instead, if I connect the pullup on PROG_B, the device ID readed was all zeros. > everything else doesnt matter > if you have xilinx cable III or IV then you can use > http://gforge.openchip.org/projects/fpgafreqmeter/ > > to see if that application can detect the jtag correctly > > and there is JTAG chain debugger in the impact I've downloaded your program, it see the Xilinx Cable III and a device "1:FC000803" (is this the device ID readed ?). Any idea?!? Thank you again for the response. EnzoArticle: 82081
"Enzo B." <enzo_br@virgilio.it> schrieb im Newsbeitrag news:oJV4e.1185199$35.43703526@news4.tin.it... > Hi, thank you for your message. > > > 1 the M0,M1,M2 no need to connect at all, the JTAG is enabled anyway > > Ok, I've also read this in the datasheet. > > > 2 PROG_B doesnt matter as long as you try to identify the chain, however > > configuration over JTAG may fail if there is no pullup on PROG_B > > 3 INIT_B pullup > > I have a pullup on PROG_B and another on INIT_B, but have seen that if I > connect PROG_B to GND I can read 0x803 as device ID on iMPACT. Instead, if I > connect the pullup on PROG_B, the device ID readed was all zeros. the value of PROG_B should not matter for the JTAG to be operational, something is really funky if it has any influence on the ID readback > > everything else doesnt matter > > if you have xilinx cable III or IV then you can use > > http://gforge.openchip.org/projects/fpgafreqmeter/ > > > > to see if that application can detect the jtag correctly > > > > and there is JTAG chain debugger in the impact > > I've downloaded your program, it see the Xilinx Cable III and a device > "1:FC000803" (is this the device ID readed ?). > > Any idea?!? > > Thank you again for the response. > > Enzo yes that is the 32 bit IDCODE as read back from the device, before the IDCODE my program validates the number of devices in the chain what is sensed correctly to the chain isnt completly broken hm have you powered VCCAUX with 2.5 and do have VCCIO on the banks that contain the JTAG pins ? when I did a wire wrap proto with Virtex-2000 in BGA then my mistake was that I did not power the VCCIO in the JTAG banks, and second was the missing pullup on PROG_B anttiArticle: 82082
Hi Antti, The secondary port which is coonected to the FPGA general purpose pins as u suggested, does it require some programming file? Or its just control to and from the FPGA. Thanks a lot, - Shailesh Antti Lukats wrote: > > > fpgavhdl@gmail.com wrote: > > > > Can an FPGA have two JTAG ports for programming an FPGA chip? > > > > > > > > One is conected thro XCf02s to the FPGA and the other is directly > > > > connected to the FPGA (XC3S400). > > > > > > > > What is the significance of having two ports? > > > > > > > > What files are used for programming this FPGA thro each of those > > ports? > > > > > > > > similar case is used in Altium livedesing, there a special 2 port Xilinx > compatible cable is used > the xilinx JTAG pins go the FPGA normal JTAG pins the secondary JTAG goes to > 4 > general purpose pins on the FPGA, those 4 pins are connected to JTAG TAP > controller > ip core inside the FPGA (made from logic resources), this secondary 'soft > TAP' is used > to control the on chip logic analyzer and that kind of stuff > > not sure if that was the answer you wanted > > anttiArticle: 82083
<fpgavhdl@gmail.com> schrieb im Newsbeitrag news:1112812058.768782.307150@z14g2000cwz.googlegroups.com... > Hi Antti, > > The secondary port which is coonected to the FPGA general purpose pins > as u suggested, does it require some programming file? > > Or its just control to and from the FPGA. > > Thanks a lot, > - Shailesh no, well it doesnt require any configuration file at least. its just an additional user access port into the FPGA and its up to the application how it is used. it could be connected to some onchip or offchip memories and your application could use it to download some data to memory, etc.. however the same functionality can be achived over the main jtag port as well, by using the BSCAN primitive what is availabe in most modern FPGA's. I think that Altium uses the second soft TAP just to make their life easier, the soft TAP can be implemented to be compatible on any FPGA being it from xilinx altera or actel, while the use of main JTAG over BSCAN is vendor dependant always. http://gforge.openchip.org/projects/fpgafreqmeter/ uses the main JTAG and BSCAN to control the on-FPGA counters, it uses JTAG HUB http://gforge.openchip.org/projects/jtaghub/ and works equally well on xilinx and altera chips (actel and lattice support is not added yet) antti > Antti Lukats wrote: > > > > fpgavhdl@gmail.com wrote: > > > > > Can an FPGA have two JTAG ports for programming an FPGA chip? > > > > > > > > > > One is conected thro XCf02s to the FPGA and the other is > directly > > > > > connected to the FPGA (XC3S400). > > > > > > > > > > What is the significance of having two ports? > > > > > > > > > > What files are used for programming this FPGA thro each of > those > > > ports? > > > > > > > > > > > > similar case is used in Altium livedesing, there a special 2 port > Xilinx > > compatible cable is used > > the xilinx JTAG pins go the FPGA normal JTAG pins the secondary JTAG > goes to > > 4 > > general purpose pins on the FPGA, those 4 pins are connected to JTAG > TAP > > controller > > ip core inside the FPGA (made from logic resources), this secondary > 'soft > > TAP' is used > > to control the on chip logic analyzer and that kind of stuff > > > > not sure if that was the answer you wanted > > > > antti >Article: 82084
On Mon, 04 Apr 2005 19:48:58 +0100, Thomas Womack wrote: > Is there any way of using the Xilinx toolchain on a Mac? > > I have become spoiled by my Mac Mini, and unpacking my loud PC > just to run place-and-route seems inelegant. > > Tom Take your PC, put Linux on it, install the Linux Xilinx tools, put it in another room and then rlogin or ssh into it. The Mac will make a fine X server. You can do all of your work from the Mac while the PC is safely out of earshot.Article: 82085
"JJ" <johnjakson@yahoo.com> writes: > If some processor that is not any way MIPs like can otherwise perform a > register ld/st for a word on any byte boundary is that a problem, or > only if the rest of it is MIPs like too. It's not the unaligned load/store per se that is patented; many processors have done that. What MIPS invented and patented was the idea that instead of having the hardware deal with unaligned bus accesses, they require software to issue *two* instructions to do an unaligned access. One does the "left part" and one does the "right part" of the word. The normal MIPS load and store instructions require alignment just as on most other RISC processors.Article: 82086
Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes: > Of course. But the one that tied it all together in a single, > coherent bundle was Patterson and Ditzel. Are you asserting that the IBM 801 papers didn't tie it all together in a single coherent bundle?Article: 82087
mojaveg@mojaveg.iwvisp.com (Everett M. Greene) writes: > It always puzzled me as to how Intel could get a copyright > on instruction mnemonics. This struck me as being akin to > someone copyrighting the Latin alphabet. An AND, is an > AND, is an AND,... AFAIK the validity of the copyright on the mnemonics was never tested in court. It seems unlikely that it would be upheld.Article: 82088
Praveen, To what are you referring? A single event error in the logic fabric (CLB SEE)? A single event transient in the fabric (CLB SET)? A single event upset of a memory cell (SEU config)? A single event upset of a BRAM memory cell (SEU BRAM)? A single event transient or single event error which affects the entire device (as in fooling the chip into thinking PROG was pulled low)? We usually refer the the last event (loss of configuration, global reset, global tristate) as a SEFI (single event functional interrupt). Not everyone uses this terminology, but we use it because it is descriptive of what happens (on very very very rare occasions!). Our mil/aero/automotive customers also think this way, and we have statistics for the probabilty of any of the above happening, all the way from 1 million years for a SEE, or SET in the fabric for the largest device, to the article that Peter pointed you to for config upsets (more than a 1000 years). By the way, Virtex 4 has now improved upon the upsets rates due to our design techniques and has shown a reduction to 60% (over Virtex II) of the previous FIT rates for the configuration memory. This winds the clock back to the days when people didn't even think about SEUs. Watch for the tech Xclusive on this subject (appearing soon). If you want all the details, contact our mil/aero/automotive group FAEs who are trained in this, and have all the field tests, studies, etc. at their fingertips. For us, there is no unknowns in this regard. After all, we are used in airplanes, spacecraft (and automobiles) so these folks want to know exactly what the probabilities of failures are, and how to mitigate them (deal with them when they occur, or mask them so you never see a failure in the system). AustinArticle: 82089
I just realized, So as not to confuse anyone, if VII is 1000 years MTBE (mean time between config upsets -- which is actually better than that based on more recent data, but we will just go with it for now), V4 is better, so it is ~ 1,667 years for the same number of config bits. (60% of 1667 years is 1000 years). If you do nothing about upsets, 90nm is worse than 130nm, is worse than 180nm, etc. So, you have to do something to make it better. We did. (You're welcome,) AustinArticle: 82090
Mentre io pensavo ad una intro simpatica "Eric DELAGE" scriveva: > Are you using WinXP Pro? Are the WinXP permissions correctly set > (installation directory, user directory where ModelSim will create a > default modelsim.ini)? I'm using WinXP Pro, I have "full control" on the ModelSim directory. Probably it is trying to write into another directory where it can't. I really don't know. -- Donne al volante pericolo costante |\ | |HomePage : http://nem01.altervista.org | \|emesis |XPN (my nr): http://xpn.altervista.orgArticle: 82091
I think I really don't understand the original question. Are you asking
"if" you could instantiate 2 TAPs on a single FPGA? Or are you asking
"why" would you instantiate 2 TAPs on a single FPGA.
If the question is "if" then the answer is, as Antti L. suggested, you
could use the single dedicated FPGA TAP and then create a separate TAP
and TAP controller out the FPGA fabric and general purpose pins. You
could then connect that "soft" TAP to whatever you needed in the device.
It would operate independently of the dedicated FPGA TAP.
If the question is "why" my answer would be "I don't know - just because
you can, I suppose" :-) There may be some specific application for
which that makes sense, I just can't think of a good one.
My previous posting was trying to describe how you could create two
separate access points on a single boundary-scan chain consisting of two
devices connected to one another in the usual manner.
fpgavhdl@gmail.com wrote:
> Hi Neil,
>
> Thanx. We understood what ur suggesting but then the problem is both
> the JTAG ports are connected to the FPGA. We dont understnd the purpose
> of the 2nd JTAG port which is directly connected to the FPGA thro TMS,
> TCLK, TDI and TDO pins.
>
> Also the 1st JTAG port sends TMS, TCLK, TDI and TDO to the PROM and the
> PROM gives a Prog_b to the FPGA...which is what we are familiar with.
>
> Thanx again for ur reply and if u can think of some reason why there
> might be 2 JTAG ports shoot me a email.
>
> Regards,
> - Shailesh
>
>
> Neil Glenn Jacobson wrote:
>
>>I am not exactly sure what you are suggesting. Are you proposing
>
> that
>
>>there is one boundary-scan TAP connection that goes through the PROM
>
> to
>
>>the FPGA and another that goes directly to the FPGA without involving
>
>
>>the PROM?
>>
>>If that this the case, since there is in actuality only one physical
>
> TAP
>
>>on the FPGA, that means there will only be one set of TMS and TCK
>>connections which means that if you are trying to access the
>
> FPGA-only
>
>>TAP you will have the PROM traversing through its state machine and
>
> when
>
>>you try to shift data into the FPGA the PROM TDO will be active and
>>shifting, as well.
>>
>>I suppose you could add some extra control logic to guarantee safe
>>operation of the two TAPs but in the end, why would you?
>>
>>If you have a single chain of a PROM followed by an FPGA you can
>
> address
>
>>either device by BYPASSing the other. You can program the FPGA with
>
> a
>
>>bitstream file with the PROM in BYPASS or program the PROM with an
>
> mcs
>
>>or exo file with the FPGA in BYPASS.
>>
>>Does that help?
>>
>>
>>fpgavhdl@gmail.com wrote:
>>
>>>Can an FPGA have two JTAG ports for programming an FPGA chip?
>>>
>>>One is conected thro XCf02s to the FPGA and the other is directly
>>>connected to the FPGA (XC3S400).
>>>
>>>What is the significance of having two ports?
>>>
>>>What files are used for programming this FPGA thro each of those
>
> ports?
>
>
Article: 82092khansa wrote: > Please mention a tool that can accepts VHDL code and converts it into > a circuit schematic(preferably at the register transfer level or gate > level). Does ORCAD have such an option? Xilinx ISE Webpack, which can be downloaded from Xilinx website, offer such an option. It's called Schematic Viewer. It's not as good as the 40K dollars Synopsis or Synplicity tool, but it's free. HendraArticle: 82093
"johnp" <johnp3+nospam@probo.com> wrote in news:1112800047.283747.285480 @f14g2000cwb.googlegroups.com: > Mark & Dave - > > 1) INIT is not pulled low at the end - it does not indicate any error. > It > *does* wiggle as expected at the start of the programming sequence. > > 2) CS is pulled low, the WR signal is attached to a control signal > and appears to be acting properly. > > 3) CCLK appears (using a scope) to be fine. D[7:0] show ample > setup and hold time to BOTH edges of the clock. > > 4) I've tried sending extra 0xFF bytes at the end of the .bit stream, > it doesn't help. I've also tried at the start of the stream. > > I'll keep debugging and let people know wht I find. > > I wonder if it's reasonably possible for an FPGA to die in a manner > where JTAG download works, normal operation works, but Select Map > download fails. Sure. A failure on the CS, WR or CCLK inputs would account for what you are seeing. Can you inspect these connections on the FPGA, or is it a BGA package? You can create a design that outputs signals on CS and WR. That will prove they are not burnt and are connected to the PCB. If you place a static value on the data lines and toggle CCLK for a while, then INIT should go low because of a CRC error. That would prove CCLK is working. Can you configure the FPGA in slave-serial mode? Then your download only depends on the CCLK and D0 inputs. If that works, then most of the configuration circuitry in the FPGA is OK > > Thanks for the help, I'll keep pulling my hair out. > > John P > > -- ---------------------------------------------------------------- Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 82094
I'm trying to do some simulations in modelsim that use one of the xilinx libraries (Specificially the RAMB4_S4_S4), but when I don't include the source to that I get an error: C:/Modeltech_xe_starter6/xilinx/verilog/src/unisims/RAMB4_S4_S4.v(651): Unresolved reference to 'glbl' in glbl.GSR I know that the file glbl.v exists (in my case it's in C:\Modeltech_xe_starter6\xilinx\verilog\src\glbl.v), but I don't know how to make modelsim aware of this file and to use it so that I can simulate the block RAMs. Does anyone elase know how to make modelsim work without having initiated it from within ISE? Thanks, ArlenArticle: 82095
Jan Bruns wrote: > "Jan Bruns": >> in an CPLD-Design (XC95??XL), > > These device have only one "product term" for clocks. Sorry. I think the XC9500 does not have "negedge" flip-flops. Thues it has to use inverted feedback clock to trigger the flip-flops with negtive edge. > > Gruss > > Jan BrunsArticle: 82096
"vax, 9000": > Jan Bruns wrote: >> "Jan Bruns": >>> in an CPLD-Design (XC95??XL), > >> These device have only one "product term" for clocks. Sorry. > I think the XC9500 does not have "negedge" flip-flops. Thues it has to use > inverted feedback clock to trigger the flip-flops with negtive edge. Looks like your're right. But the 9500XL have a programmable clock-inverter. Gruss Jan BrunsArticle: 82097
Hi Austin, Thanks for the reply. First of all, I am using virtex -II. I am concerned about the SEUs occuring in controls of the device(leading to SEFI like behavior). I have obtained a document from SEE consortium that discussess the different SEFIs (like POR, SMAP and JTAG) and the ways to mitigate them. I also found other presentations on xilinx website that discuss the same thing. I wanted to know if there are any other SEFI issues in Virtex-II and the mitigating methods that can be used (and have been used). Thank you, -PraveenArticle: 82098
Jim Granville wrote: > lecroy7200@chek.com wrote: > <snip> > > > > The following link is to my post about the reflected energy causing > > possible problems: > > > That's from a Pin-failure viewpoint. - ie energy damage. > They also spec a MAX peak current. > -jg Yes, I think that's what I had stated. Peter's original app note on the subject. http://klabs.org/richcontent/fpga_content/DesignNotes/signal_quality/xapp096.pdf So far no problems with my testing. If this solves the problem it would be interesting to know if there was some reason that the 3100A's internal doublers were prone to failure because of this.Article: 82099
Eric Smith <eric@brouhaha.com> writes: > Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes: > > Of course. But the one that tied it all together in a single, > > coherent bundle was Patterson and Ditzel. > > Are you asserting that the IBM 801 papers didn't tie it all together > in a single coherent bundle? The earliest 801 paper I'm familiar with was published in 1982. While the project certainly tied things together in a coherent RISC bundle before the RISC and MIPS projects (as both Hennessy and Patterson acknowledge), Patterson and Ditzel is the first publication I'm aware of that does. -- Joseph J. Pfeiffer, Jr., Ph.D. Phone -- (505) 646-1605 Department of Computer Science FAX -- (505) 646-1002 New Mexico State University http://www.cs.nmsu.edu/~pfeiffer
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Compare FPGA features and resources
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