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Hi, It works now. But for some reason, the data read out is one cycle late. Is this how it supposed to be. For example, I set it up so that it store value 0 at address 0, 1 at address 1, 2 at 2, 3 at 3 etc. But when I read back, address 1 read back 0, address 2 read back 1, address 3 read back 2, etc. Thanks, AnnArticle: 81976
Personally I would use wire [3:0] row = 1<<address; // This one-hot decode asserts row[address] 1) Succinct. 2) Commented 3) Why bother with an always block when an assign will do?Article: 81977
Antti Lukats wrote: > "Ziggy" <Ziggy@TheCentre.com> schrieb im Newsbeitrag > news:jOx4e.13997$Vx1.6361@attbi_s01... > >>Antti Lukats wrote: >> >>>"Ziggy" <Ziggy@TheCentre.com> schrieb im Newsbeitrag >>>news:Yww4e.13712$Vx1.3133@attbi_s01... >>> >>> >>>>Alex Freed wrote: >>>> >>>> >>>>>"Ziggy" <Ziggy@TheCentre.com> wrote in message >>>>>news:XYS3e.131292$r55.32410@attbi_s52... >>>>> >>>>> >>>>> >>>>>>Eric Smith wrote: >>>>>>. A reproduction of a 486 or base Pentium would >>>>>>be plenty for what i want to do. >>>>> >>>>> >>>>>Not being a top authority on soft core I'll still observeve that: >>>>> >>>>>1. Implementing a CISC CPU is much more resource consuming than >>> >>>implementing >>> >>> >>>>>a RISC core. >>>>>2. x86 is way crazy because of the need to maintain compatibility with >>> >>>the >>> >>> >>>>>8086's real mode. >>>>> >>>>>In late 80's Intel made a special version of 386 (385 if I remember >>> >>>right) >>> >>> >>>>>that was basically a 368 without the real mode. >>>>>It was much cheaper than a 386 but there were no takers: x86 is used so >>> >>>much >>> >>> >>>>>only because of the huge volume of written code, >>>>>not because it is a good architecture. >>>>>If I had to go the CISC way, I'd much rather clone a 68000. Just as > > much > >>>>>software written and a considerably better >>>>>instruction set. >>>>> >>>>> >>>> >>>>But in todays world, does anything actually use >>>>the 'real mode' on an x86 chip? >>>> >>>>Though i do agree that the 68k is a much better >>>>chip, the x86 has a larger 'generic' software >>>>base. >>>> >>>>I think the 68k has been done however.. I just >>>>dont remember where i saw that at. >>> >>> >>>something is at opencores not sure how useabe it is >>> >>>antti >>> >>> >>> >> >>I think you saw the 6800 core.. i dont think there is a 68000 core >>unless i missed something, which is always possible. > > > http://www.opencores.com/projects.cgi/web/k68/overview > > 68K > but as said I have not evaluated it, so not sure how useable it is > > antti > > > > Wonder how i missed it.. tksArticle: 81978
NET "cp100" TNM_NET = "cp100"; TIMESPEC "TS_cp100" = PERIOD "cp100" 10 ns HIGH 50 % INPUT_JITTER 400 ps; TIMEGRP "cp100anxffs" = FALLING FFS; TIMEGRP "cp100axffs" = RISING FFS; TIMEGRP "TG_S1S2D_INPADS" = PADS( "s1d<0>" "s1d<1>" "s1d<2>" "s1d<3>" "s1d<4>" "s1d<5>" "s1d<6>" "s1d<7>" "s2d<0>" "s2d<1>" "s2d<2>" "s2d<3>" "s2d<4>" "s2d<5>" "s2d<6>" "s2d<7>" ); TIMEGRP "TG_S1S2D_INPADS" OFFSET = IN -3 ns VALID 5 BEFORE "cp100" TIMEGRP "cp100anxffs" ; I'm using a virtex2 part with a differential 100mhz lvpecl clock. s1d(x) and s2d(x) go directly into FFs clocked on the falling edge of the 100mhz clock. The data at the s1d(x) and s2d(x) input pads are valid 2ns before the falling edge and 3 ns after. Are my constraints setup correctly above? I'm confused because I'm using the falling edge of the 100mhz clock. And I am getting hold errors when I run the Timing Analyzer with -min times but not with -4 times. Any and all comments appreciated. Thanks.Article: 81979
At one time I worked for a company that did chip IP reverse engineering usually by the stitched photo capture route, long before India was doing anything in that area and also long before FPGAs could host anything but glue logic. Such projects used to be billed for many 100Ks or low $mil or so, after all its incredibly labour intensive typically had half a dozen sets of eyeballs categorizing stitched plots and then figuring what the netlist was from that. Atleast one contractor actually did lose his marbles and was later found by police doing some strange things.... It can be automated to some extent but that requires the scanned images to be "corrected" before tiling. And getting EBES pics didn't seem to work out too well either. We just used robo step & repeat high end micro photography and sweat & tears. Much more fun when it was transister level since you never quite knew what sort of circuit structure would pop up and that needed EEs rather than technician level to put a netlist together that made any sense but the flip side was that hand layed out chips are easier for humans to figure out too if you think the same way. The huge std cell arrays though have no logical structure to guide, all random placed so nothing much to infer. We even had a nice little DSP project from a former great company that had to reverse engineer its own chip since maybe 15yrs had passed and that was many technology generations old back to nmos days but they did give masks and vecs, just no netlist. Usually the customer for such services never sees any of the results, not even the netlist. They forward design their own clean room compatible design as best they can from open docs but when they need to know what the chip is supposed to do with a set of vectors, they'd get our guys to run same vecs on extracted netlist on some HW simulator. And only the really big companies could afford that sort of service but had to have legally safe way of checking their own designs. Usually getting a license from a competitor was unacceptable to them so they dig in an clone the part. regards johnjakson at usa dot comArticle: 81980
Here is a solution for your noise, http://www.zalman.co.kr/eng/product/view.asp?idx=151&code=020 The cost could not be the issue if you start using Altera devices :-) Thomas Womack wrote: > Is there any way of using the Xilinx toolchain on a Mac? > > I have become spoiled by my Mac Mini, and unpacking my loud PC > just to run place-and-route seems inelegant. > > TomArticle: 81981
Hendra wrote: > Both of the following 2 always blocks should synthesize to a decoder. > > always @(address) > case (address) > 2'b00 : row = 4'b0001; > 2'b01 : row = 4'b0010; > 2'b10 : row = 4'b0100; > 2'b11 : row = 4'b1000; > endcase > > always @(address) > row = 2**address; > <snip> Not that this answers your question... but I believe both of these code fragments are behavorial code. Structural code instantiates components. The style of code I use is always based on the synthesis tool's guidelines doc. It's the first thing I read before writing any code.Article: 81982
Keep in mind that the write data goes to the write address at the sampling clock edge. Read data comes from the read address sampled on the clock edge becoming valid a few nanoseconds later. If you're looking at what the address is in your simulation when you look at the data that's coming back from the BlockRAM, they will be one cycle skewed because the address you see is the address for the read data AFTER the clock edge. These memories are synchronous. Look at the Xilinx page on the primitive - http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/lib/lib0346_332.html - and you'll see the logic table for the BlockRAM. Note that there are three different modes for reading and writing at the same time for this single port memory set by a parameter. The RAMB16_S9_S9 is a dual-port memory that allows independent read and write addresses to the same memory array. "Ann" <ann.lai@analog.com> wrote in message news:ee8d229.7@webx.sUN8CHnE... > Hi, It works now. But for some reason, the data read out is one cycle late. Is this how it supposed to be. For example, I set it up so that it store value 0 at address 0, 1 at address 1, 2 at 2, 3 at 3 etc. But when I read back, address 1 read back 0, address 2 read back 1, address 3 read back 2, etc. Thanks, AnnArticle: 81983
On Tue, 05 Apr 2005 15:26:48 GMT, "John_H" <johnhandwork@mail.com> wrote: >wire [3:0] row = 1<<address; // This one-hot decode asserts row[address] >1) Succinct. >2) Commented >3) Why bother with an always block when an assign will do? Fascinating... I can't easily think of another four lines of text that could be as diametrically opposed to my own position as these. Point by point... Succinct - yes, but it needs a comment to make it easily comprehensible, thus dramatically reducing the (IMHO imaginary) benefit of brevity. Why is brevity good, for heavens' sake? Any half-decent piece of code will be at least 50% comment, so there is at the very most 50% saving to be made from brevity of code - and nothing, not even the tiniest thing, that compromises clarity and maintainability is worth that. Code is written once but read (and modified) often; saving a few keystrokes is not something that's worth chasing. Commented - yes, for sure. But the comments are just that, comments; they can get out-of-step with the code, and nobody gets to check. If, by writing somewhat more verbose code, I can "animate" the comments so that they are part of the code's functionality, then I don't have that risk. In general I am deeply distrustful of comments that describe the behaviour of procedural code, which tends to be almost self-evident to anyone skilled in the language; the teacher in me still comes out in a cold sweat at the sight of this vacuity: i = i + 1; // increment i So, let's have the comments as far as possible embedded in the code itself. Intriguingly, the most useful part of your commentary, where you say "assert row[address]", could easily be a piece of procedural Verilog (see my earlier post). Note, by the way, that assertions provide an even better way to add "animated comments" that *are* checked by tools. An assertion could easily check for one-hot-ness of the output, for example. Why bother with always? - Because it gives me a lot more room to manoeuvre if I later decide I need to change something. Especially in Verilog, where the change from "assign" to "always" also impacts the declaration of various things, I lean towards using "always" right from the start so that there's less to change later. Of course there are exceptions: some places you have little choice but to use assign (three-state drivers, etc); certain patterns of glue logic, like fixes for the polarity of strobe signals, are nicer done as assigns. But any logic with some real functionality behind it IMHO belongs in a procedural block. These are emphatically my own opinions and I am very much aware that many skilled people will profoundly disagree with me. I'm sure there is a place for both points of view, and for many in between. Just so long as everyone is aware that the choice is not obvious :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 81984
I'd have to vote with John_H here but I know many won't.
wire [3:0] row = 1<<address; // about as good as it gets
When I see code that describes an obvious TTL nobrainer structure
using more than a few lines of code I start to wonder, are we boosting
line count or being succinct.
If it can be done in a few chars or 1 line why use any more.
Even more so giving every minor structure it own always begin .. end or
assign {} when a lot of related assignments can be bumped into 1 larger
always / assign cluster for the overall function. Same as putting tiny
pieces of related logic on separate schematics sheets.
We dont usually see C programs with a set of {} around each and every
statement, only logically related code blocks. Same as over (())
expressions, my C VC6 compiler always nags me because it assume I can't
remember precedence rules for <<& bit extracting so I have to put in
more () than I need to keep warnings down.
But JB is right, always question evrything you do to see if there are
better ways to do it.
The Doug Smith book gives out pretty good examples of this sort of
thing too in several languages for ASICs & FPGAs all meant to
synthesize well with the schematics.
My 2c from an old APL kind of guy
johnjakson at usa dot com
Article: 81985All, I know that we have customers who have ASICs on obsolete process nodes, which can not be ecconmically obtained. We have exactly the same problem, as is evidenced by our phasing out of the XC2000, and the XC3000 (although we still supply the XC3100A in some packages and parts for a while yet). In fact, I talked with one company that converts about 50 ASICs a year into our FPGAs, because they can't fabricate these old ASICs any longer. One big advantage they have, is they have schematics, verilog, or VHDL, so they can simulate, and put together test benches. Without the schematics, or HDL, it is a very tough job to convert to anything at all. AustinArticle: 81986
When one has read a beginner/introduction book of VHDL what is a good second book to read? And where to go next? (Student)Article: 81987
Hi everybody! Does somebody found a solution. I have the same problem MArtinArticle: 81988
Hi, Are ISA covered by patents or trademarks? Is it allowed to develop a processor core for a popular ISA as long as no reference is made to any of the original company trademarks? Many thanks for your comments. EricArticle: 81989
I think the PITA part of vision is the hardware simulation. It is
usually dog slow since it is a simulation usually of multiple video
frames and the hardware might be working at 10's to 100's of MHz (eg,
one vision system I designed used a 108 MHz process clock and NTSC video
input. A video field takes 1.8 Million clocks, or the better part of a
day per field to simulate the full FPGA design).
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 81990What I need is some kind of roadmap how to learn more VHDL. How did you all get so good in this field of work, a lot of hard work (of cause)? :-) "Elektro" <blabla@bredband.net> skrev i meddelandet news:4252bf73$0$43990$14726298@news.sunsite.dk... > When one has read a beginner/introduction book of VHDL what is a good second > book to read? > > And where to go next? > > > > (Student) > >Article: 81991
Karl wrote:
>Here is a solution for your noise,
>
>http://www.zalman.co.kr/eng/product/view.asp?idx=151&code=020
>
>The cost could not be the issue if you start using Altera devices :-)
>
>
>
that doesn't address the disk drive noise. 15000 rpm SCSI drives are
pretty noisy.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 81992I could also say it wasn't that long ago that I would have written DEC4_1 u0 (.addr(i), .out(o)); // or whatever the std cell was called Now that synthesis has fully taken over except at the very top end of the speed curve, its not so necessary, only on interesting block level. Although instancing of blocks is usually considered structural or schematic thinking, you can then put anything at all into the module that describes that it even the original case statement as the visual clutter from it is now elsewhere. There is another way to have it both ways and that is to use a folding text editor, click on the 1 liner and see the the 1 or 5 or 100 lines it represents. Pretty much a schematic thing to do to when you could push down into sub sheets. Does anyone actually use such a thing, recomendations esp Windows, I half suspect Emacs can do it but never took to it. johnjakson at usa dot comArticle: 81993
"Eric DELAGE" <"eric UNDERSCORE delage AT yahoo DOT fr"> schrieb im Newsbeitrag news:4252c3dc$0$3114$8fcfb975@news.wanadoo.fr... > Hi, > > Are ISA covered by patents or trademarks? Is it allowed to develop a > processor core for a popular ISA as long as no reference is made to any > of the original company trademarks? Many thanks for your comments. > > Eric It all depends what you are up to and against whom, some companies are very quick to get their lawers involved. However I think it is not actually possible to fully copyright an ISA, because 1) languages can not be patented, any one can learn another language if he pleases so. That is covered by basic human rights I hope. 2) an ISA can be considered a description of some formal language, in any case you yourself can learn to understand the bytecode, etc.. that cant be prohibied. 3) You can buy a smart-dog and teach that dog that ISA (if you are able too), its isnt prohibited to try. 4) You can buy and FPGA and teach that FPGA to understand what you learned in step[2] - that again can not be directly forbidden. Now, that doesnt mean the lawers want come after you, they can try at least. But by being VERY VERY Careful it is possible to make the case a 'no case' for the lawers. But you really have to have a 'clean implementation' - and you have to withstand any pressure from the lawers who try to prove the opposite. ARM shuts down, nnARM was forced underground/dead, picoturbo was closed down MIPS shoots as well SPARC is Open for anyone to implement. that the reason why Gaisler did choose SPARC for their space stuff Altera tolerates the GPL version of NIOS-I, but is also trying to shut down OpenSource NIOS-II Xilinx has said they have nothing against 3rd MicroBlaze implementations my 2cents AnttiArticle: 81994
Benjamin Menküc wrote: > Hi, > > I want to build a dvi to lvds konverter. Betweeen there two busses, I > have a 24 bit parallel bus. Eventually I want to do some signal > processing with the parallel data too. Will an FPGA be fast enough for > this task? > > regards, > Ben I designed a 16b datapath running @120MHz for a Xilinx Spartan-3 XC3S1000-FT256-4 (the slowest one) w/o any problem as long as you use a good VHDL synthesizer. The FPGA does not cost more than a few 10s$. So It's possible. Notice however that multipliers are scarce ressources for FPGA. Video processing w/ its trend to use // implementations (to sustain the sample rate) can require many of them if you don't take this constraints into account from the very beginning. EricArticle: 81995
> Are ISA covered by patents or trademarks? Is it allowed to develop a > processor core for a popular ISA as long as no reference is made to any Depends on the ISA. ARM, for instance, is covered by thick IP protection layers, and is vigorously defended. 8051, not so much :)Article: 81996
Nemesis wrote: > Mentre io pensavo ad una intro simpatica "Nemesis" scriveva: > > >>>ModelSim needs an env variable called LM_LICENSE_FILE which points to >>>the license.dat file. When you install ModelSim as administrator I guess >>>that this env. variable is installed in the private space of the >>>administrator. Have you verified that LM_LICENSE_FILE is defined as >>>system variable and not user variable? Can you see it when you log in as >>>a normal user? >> >>Now I can't control (I'll see tomorrow) but the error says that a "text >>file" cannot be written. >>However I'll try setting this environment variable. > > > I checked, the environment variable is correct. Today I saw that if I > open the licensing wizard before opening ModelSim, it correctly reports > that the license is valid, but when I open ModelSim as User it stops > working. > I never use the licensing wizard because it does nothing more than setting the variable and checking the hostid (which is unnecessary if you ask for your license through a direct internet connection). Are you using WinXP Pro? Are the WinXP permissions correctly set (installation directory, user directory where ModelSim will create a default modelsim.ini)? EricArticle: 81997
In article <qhpsxanzti.fsf@ruckus.brouhaha.com>, Eric Smith wrote: > > But if there isn't a patent on an architecture, you don't need a license > to implement it. The purpose of the license is to grant you a right that > was taken away from the patent. If there's no patent, you haven't been > denied the right. No, you are wrong. I do not need a patent on my IP in order for me to license it to you. It's called copyright. -- [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salaxArticle: 81998
Repeating myself "Doug Smith", look him up for both VHDL & Verilog. google groups for vhdl books, use amazon engine thats what search engines are for There must be other pure VHDL books too but I can't say. Cohen IIRC, and maybe Palniker (verilog but think he did VHDL follow on). More and more authors seem to do both languages now, either same time or follow with 2nd edition. johnjakson at usa dot comArticle: 81999
In article <42517aee_4@x-privat.org>, Symon wrote: > > Naahh, I sent a copy of the databook to Pune, India. Three months later... Black box... as in I do not have the databook. -- [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax
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