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Phil Tomson wrote: ... > Well, I haven't had a successful run of the GUI yet. I'll have to look > at it on a Windows machine at school. > > BTW: is it possible to set up the project without the GUI? I'm assuming > it's just some sort of text file (the project file). > > Phil Phil, yes, it is possible to replace the GUI with a script. At least for ISE. I have not been able to figure out hot to do the same for EDK (yet). I have attached my script. Please note this is something I am using internally and it was not meant to be flexible or easily portable. Besides the main "comp" script you need a few setup/scripts for various tools. This is all from my USB_OTG project, so you have to search for those keywords and replace them for your project. I think I have problems attaching files to my news post, so I uploaded them to: http://www.asics.ws/ise/ Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 82776
"Phil Tomson" <ptkwt@aracnet.com> wrote in message news:d3qdl402ql5@enews3.newsguy.com... > In article <iV08e.7071$yq6.1107@newsread3.news.pas.earthlink.net>, > Bob <nimby1_notspamm_@earthlink.net> wrote: > >Dave, > > > >I'd estimate at least $700K/yr for Atlanta, and about 20% more for San > >Jose -- especially since this person will need to do technical > >documentation/marketing material. > > > > $700K/yr! Wow, where do I sign up?! > > Phil Me too! I have already sick of with having to deal with that dirty rascal in this office.Article: 82777
I would like to make it into a hobby, but my pay is too low to afford a decent board and accessories. I realized that it's interesting to combine a MSP430F449 and a xc2v2000 to run a robot. "Phil Tomson" <ptkwt@aracnet.com> wrote in message news:d3p8ng01f0i@enews2.newsguy.com... > I've been following this newsgroup off and on for the last couple of years > and I notice a steadily increasing amount of traffic here. The volume > seems to be approaching that for various open source language > forums/newsgroups thta I also follow. > > I'm curious: > Any speculation as to the split between hobbyists and paid FPGA > practicioners posting/lurking here? > > It would seem that with the advent of cheap FPGA prototyping boards, > devices and free/semi-free design tools that a lot of hobbyists are trying > out FPGAs. After all, you can get into FPGA design now for about the same > or less money than it takes to get into Lego Mindstorms - which is just > amazing when you think about it. > > Also, are there FPGA user's groups springing up out there? I'm thinking > of starting one here in Portland, OR. Any interest? > > Phil >Article: 82778
If you want to use a LUT as a 16b table with values you fill in driven
by 4b inputs, forget the old schematic way. Learn either V language
synthesis subset, also get the Doug Smith and Palnitker books too.
in pseudo Verilog/HDL/C
wire6 my7b;
wire4 my4binput;
switch(my4binput) {
case 0: my7b=1; // the actual segment values are in the starter kit
manual.
case 1: my7b=0;
case 2: my7b=1;
case 3: my7b=1;
...
case 15: my7b=42;
}
Should synthesize perfectly well and simulate after you fix up the
syntax.
Also in the webpack find your way over to templates menu for examples
of most everything (simple) you could cut n paste n edit. Case
statements are in there.
regards
johnjakson at usa dot com
Article: 82779For each schematic sheet you can generate a symbol (the inputs and outputs of that sheet become the ports of that symbol). This symbol can be used in other schematics (also multiple times), so you have a hierachical design. Thomas www.entner-electronics.com "Len" <LeonardGabrielson@adelphia.net> schrieb im Newsbeitrag news:1113794842.776313.319400@o13g2000cwo.googlegroups.com... > Can someone please tell me how to make a multi-page schematic in > Altera's Quartus II software? I can't seem to find anything on this in > the documentation. > > How is connectivity handled between the pages?... just by the net or > node name? > > Thank you!! > Len >Article: 82780
Try Help\Tutorial... Dan.Article: 82781
Austin, Thanks for the excellent post. I agree with your sentiments in that salary isn't everything (indeed - it is far from it). Your brother hit the nail on the head for sure. The main thing I think is that you enjoy what you do and get paid such that your employer *values* you and you feel valued. This leads to stimulating environment where employee and employer respect each other and neither party feels like they are getting a bum deal. Of course, you need an idea of what your value is to make sure the salary fits (or thereabouts!), hence my post. I also agree that an engineer with a bachelors degree and years of experience is worth way way more than someone with a PhD an next to no experience (2000 - 2004 was a good time to be doing a PhD on DSP on FPGAs however given the state of the industry! :-) ) Incidentally, my wife is always telling me how much smarter than me she is (she is). I just wave my PhD certificate at her when that happens - drives her nuts... ;-) Cheers, DaveArticle: 82782
Peter Alfke schrieb: > But nobody will ever accuse us of hiding... And just to make sure that nobody does you posted your message four times. ;-) Kolja SulimmaArticle: 82783
Seems I can't attach files in the newsgroup. The problem is as follows:
I have defined the types uint8 and uint16 in "mavision_package.vhd". I use
these to define the ports of "mavision_top.vhd". If I check syntax for
"mavision_package.vhd" and "mavision_top.vhd", I get no warnings or error
messages from ISE. But, if I try to automatically derive a Test Bench
Waveform from "mavision_top.vhd", all uint8 and uint16 ports are defined as
std_logic ports.
This can be seen in "TBW1.tbw" or "TBW1.vhw". This is the reason, why I cant
run a simulation.
Where's the mistake?
Here are the package an the main file:
################################################################################
package
################################################################################
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mavision_package is
type uint8 is range 255 downto 0;
type sint8 is range 127 downto -128;
type uint16 is range 65535 downto 0;
end mavision_package;
################################################################################
main
################################################################################
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
library mavision_lib;
use mavision_lib.mavision_package.all;
entity mavision_top is
port (CLK_Pixelclock : in std_logic;
Data_in : in uint8;
LVAL : inout std_logic;
FVAL : inout std_logic;
PVAL : out std_logic;
ROWS : out uint16;
COLS : out integer
);
end mavision_top;
architecture Behavioral of mavision_top is
component tstr is
port (CLK_Pixelclock_S : in std_logic;
Data_in_S : in uint8;
LVAL_S : inout std_logic;
FVAL_S : inout std_logic;
PVAL_S : out std_logic;
ROWS_S : out uint16;
COLS_S : out integer
);
end component tstr;
begin
tstr_1 : tstr
port map (CLK_Pixelclock_S => CLK_Pixelclock,
Data_in_S => Data_in,
LVAL_S => LVAL,
FVAL_S => FVAL,
PVAL_S => PVAL,
ROWS_S => ROWS,
COLS_S => COLS
);
end Behavioral;
################################################################################
I really would appreciate if you'd find the time to have a look at it.
Greets,
Hanns-Walter
"Dipl.-Ing. Hanns-Walter Schulz" <ha.schulz@tu-bs.de> schrieb im Newsbeitrag
news:d3o61m$7d2$1@rzcomm2.rz.tu-bs.de...
> Using the Xilinx Project Navigator, I created a project and added a
> package definition (vhd-file) at the very top level. Inside this package I
> defined some types of integers, signed and unsigned.
> I included this package in all other vhd-files of the project with "use
> my_package.all". All syntax checks were successfull.
> Now the problem: When I automaticaly create a Schematic or a Testbench
> file, the package definitions seem to be ignored: all ports defined in the
> original vhd-file as integers (8bit) are now only std_logic. This can be
> seen directly in the schematics drwaing, or the testbench grafical display
> or the testbench vhd-file.
> I get an error message saying:
> "Compiling vhdl file ##_top.vhd in Library work.
> ERROR:HDLParsers:3014 - ##_top.vhd Line 9. Library unit my_package is not
> available in library work.
> WARNING:HDLParsers:3465 - Library as no units. Did not save reference file
> xst/work/hdllib.ref for it."
>
> Does anyone know where the error is located?
>
> --
>
> __________________________________________
> Dipl.-Ing. Hanns-Walter Schulz
> TU Braunschweig
> Institut fuer Luft- und Raumfahrtsysteme
> Institute of Aerospace Systems
> Hermann-Blenk-Str. 23 Tel.: ++49 531 391 9968
> D-38108 Braunschweig Fax: ++49 531 391 9966
"Dipl.-Ing. Hanns-Walter Schulz" <ha.schulz@tu-bs.de> schrieb im Newsbeitrag
news:d3o61n$7d2$2@rzcomm2.rz.tu-bs.de...
> Using the Xilinx Project Navigator, I created a project and added a
> package definition (vhd-file) at the very top level. Inside this package I
> defined some types of integers, signed and unsigned.
> I included this package in all other vhd-files of the project with "use
> my_package.all". All syntax checks were successfull.
> Now the problem: When I automaticaly create a Schematic or a Testbench
> file, the package definitions seem to be ignored: all ports defined in the
> original vhd-file as integers (8bit) are now only std_logic. This can be
> seen directly in the schematics drwaing, or the testbench grafical display
> or the testbench vhd-file.
> I get an error message saying:
> "Compiling vhdl file ##_top.vhd in Library work.
> ERROR:HDLParsers:3014 - ##_top.vhd Line 9. Library unit my_package is not
> available in library work.
> WARNING:HDLParsers:3465 - Library as no units. Did not save reference file
> xst/work/hdllib.ref for it."
>
> Does anyone know where the error is located?
>
> --
>
> __________________________________________
> Dipl.-Ing. Hanns-Walter Schulz
> TU Braunschweig
> Institut fuer Luft- und Raumfahrtsysteme
> Institute of Aerospace Systems
> Hermann-Blenk-Str. 23 Tel.: ++49 531 391 9968
> D-38108 Braunschweig Fax: ++49 531 391 9966
>
>
Article: 82784Hi, I am trying to debug a simple application which is running on a powerpc. I can set breakpoints (in gdb) and run until the breakpoint is reached. But after coming at the breakpoint, I can not step throug the code. If I choose "Next" in gdb, the program will not continue, but stands still at the current breakpoint. If I remove the breakpoint and place it somewhere else, I can choose continue and run the program till the next breakpoint. I have found out that disabling the interrupts helps a lot. If the interrupts are disabled I can step through my code. My question is: should it also be possible to step through the code with interrupts enabled and if so, what could be the problem in my case that it is not working? The interrupts I have are an uart interrupt, an user defined interrupt and the timer interval interrupt. TIA, FrankArticle: 82785
There is a second reason to be anonymous.. I get 200+ spam emails a day.. so I don't have a valid email address for publicly searchable news groups... but I have been an engineer for over 20 years... and my email address is about as old too... In fact I designed the modems that connected the ISP to the university. I think it had a 3000 series fpga from memory :-) Simon "Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1113767492.507934.154770@f14g2000cwb.googlegroups.com... > I know that Austin's Sunday-morning concern is valid, and it stems from > previous incidents, where unfriendly people, (sometimes referred to as > Competitors) have started anonymous mudslinging campaigns. It's so easy > to do, and hard to spot. > None of us says that this is the case with George Mercury (at least he > posts a reasonable name), but anonymity is known to be an invitation to > mischief. > That's all. > Peter Alfke > PS: Austin and I always give our company affiliation. But sometimes we > are too lazy to type, or we want to demonstrate that this is personal > opnion, like this one. But nobody will ever accuse us of hiding... >Article: 82786
Len wrote: > Can someone please tell me how to make a multi-page schematic in > Altera's Quartus II software? I can't seem to find anything on this in > the documentation. Open the Block you wish to make into a nested symbol Select File | Create/Update | Create Symbol Files for Current File Open the symbol / libraries dialog You will find your new symbol under the "Project" branch If you ever have cause to change the nested module's I/O ports, you need to repeat the "Create Symbol Files for Current File" step, then open the module that references it, right click, and select Update.Article: 82787
Phil Tomson <ptkwt@aracnet.com> wrote: > I think I'm about to try running the Win32 version under Wine - pretty > sad that their Linux version is so crappy. You'd think they'd have better > understanding of the Linux platform than this If you run with a 2.6 Kernel, you must do as root echo 1 >/proc/sys/vm/legacy_va_layout Linux Memeory layout was changed in 2.6 , now pointers to memory between 0x80000000 and 0xBFFFFFFF can escape to the windows programm and ISE stumbles about some signed/unsigned problem I guess. Also the Output windows now uses more RichEdit functionality that is not yet implemented in the Wine builtin Richedit implementation. Use native RicheEdit so long. > - maybe Xilinx should hire some of us? ;-) They should talk to Codeweavers. I guess for the money Xilinx spends on WindU, they could have Codeweavers weed out a lot of Problems in Wine (and perhaps some in the Xilinx code) so that ISE would run flawless in Wine. No more need for a WindU license and a single source tree... > Hopefully ... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 82788
Maybe try iscanf, which is an integer only version of scanf. Cheers, JonBArticle: 82789
hi there.... first of all the development board that u r using contains a serial PROM for configuration in case u r not programming through the JTAG. Once u select JTAG option in the programming environment the FPGA is configured directly using the JTAG without the use of the PROM. The JTAG uses TDI,TDO,TCK and TMS pins for this purpose which connect to the respective pins of the FPGA. The TDO from JTAG connector goes to the TDI of FPGA and TDO of FPGA goes to TDI of JTAG. TDI and TMS are connected as it is. Coming to storing ur program, first of all u hav to generate a serial PROM configuration file. This is different from the configuration file generated for the JTAG mode. This option u can find in the create programming file tab. Then u hav to program ur serial PROM. This is mostly flash that u can program via serial port and the software for the same will be provided with the tool itself. Now if u r planning to develop ur board then it is best to go for a platform flash solution from the xilinx the compatible platform flash PROM for your spartan IIE device ( XC2S200E) is XCF02S. This has an advantage of getting programmed directly with a JTAG cable. Just search this on xilinx site n read about these PROMs. These r really a wonderful solution so u dont need a third party programmer tool also. Hope it helps... thanx n regards, PUNEETArticle: 82790
Hi all, thank you very much for your answers and questions. I now have some more specifics about the system-to-be: - there are 4 ccd cameras with 1024 pixel which are read out each by 1 FPGA (Spartan) - this is already done and the system we want to build our's on. - those FPGAs behind the CCD cameras send out byte arrays. We aim at producing about 60 MByte/sec - our part now is to read those byte arrays (all 4) and do edge detection on it. This has to be done in real-time. - if this is too heavy we could imagine doing the edge detection separate for each of the 4 data streams (still in real-time), although this would result in significantly more work to be done in consecutive steps. - The parameters of the edge detectors must be configurable in near real-time. - The output of our FPGA(s) is a figure for number and size of identified objects of interest. Well now, do you still think it is feasable? Would a Spartan 3 do it or is a Virtex needed (one with DSP slices)? I very much appreciate your input! Thanks a lot, ChristianArticle: 82791
Hi newsgroup, maybe someone of you out there has faced some similar problem: I want to sample 16MHz data with a 125MHz clock. But 125/16 = 7.8125 Is there some tricky method to perform this kind of oversampling ? The only thing I know is the Bresenham algorithm, but could that be the solution ? Thank you in advance. RgdsArticle: 82792
Hi, Does anyone know where I can get hold of an Altera Logic programmer card (lp6). Any info appreciated. Cheers Alan.Article: 82793
Hello guys, I am working on a project which contain some IP core which is avaiable to me in EDF netlist form. I am having the following doubt I synthesis my verilog code in synplify and implementing this EDF in the ISE. Now since i have my design in EDF format , how can i instantiate a new IP core which in EDF format in my design which is also in EDF file. Is there a way by which i can instantiate the netlist of IP core in by verilog code. If so how do i do that? waiting for your reply, Thanks and regards williamsArticle: 82794
williams wrote: > Hello guys, > > I am working on a project which contain some IP core which is avaiable > to me in EDF netlist form. I am having the following doubt > I synthesis my verilog code in synplify and implementing this EDF in > the ISE. Now since i have my design in EDF format , how can i > instantiate a new IP core which in EDF format in my design which is > also in EDF file. > > Is there a way by which i can instantiate the netlist of IP core in by > verilog code. If so how do i do that? > waiting for your reply, > Thanks and regards > williams Make it a synthesis black box. The synthesis tool will put a placeholder for the undefined module and ISE should put appropriate EDIF file where applicable as long as the instantiated EDIF is stored in one of the macro search folders. Declare such module as follows: module CBD16CE(CEO,TC,Q,C,CE,CLR) /* synthesis syn_black_box */; output CEO, TC; output [15:0] Q; input C, CE, CLR; endmodule Aldec's Active-HDL has also an utility that allows to merge all HDL files in the design including EDIFs so you combine everything after synthesis and pass flat netlist to the place-and-route (usually faster). EGArticle: 82795
On Mon, 18 Apr 2005 11:47:37 +0200, "C. Peter" <die_les_ich_nicht@gmx.net> wrote: >- there are 4 ccd cameras with 1024 pixel which are read out each by 1 >FPGA (Spartan) Line scan cameras, then. OK. As you say below, they usually produce data slightly faster than typical video-compatible area cameras. >- those FPGAs behind the CCD cameras send out byte arrays. We aim at >producing about 60 MByte/sec > >- our part now is to read those byte arrays (all 4) and do edge detection >on it. This has to be done in real-time. If the edge detection is one-dimensional, in the direction of the line scan, this is very easy indeed and would fit in even the cheapest modern FPGA. However, if your edge detection needs 2-D processing as I guess it does, then you need to store recent video lines and you will certainly need lots of bandwidth to internal memory because you need access to more than one line to process each pixel. >- if this is too heavy we could imagine doing the edge detection separate >for each of the 4 data streams (still in real-time), although this would >result in significantly more work to be done in consecutive steps. It depends on the edge detection algorithm. Something simple like a 4-point Sobel would cause no trouble at all. Edge detectors with more complex branching algorithms (Canny?) would be much trickier. >- The parameters of the edge detectors must be configurable in near real-time. In itself this is unlikely to be a problem. You have several dead pixel times at the end of each line; during this time you can copy parameters, from a RAM where they've been written by software, into the registers where they will be used. >- The output of our FPGA(s) is a figure for number and size of identified >objects of interest. So presumably you are not only edge detecting, but also keeping track of those edges and inferring object outlines from them? That kind of task typically creates variable-sized data structures, which don't map on to FPGA implementation very well unless there are other application-specific constraints that you can exploit in the algorithm design. Depending on the exact nature of the object-finding, this may be good work for a small embedded CPU (Microblaze etc) in the FPGA. >Well now, do you still think it is feasable? Would a Spartan 3 do it or is >a Virtex needed (one with DSP slices)? You'll need to be much more specific about the edge detection and discrimination algorithms. Things like how many multipliers (if any) are needed by the area convolution operations. We, and many other organisations, would be in a good position to help with specifics of implementation - but there's no way you can start to estimate required hardware resources until you have a clear description of the required algorithms. Only then can you begin to bash the algorithms into an FPGA-friendly form and start allocating hardware to them. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 82796
On 18 Apr 2005 03:03:25 -0700, ALuPin@web.de (ALuPin) wrote: >I want to sample 16MHz data with a 125MHz clock. > >But 125/16 = 7.8125 > >Is there some tricky method to perform this kind of oversampling ? Why do you need any tricks? You have at least 7 cycles of your fast clock in which to sample each data point. The samples will be either 7 or 8 clocks apart. So, you look at the 16MHz clock and use it to create a clock-enable in the 125MHz clock domain. If you don't have access to the original 16MHz clock, you can either try to recover it by locking a digital PLL on to the data transitions (7x oversampling is *just* about enough to be able to do this easily) or you can use dead-reckoning by using a numerically-controlled oscillator (NCO) to generate 16MHz sampling pulses with a phase jitter. And yes, an NCO is effectively an implementation of Bresenham. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 82797
Thanks everybody for your help.Article: 82798
khansa wrote: > I am a beginner in VHDL using Xilinx Project Navigator 5.2i to design > a 8-bit by 8-bit binary array divider, the maximum pad to pad delay > that the 'Text-based Post Place & Route Timing Report' showed for the > program below was found to be 77.233 ns (from m<1> to r8<0> and from > m<2> to r8<0>), but when the output port 'f' was removed from the > design, the maximum pad to pad delay increased to 85.713 ns (from m<0> > to r8<4>). The only reference to 'f' in the architecture is in line > number 29 as > "f <= r2(8) or r3(8) or r4(8) or r5(8) or r6(8) or r7(8) or r8(8);" > I was wondering how this increase in delay happened when a port was > removed. > Also, the maximum combinational delay estimate in the synthesis report > is and 130.499 ns from m<0> to q<0> (without the port 'f') and 130.598 > ns from m<0> to f (with the port 'f'). > The device family is Spartan2 and device is xc2s15, package is cs144, > speed grade is -6 and design flow is XST VHDL. > It's important to note that post place-and-route timing depends heavily on the place and route. That is, changes in the input design that would seem to speed up the outcome may not due to the place and route finding a better solution to the seemingly slower design. The first place to look is in your timing constraints. The place and route engine usually stops to optimise as soon as the constraints are met, thus not finding a potentially "optimum" placement / routing. Also if you only constrain maximum pad-to-pad timing, removing the path that originally had the longest delay would allow the tools to take fewer optimization passes and thus probably not do as good a job on the remainder of the design. I doubt that removing port 'f' from your design caused the synthesis to create more logic levels. You can check this by looking at the post-translate static timing rather than post place-and-route. Regards, GaborArticle: 82799
Hi everyone, Paul Boven wrote: > I think I can wrap my head around the concept of the LUT allright, but > the problem I'm having is that I can't find where in the Xilinx WebPack > software I get to determine the contents of the LUT. Found it: In component properties, set the INIT attribute. I had tried this before but hadn't yet realised that this value needs to be in hexadecimal, binary won't fit. Regards, Paul Boven.
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