Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
stud_lang_jap@yahoo.com (williams) writes: > Is there a way by which i can instantiate the netlist of IP core in by > verilog code. If so how do i do that? > waiting for your reply, Make a dummy module with same interface in your HDL. Tell your synthesis tool that this is a black box. You can then merge the edif netlist in ngdbuild. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 82801
Phil Tomson wrote: [...] > > What is the 'broken library support' issue? Howdy Phil, In the VHDL source flow, ISE creates a project file (which as you probably guessed, is text) for that synthesis tool... so if Synplify is the selected synthesis tool, a Synplify .prj file is created. When creating that .prj file, 7.1 leaves out any files that are identified as libraries in ISE, causing Synplify to immediately error out. And as if that isn't enough, ISE *obviously* knows best and refuses to run if you manually fix the Synplify .prj file (ISE complains that the Synplify .prj file was edited manually and errors out). It all worked correctly in 6.3. And yes, the week that 7.1.0i came out, we told our FAE about these problems (along with numerous other issues). MarcArticle: 82802
ALuPin wrote:
> I want to sample 16MHz data with a 125MHz clock.
> Is there some tricky method to perform this kind of oversampling ?
There's a simple one if you have both clocks.
Write a synchronous process using 125MHz
as the clock and 16MHz as an input named "rate"
Synchronize "rate" and use it to generate a
rate_rising clock enable pulse.
-- Mike Treseler
Article: 82803I've posted a question to the newsgroup a few days ago about some Virtex2 DCI problem I have, the post seems to have disapeared! It was there for a day or so... I don't know why, this was my first post from Gmail, it there something I'm missing? Who can remove post from the newsgroup? --- jakabArticle: 82804
Spam avoidance is a good idea, but it does not require anonymity. You cn obfuscate your return address, but still reveal your identity to us humans. PeterArticle: 82805
jakab.tanko@gmail.com wrote: > I've posted a question to the newsgroup a few > days ago about some Virtex2 DCI problem I have, > the post seems to have disapeared! It was there > for a day or so... > I don't know why, this was my first post from Gmail, > it there something I'm missing? Who can remove post > from the newsgroup? Well, I still can see it... as well as Austin's response. :) cu, SeanArticle: 82806
> It's just too easy to start a rumor which then "blossoms" into a > 50-post thread. Especially when messages get posted 4 times ;) Cheers, JonArticle: 82807
Somebody published nice tutorial on FPGAs. Describes architecture, logic blocks and routing in common FPGAs. http://www.tutorial-reports.com/computer-science/fpga/index.php best wishes GauravArticle: 82808
Hi, Yeah if any body has any idea of how this thing can be done please share your views.I am stuck at this point and cannot proceed till i solve this problem of getting data into microblaze from outside(say using UART). Thanx. Herb T wrote: > Dan Henry wrote: > > kittyawake@gmail.com wrote: > > Hi Dan, > Can you give us some more specific details how to do it (or anyone that > knows ;-)? It would be a great help. > Thanks, > -HTArticle: 82809
"Older Posts", "next page" also "show options" "find messages by this author"Article: 82810
"Preben Holm" <64bitNOnoSPAMno@mailme.dk> wrote in message news:4262a53f$0$79456$14726298@news.sunsite.dk... > >>Hi, > >> > >>I have an A/D-converter attached to my Spartan3 starter kit, running at > >>100Mhz Maximum speed. > >> > >>But the A/D converter only has valid data 7 ns after the rising clock > >>edge and until 2ns after the next rising clock edge? > >>Where should I sample running a low-frequent sampling of fx. 10 MHz? > >> > > > > Preben, > > The IOBs have an optional delay element. RTM. If you use this with the IOB > > input flip-flop, you eliminate pad-to-pad hold time. > > Cheers, Syms. > > Pretty confused now... > > Pad-to-pad delay is the delay between the two IC's Is this correct? Incorrect. In your case, pad to pad delay is the delay from the clock arriving at the FPGA input pad, to the clock input of the IOB FF in the data input IOB, plus the hold time of the FF. This delay must be less than the time from the clock transition to the data transition. The optional IOB input delay in the data IOB delays the data transition, so you have more time to get the clock to the data IOB's FF. Is that any help? Cheers, Syms.Article: 82811
Pretty sure you only need to decouple the rocket I/Os you're using. You could email Ed McGettigan to find out the official Xilinx line, his email address is in his posts here. I believe he knows about the ML board too. Best, Syms. "jean-francois hasson" <jfhasson@club-internet.fr> wrote in message news:42616ac7$0$15282$7a628cd7@news.club-internet.fr... > Hi, > > I work on a project involving the rocketios. I have read the user guide > and among other things notcied the decoupling advised : a very big > capcitor at the output of the LDO (330 uF) and several smaller ones (1 > uF). The user guide advises eight 1 uF. Are that many capacitors > necessary especially when not all the rocketios (2 for instance in my > case) are used ? Moreover I looked at the ML300 board design and I did > not see these 1 uF capacitors so what is the right move here ? Any advice ? > > Thanks, > > JFArticle: 82812
"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:ft8761tdcb22fop7o910lkc8l5qlirhueg@4ax.com... > If you don't have access to the original 16MHz clock, you can > either try to recover it by locking a digital PLL on to the > data transitions (7x oversampling is *just* about enough > to be able to do this easily) It's easy enough with just 4 times oversampling. XAPP224 shows how to do it at 400Mb+ data rates. Cheers, Syms.Article: 82813
Hello, I have an idea for a design of a data aquisition system and i am willing to verify the possibility to implement it. Basically it's an ADC connected to the TS201 that sends the entire information sampled to a PC through one of it's LVDS connectors. On the PC there is a PCI Card that knows how to do LVDS for example the PCI GP-ECL/SSD16. of the EDT group. Before checking all the cards availbe i would like to ask: 1.Did someone do the LVDS connection betwenn the TS201 and PC? 2.Do i need to do something special when connecteing the TS to the PC board? (someone told me that there are special cables for it and the connection is not Trivial). Thanks in adcance, Marc.Article: 82814
jean-francois hasson wrote: > I work on a project involving the rocketios. I have read the user guide > and among other things notcied the decoupling advised : a very big > capcitor at the output of the LDO (330 uF) and several smaller ones (1 > uF). The user guide advises eight 1 uF. Are that many capacitors > necessary especially when not all the rocketios (2 for instance in my > case) are used ? Moreover I looked at the ML300 board design and I did > not see these 1 uF capacitors so what is the right move here ? Any advice ? We did a rewrite of this section in the user guide (page 110) to clarify this, but when I reviewed it again today it's still not clear. What it should state is 1.0 uF for every 2 MGTs that are used and these should be placed near the ferrite beads, which should be placed near the FPGA. If you are looking for an example of how Xilinx created a board that uses the RocketIO, the ML300 is not a good choice as this was done very early and is missing some of the final design recommendations. The ML310, ML321, ML323 and ML325 are better examples in this area http://www.xilinx.com/ml310 http://www.xilinx.com/ml321 EdArticle: 82815
In article <d3vt99$iia$1@lnx107.hrz.tu-darmstadt.de>, Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: >Phil Tomson <ptkwt@aracnet.com> wrote: > >> I think I'm about to try running the Win32 version under Wine - pretty >> sad that their Linux version is so crappy. You'd think they'd have better >> understanding of the Linux platform than this > >If you run with a 2.6 Kernel, you must do as root > >echo 1 >/proc/sys/vm/legacy_va_layout > >Linux Memeory layout was changed in 2.6 , now pointers to memory between >0x80000000 and 0xBFFFFFFF can escape to the windows programm and ISE >stumbles about some signed/unsigned problem I guess. Also the Output windows >now uses more RichEdit functionality that is not yet implemented in the Wine >builtin Richedit implementation. Use native RicheEdit so long. > >> - maybe Xilinx should hire some of us? ;-) > >They should talk to Codeweavers. I guess for the money Xilinx spends on WindU, >they could have Codeweavers weed out a lot of Problems in Wine (and perhaps >some in the Xilinx code) so that ISE would run flawless in Wine. No more >need for a WindU license and a single source tree... > >> Hopefully ... > Isn't it interesting how fast some Xilinx guys (FAEs?) jumped on the other thread about Spartan 3E being slower than Spartan 3, but we've heard nary a peep out of them about this thread? PhilArticle: 82816
I just got my first job offer with a semiconductor company. I am yet to sign the paperwork. I am hoping to get more offers in the forthcoming month. I am wondering if the paperwork that I sign for this company can be used against me if I turn down the position for a different one, say in a month? Is the paperwork legal and binding? My start date is not until July 1st. Thanks in advance for your inputs.Article: 82817
Hallo, I should connect the wishbone can core with opb bus. I have downloaded from asics.ws the wrapper. There is someone who could explain how to use it? I have also made some search for a tutorial or documentation, but I don't have found nothing. Where I could find the documentation? Many Thans MarcoArticle: 82818
In article <1113845249.689554.28780@g14g2000cwa.googlegroups.com>, <shuss3@yahoo.com> wrote: >I just got my first job offer with a semiconductor company. I am yet to >sign the paperwork. I am hoping to get more offers in the forthcoming >month. I am wondering if the paperwork that I sign for this company can >be used against me if I turn down the position for a different one, say >in a month? Is the paperwork legal and binding? My start date is not >until July 1st. Thanks in advance for your inputs. > Maybe I'm misunderstanding, but you say that you have not signed anything. If that's the case you're fine. Then you say that you might sign the paperwork thus accepting said semiconductor company's offer. Then you imply that you might (after signing and accepting the offer of company #1) turn down the offer if a juicier offer comes before your start date. There are two issues here: legal and ethical. Legally, you'll be OK because you will have declined the offer even after you've signed an acceptance letter. It would be just as if you were an employee for years with the company and you decide to quit, your employee agreement will be terminated. The difference being that you will not be privy to any company confidential info since you will not even have started working there yet. Ethically what you're doing (or planning to do) is rather shakey IMHO. If you're going to sign the acceptance letter that means you intend to accept their offer and by all means you should keep your word and start working for them. If, after a couple of years you decide that you want to seek employment elsewhere (perhaps sooner if you find that the job wasn't as represented OR if you find something bad like illegal activity, etc. going on). Why a couple of years? Well if things aren't completely terrible there you should try to stick around for at least 2 years because you don't want to be seen by future employers as someone who moves around a lot. If you think you'll be getting better offers in next couple of months you should decline to sign the offer letter but try to keep your options open with the first company - be honest and let them know that you want to evaluate some other offers before you commit. Since your start date wouldn't be until July 1 they would probably be flexible if they really want you. However, given that things still aren't that great in the industry right now, I would consider myself lucky that I got one offer - don't burn your bridges with this first company, you might need a job from them in the future. Mr. Manners...errr.. PhilArticle: 82819
Just got my new Xilinx platform usb download cable. $149. Works great, even with 6.3.03, very fast. No longer will I need to position my laptop near a desktop to get PS2 power for my parallel download cable! Inside, there's a Cypress EZ-USB CY7C68013 and a Coolrunner XC2C256, with a unfitted 14 way connector probably to download to it! Best, Syms.Article: 82820
Hi, I am having a problem installing Xilinx ISE 7.1. It completed 99% and then it says "The following error was encountered during installation: 2 : An error was detected in the archive. Press retry to try again, otherwise press cancel to exit the installation." It was under an administrator, so I don't know what the problem is. I had version 6.1 before I tried to install 7.1. Has anyone run into this problem before? And how do you fix this? Thanks, AnnArticle: 82821
Phil Tomson <ptkwt@aracnet.com> wrote: > Isn't it interesting how fast some Xilinx guys (FAEs?) jumped on the > other thread about Spartan 3E being slower than Spartan 3, but we've > heard nary a peep out of them about this thread? No theory of conspiration, please, Those guys (always helpfull and responsive) come from different areas then the guys responsible for programming... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 82822
> I think I can wrap my head around the concept of the LUT allright, but > the problem I'm having is that I can't find where in the Xilinx WebPack > software I get to determine the contents of the LUT. If your question means "where can I set the INIT values", you can do this in your source code either as a generic on the LUT or an attribute on the LUT. If you meant "how can I check the INIT value assigned", this can be done with FPGA Editor (not available with Webpack), which will show you the logic equation associated with each LUT.Article: 82823
Symon wrote: > "Preben Holm" <64bitNOnoSPAMno@mailme.dk> wrote in message > news:4262a53f$0$79456$14726298@news.sunsite.dk... > >>>>Hi, >>>> >>>>I have an A/D-converter attached to my Spartan3 starter kit, running at >>>>100Mhz Maximum speed. >>>> >>>>But the A/D converter only has valid data 7 ns after the rising clock >>>>edge and until 2ns after the next rising clock edge? >>>>Where should I sample running a low-frequent sampling of fx. 10 MHz? >>>> >>> >>>Preben, >>>The IOBs have an optional delay element. RTM. If you use this with the > > IOB > >>>input flip-flop, you eliminate pad-to-pad hold time. >>>Cheers, Syms. >> >>Pretty confused now... >> >>Pad-to-pad delay is the delay between the two IC's Is this correct? > > Incorrect. In your case, pad to pad delay is the delay from the clock > arriving at the FPGA input pad, to the clock input of the IOB FF in the data > input IOB, plus the hold time of the FF. This delay must be less than the > time from the clock transition to the data transition. The optional IOB > input delay in the data IOB delays the data transition, so you have more > time to get the clock to the data IOB's FF. > Is that any help? > Cheers, Syms. Well, actually no!! But I don't get the idea about what the Input FF can do for me at all - so let's forget about that in the first time. Is the delay element any good when not using the input FF. What clock arriving at the FPGA input pad - some special input clock or the overall system clock? The delay element makes my signal settle approx. 4 ns later which means 1 ns ((7+4) mod 10 = 1) after the rising edge of the clock - that's where I don't understand it anymore?Article: 82824
My earlier answer is probably easier to understand if you're looking at figure 1 in the ds099-2.pdf (Spartan-3 FPGA Functional Description)
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z