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> Synplify DSP does indeed support multi-rate systems. It utilizes the > sample rate capabilities that are native in the Simulink environment > from The MathWorks. Synplify DSP fully understands all of a users > sample rate designations, and will > exploit this information to create an optimal implementation. > > All the designer needs to do is specify the sample rate on the design > inputs. This can be done explicitly, or inherited from the signals that > drive the system. Sample rates are then propagated automatically > through all blocks, changing when requested through an upsample or > downsample instance. All sample rates domains are derived automatically > from this infrastructure, and Synplify DSP infers the required > interface between sample domains during hardware implementation. > It may even create a multi-rate system from a single-rate specification > in order to achieve this most efficient hardware implementation. The > goals is to ease the specification process through automation, and > relieve the designer from the tedious tasks of system level clock > definition and interface specification in a multi-rate design. Hi Andrew, Thanks for your answer. However, I am aware of Synplify DSP's DSP Synthesis capabilities when it comes to inferring efficient structures in multi-rate systems where each sampling domain is an *integer ratio* of the others. What is not clear from your answer is whether or not Synplify DSP supports multiple *clock* domains where the tools must infer suitable hardware to transfer data reliably from one clock domain to another, unrelated, asynchronous clock domain. Sorry if this seems pedantic but mutiple sampling rate domains that are integer ratios of one another are a very different design prospect to multiple, unrelated clock domains. Cheers, DaveArticle: 83051
Hi Klaus... Ok... this was something i was not knowing about. I thought there might be just some way that i may not be knowing about. Thanx for the answer. But i feel in VHDL 200X, i.e. the next version coming up, in that i think they r planning to include these things also. regards, puneetArticle: 83052
Hi Philip,
As per ur suggestion, i tried out something different and also
mixing outputs by ORing them together has helped to some extent. Now i
am giving final touches to the design, hope it works. The basic module
is working fine. Thanx for the answers.
regards,
puneet
Article: 83053"Klaus Falser" <kfalser@durst.it> schrieb im Newsbeitrag news:MPG.1cd2c4468eb269c5989687@news.inet.it... > In article <4267a83b$1@e-post.inode.at>, nospam@nospam.com says... > > Hi there, > > > > I created a CPLD design which works perfect in simulation, but does not work > > in hardware. There are many warnings from the Xilinx ISE looking like > > > > WARNING:Xst:1291 - FF/Latch <Sig> is unconnected in block <Blck>. > > > > or > > > > WARNING:Xst:1710 - FF/Latch <Sig> (without init value) is constant in block > > <Blck>. > > > > These come up only in the Low Level Synthesis processing step. There is one > > relevant solution record on the Xilinx website (see > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18396) > > with the following suggestion: > > > > >> When this warning occurs, a register or latch in your design has been > > created, but the output is never connected or the signals or logic it drives > > have been trimmed. Check the XST log for messages such as the following to > > find signals that have been trimmed out of the design: > > > > "WARNING:Xst:646 - Signal <my_sig> is assigned but never used." << > > > > However, there are no such warnings in my XST log. > > > > Any help would be appreciated. > > > > Christian > > > > > > > > If working with ISE/Webpack 7.1, did you apply the the patch 21168? > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= > 1&getPagePath=21168 > > Best regards > Klaus Thanks for your advice, I installed the newest ISE (7.1), service pack 1 and the patch. Now these strange warnings are gone. Best regards ChristianArticle: 83054
Erik Walthinsen wrote: > Symon wrote: > >> Does the Platform USB cable help? $149 ;-( >> http://www.xilinx.com/bvdocs/ipcenter/product_brief/usb_cable_overview.pdf >> > > > Holy cow. > > Exact same price as the "coming soon" Spartan 3E starter kit, which also > has an FPGA (xc3s500e), 32MB of DDR SDRAM, flash, Ethernet PHY, USB 2.0 > (Cypress EZ-USB FX2 I hope), etc. I'm assuming it will come with Impact > drivers to use the FX2 to drive the JTAG chain, and/or use serial slave > mode, and hopefully an appnote on writing your own download sequence > into your FX2 firmware. Then again the Xilinx page lists the good old > parallel JTAG cable as coming with it. Just as long as they hook up > enough pins to let the USB controller config the FPGA, I'll be happy. Erik, where are the links for this starter kit please.Article: 83055
Symon wrote: > Does the Platform USB cable help? $149 ;-( > http://www.xilinx.com/bvdocs/ipcenter/product_brief/usb_cable_overview.pdf I thought it did not work on Linux, specially on my non supported FC3 platform .... rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 83056
Hello,
i am using an Xilinks Spartan 3 XC3S200 FPGA. What i am trying
to do is write to the Ram on this board (256K by 16 - two of).
I have declared my memory as [17:0], an 18 bit value which represents
the RAM addresses on the FPGA ram (A0 - A17). When i try read the
values out from the RAM, eg. Ao, it only reads out 1 bit, instead of 8
bits. I have set the lower byte on and the upper byte off, but i dont
think it is anything to do with this.
Do i have to declare my memory something like this?
reg [7:0] memory [17:0];
So it has an 8 bit width and 18 bit memory addresses. When i try and
do this the XIlinks ISE 6, gives me error mesages.
Any ideas ????? thnanks
Article: 83057
you don't need special buffering, but don't forget to add the PROM into
the chain, if you don't solder the prom due to time constraints make
sure you close the chain (TDO-TDI at the prom pins) with a jumper.
Aurash
aosik5@gmail.com wrote:
>I'm currently laying out a PCB containing a Spartan II-E (XC2S200E
>PQ208). I'm laying out the circuitry for an SPROM chip to store my bit
>file, but due to time constraints I would like to be able to program
>the chip using the JTAG interface (similiar to the one on the
>development board I am using, a Digilent development board from
>NuHorizons) in case, due to time constraints, I am unable to program
>the SPROM before a presentation.
>
>I'm familiar with the way the JTAG cable works but am a little confused
>as to how the four pins (TMS TDI TDO TCK) interact with the FPGA.
>Based on my knowledge, I am assuming that the four pins are wired one
>to one with the corresponding FPGA input pins (and one output). The
>board I'm using has a parallel port to JTAG interface which makes
>tracing the port routes confusing. I really only have one or at most
>two shots at the PCB so I was just wondering if the JTAG pins can be
>wired directly to the FPGA, no buffer chip or anything in their way.
>
>Thanks!
>
>George
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 83058CODE_IS_BAD wrote: > Hi all... > After i synthesize my code i get the following timing reports in my > synthesis report file. > > Minimum period: 11.536ns (Maximum Frequency: 86.685MHz) > Minimum input arrival time before clock: 22.952ns > Maximum output required time before clock: 7.829ns > Maximum combinational path delay: No path found > > Now it says maximum frequency as 86.685 MHz. > But at the same time the minimum i/p arrival time before clock is > 22.952 ns. So in this case what will be my maximum clock frequency of > operation ? > Also can anyone explain the significance of all the tree timing > parameters listed above. That will b of some help to me. Thanx a lot. > puneet First of all realize that the synthesis timing report is just an estimate of final timing and may be significantly different than the post place-and-route results. Minimum period only looks at paths that start at a flip-flop and end at another flip-flop. Thus it won't include for example timing from an external input to the first clocked component. In this case it says that from one rising clock edge to the following rising edge some signal will leave a flip-flop in your design and just meet the destination flip-flop's setup timing requirement in 11.536ns. Actually I can only guess at this. If your design uses both edges of the clock, the minimum period may be computed from a path that goes from one clock edge to the other, based on a 50% duty cycle clock. This sort of path will be much easier to determine in the back-end timing reports. Minimum input arrival time before clock is your input setup time. Since it is longer than the reported period it may indicate that the design won't run at 86.685 MHz, but this depends on how you sample your inputs (specifically those causing the longest input path delays). If you don't get a new sample on every clock or if the maximum time path is your reset signal, your design might still run at 86.685 MHz. Maximum output required time before clock would be your output clock to Q timing. This indicates that an external device can assume outputs valid by waiting 7.829ns after the clock edge before sampling the signal. Maximum combinational path delay is only for paths that start at an input to the design and go to an output of the design without being clocked along the way. Input and output timings are especially dubious in the synthesis-level timing report. It's hard to imagine that the synthesizer can report these numbers before knowing whether the mapper will force flip-flops into the IOB's (other than instantiated components). These timing reports are mostly to give you an idea whether you're in the right ballpark to meet your timing requirements, so for example I wouldn't try to run this design at 120 MHz.Article: 83059
Hello I am using a Virtex2Pro board and lately I was trying to use the PowerPC at the highest speed (300MHz) on my board. I have a function which uses a lot of floating point instructions for calculating the log, sine, cosine and such stuff. When I ran this program on the PowerPC it took almost 2 minutes to perform 1000 iterations at 100MHz. Then we wanted the code to run a little more faster and so we implemented the same design at 300MHz. Even if we didn't expect a three fold increase in speed, there was only an improvement of a couple of seconds. Can somebody tell me the reason. Well about the memory that I was using, I used a OCM interface with 32kB for Instruction and 8kB for data. Cache memory was given to the PLB RAM(16kB). There was infact no speed difference with and without the cache memories !! Can somebody please help. When I selected 300MHz for the processor, the maximum bus freq that I could select was only 100MHz. But this is only for the PLB or is it also for the OCM interface. (I always uses the wizard to build a new system, as I am quite new to tis stuff) Thank you very much JoeyArticle: 83060
Hi, I can't seem to find any documentation on Virtex-4 routing, no even a general schematic, i looked at the datasheets and user guides but nothing. I saw a answer record that said that there weren't any TBUF's, and the data sheet shows that there is a switch matrix similar to Virtex-II in the CLB's. Does anyone have more information about it? is it similar to Virtex-II? When does Xilinx plan to release this information? Those who have ISE 7.1 can see FPGA Editor is there considerable differences? Thanks MiguelArticle: 83061
Hi Gabor, That was really wonderful piece of information and also explained quite nicely. Actually after map i got a speed of 123 MHz and after place n route it came to 79.001 MHz. Once again thank you very much. PUNEETArticle: 83062
Hello all, I would like to know whether an interface like an OCM interface is possible at all for the SDRAM !!! Thank youArticle: 83063
Miguel, It is virtually identical to Virtex II, II Pro. The main differences are the additional global clocks, and the regional clocks. In terms of the local interconnect, we still have horizontal and vertical longs; the hexes, doubles, singles and directs like we do in V II. Austin Miguel wrote:Article: 83064
Probably not. What parts are you using? BCD Joey wrote: > Hello all, > > I would like to know whether an interface like an OCM interface is possible > at all for the SDRAM !!! > > Thank youArticle: 83065
Uwe Bonnes wrote:
> Trond Egil Gran <nospam@for.me> wrote:
>
>>Have anyone got Impact working in Fedora Core 3? Or any similar Linux?
>
>
>>I have tried this:
>
>
>>http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm
>
>
>>but I probably get 1000 compile errors.
>
>
>>Is there any other possibilities for programming xilinx FPGA's?
>>I have read about NAXJP but can't find any places to download it,
>>I have tried http://www.nahitech.com/nahitafu/naxjp/naxjp-j.html#down
>>but can't find any links to click on to download it. I'm using a spartan
>>2E at the moment.
>
>
> Try
> http://www.rogerstech.force9.co.uk/xc3sprog/
>
> XC2S should work too.
>
No that did not work, it does read IDCODES form the system and does
have some XC2S devices in it's device list but it seems as the program
does not suppurt them. As can be seen from these lines in the source
code:
if(strncmp("XC3S",dd,4)==0) programXC3S(jtag,io,file);
else if(strncmp("XCF",dd,3)==0) programXCF(jtag,io,file);
else{
fprintf(stderr,"Sorry, cannot program '%s', a later release may be
able to.\n",dd);
return;
}
TEG
>
>
>>Why don't just Xilinx program against the parallelport in user-space
>>(ppdev) Instead of having two drivers??
>
>
> Or if Xilinx would publish an interface to adapt one's own Jtag interfaces...
>
Article: 83066
Acceed See wrote:
> I am performing a huge simulation, netlist and SDF file size were each
> ~110MB. The first segment of my simulation were correct, then all of a
> sudden some of my signals became question marks. On the simvision,
> they appear to have been blank after certain time, and cursor value turned
> question mark.
>
> Is this caused by memory depletion or what?
>
> Thank you for your input.
I've noticed the same thing happening when a simulation ends.
When Simvision is connected to the sim, it apparently uses the network
to get information -- when the sim ends, it has to switch to using the
file. I've had to shut down Simvision, then restart it, to get the
correct values back.
Article: 83067Hi BCD, I didn't really understand what you meant with what parts I am using. I am trying to implement a C program which is a little big. I tried it with the local BRAMs and now I want to know whether I can really route the signals out of the FPGA chip and to the peripherals on the board. I just wanted to make the onboard SDRAM as the place for my program !! So the plan is, to fetch the program from the SDRAM interface. Somehow I cannot increase the Bus frequency more than 100MHz. But the SDRAM might work faster and thats why I am trying to do this. Thank you Joey <pilot172@gmail.com> schrieb im Newsbeitrag news:1114181921.329786.190300@g14g2000cwa.googlegroups.com... > > Probably not. What parts are you using? > > BCD > > Joey wrote: > > Hello all, > > > > I would like to know whether an interface like an OCM interface is > possible > > at all for the SDRAM !!! > > > > Thank you >Article: 83068
Ahh I actually got it working, I just added:
else if(strncmp("XC2S",dd,4)==0) programXC3S(jtag,io,file);
after the line:
if(strncmp("XC3S",dd,4)==0) programXC3S(jtag,io,file);
And now it seems to work. I also added the device ID for my
XC2S100E and 18V01 to the the devlist.txt file.
Thanks for the tip about this program!
This is good now I just need one OS and one computer and no WMvare.
TEG
Trond Egil Gran wrote:
> Uwe Bonnes wrote:
>
>> Trond Egil Gran <nospam@for.me> wrote:
>>
>>> Have anyone got Impact working in Fedora Core 3? Or any similar Linux?
>>
>>
>>
>>> I have tried this:
>>
>>
>>
>>> http://www.fpga-faq.org/FAQ_Pages/0044_Xilinx_Parallel_on_Linux.htm
>>
>>
>>
>>> but I probably get 1000 compile errors.
>>
>>
>>
>>> Is there any other possibilities for programming xilinx FPGA's?
>>> I have read about NAXJP but can't find any places to download it,
>>> I have tried http://www.nahitech.com/nahitafu/naxjp/naxjp-j.html#down
>>> but can't find any links to click on to download it. I'm using a spartan
>>> 2E at the moment.
>>
>>
>>
>> Try
>> http://www.rogerstech.force9.co.uk/xc3sprog/
>>
>> XC2S should work too.
>>
>
> No that did not work, it does read IDCODES form the system and does
> have some XC2S devices in it's device list but it seems as the program
> does not suppurt them. As can be seen from these lines in the source
> code:
>
> if(strncmp("XC3S",dd,4)==0) programXC3S(jtag,io,file);
> else if(strncmp("XCF",dd,3)==0) programXCF(jtag,io,file);
> else{
> fprintf(stderr,"Sorry, cannot program '%s', a later release may be
> able to.\n",dd);
> return;
> }
>
>
>
> TEG
>
>>
>>
>>> Why don't just Xilinx program against the parallelport in user-space
>>> (ppdev) Instead of having two drivers??
>>
>>
>>
>> Or if Xilinx would publish an interface to adapt one's own Jtag
>> interfaces...
>>
Article: 83069The EP2C5 and EP2C8 devices will be available in the July timeframe. The EP2C20 in the F256 package is vertically migratable (same pinout) to both the EP2C5 and EP2C8. The EP2C20 will be available in the beginning of June. BTW, we do publish the availability dates for our devices our our website. Here is the URL: http://www.altera.com/products/devices/cyclone2/overview/cy2-overview.htmlArticle: 83070
Kind of like the battle of (pick any one you are familiar with). Both armies on top of their respective hills can see the other side perfectly well, but got other business to attend to first. regardsArticle: 83071
"austin" <austin@xilinx.com> wrote in message news:d3sfdk$15g1@cliff.xsj.xilinx.com... > All, > > The micro-machanical structures are huge. They are hundreds, if not tens > of thousands of times bigger than the transistors used in the FPGA fabric. > > Austin One of the reasons of a lot of research into photonic crystals as a replacement for mems(micro electro mechanical) devices. Supposed to be the next step towards optical processors as well as replacement for current optic fibre materials / do away with non optical amplifiers in present optical fibre systems http://ab-initio.mit.edu/photons/Article: 83072
I need to buy a new PC. What is the best processor for saving time during synthesis projects? AMD Athlon 64 Intel XEON Intel Pentium 4 ?? Thanks MarcoArticle: 83073
Joey, I asked about the parts because the OCM interface changed from V2Pro to V4. If you're using V2Pro, you can't do it. If you're using V4, you probably still can't do it, but I can't say for sure...although I'm sure someone else can tell you with certainty. Regardless of which parts you're using, I think you're best bet is to put the SDRAM off the PLB bus. BCDArticle: 83074
Acceed See wrote: > "Acceed See" <invalicd@hotmail.com> wrote in message > news:4264e0ae$1@news.starhub.net.sg... > >>My LA is agilent 16702. When I use the 400MHz internal clock to sample >>the clock pin and the data pin with probes, I can see them nicely on the > > LA, > >>and positive edge of the clock is right in the middle of the data. When I >>change >>to sampling data with my external clock pin, LA told me the clock is too >>weak >>and can not see a clock in the top-right banner. Of course, I don't see > > any > >>data. >> >>What is the cause of that? How can I correct this? >> > > > > Any quick fix for those "It worked in simulation, but not in FPGA" > nightmares? > My design is 200K ASIC gates burned in an FPGA, it's so tiring to debug > that. What is the clock source? Is id overloaded or short on settling time? Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻ
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z