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I am using Virtex2pro - xc2vp30 to implement my HDL-based design. The output of my design will be stored in BlockRAM. How can I read my output from BlockRAM (BRAM)? Do I need to access BRAM using PowerPC? If so, how can I connect this BRAM with the PowerPC bus? I am a beginner of FPGA implementation. So, your advice will greatly help me.Article: 81726
Benjamin, http://www.xilinx.com/prs_rls/ip/04122milcom.htm and Google JTRS SDR Xilinx You will get ~ 1900 hits. We are part of every JTRS SDR experiment, program, verification, project, etc. Especially due to our extremely low power, we are even being used for handie-talkies ..... The ability to reconfigure live (take out waveform A, insert waveform B), as well as use the 405PPC (the lowest power 32 bit integrated uP in 90nm) allow for identification of the waveform required, reconfiguration, and then opening the channel for tx and rx, as well as shutting it down, and returning to "wait for somebody calling me" again. Austin Benjamin Menküc wrote: > Hi, > > I am generally interested in SDR with FPGA. Does anybody know some nice > projects or where to find good information about it? > Any experiences would be appreciated too. > > Maybe there is somebody involved with the SCA/JTRS (joint tactical radio > system) here in the Newsgroup :) > > regards, > BenjaminArticle: 81727
Hi, ALL! Several months ago I did schematic based design, implementing median image filtering in Altera EP1K30TC144-2. It was running something close to 150MHz without any explicit constraints, except target clock frequency. At that time I did not need that much speed, because my device was providing me data only 60MHz or below. Now we are busy with another device, capable to run at 150MHz and we have XC2VP4 speed grade 6 Xilinx FPGA as a data processing unit within the device. I rewrote design using VHDL language. During verification, RTL schematic of synthesized VHDL code was looking exact like schematic for Altera ACEX-1k device. The only issue was speed. VHDL reincarnation of median filter was running only 134+MHz. Flor-plan editor was showing half of the chip polluted with registers and multiplexers of the design. I tried to set some constraints on VHDL code to reduce area where this block located. I spent about 6 hours playing with various placement/timing/routing attributes and constraints but failed to get any better. So, is there any guide about constraints strategy? I read the guide about constraints, but there are too many choices. I managed to remove couple setup errors by explicit placing combinatorial logic and registers in adjacent slices, but it would be horrible idea to do manual chip routing :( With best regards, Vladimir S. MirgorodskyArticle: 81728
Arul schrieb: > I am using Virtex2pro - xc2vp30 to implement my HDL-based design. The > output of my design will be stored in BlockRAM. How can I read my > output from BlockRAM (BRAM)? Do I need to access BRAM using PowerPC? > If so, how can I connect this BRAM with the PowerPC bus? I am a > beginner of FPGA implementation. So, your advice will greatly help me. Using BRAM is quite easy. Take a look at the XST documentation, chapter 2: "HDL Coding Techniques". There you find many examples how to describe your design so that the synthesis will use the features of the FPGA. You don't need the PowerPC to access the BRAMs. Matthias AllesArticle: 81729
Hello. I am writing VHDL code to be synthesized on a Xilinx Spartan II FPGA. For the past month, I've been beating my head against one problem with synthesizing the latest version of my code. I am using the Xilinx Webpack IDE V7.1.01i available for free from <http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack>. Synthesis usually takes about a minute with my previous code versions. When I added a few lines about a buffer and references to that buffer, and try to synthesize, the synthesis goes to 66% of completion normally, but then stays there for about 15 minutes before spitting out an out of memory error: ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 1954536 kb. Memory problems may require a simple increase in available system memory, or possibly a fix to the software or a special workaround. To troubleshoot or remedy the problem, first: Try increasing your system's RAM. Alternatively, you may try increasing your system's virtual memory or swap space. If this does not fix the problem, please try the following: Search the Answers Database at support.xilinx.com to locate information on this error message. If neither of the above resources produces an available solution, please use Web Support to open a case with Xilinx Technical Support off of support.xilinx.com. As it is likely that this may be an unforeseen problem, please be prepared to submit relevant design files if necessary. ERROR: XST failed Process "Synthesize" did not complete. I have stripped my program down to the simplest version that still exhibits the problem: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity frameCapture is port ( clk :in std_logic; lineBuffer : out std_logic_vector(1780 downto 0); --will buffer most significant 5 bits of each pixel on even lines. UV: in std_logic_vector(7 downto 0)); --Digital output from camera. UV bus. end frameCapture; architecture reg_transfer of frameCapture is signal bufPosOne, bufPosTwo, bufPosThree : integer range 0 to 1785; --are five more than they needs to be to prevent negative numbers. signal colCount : integer range 5 to 25 :=5; -- I picked these values in this example so that bufPosTwo and bufPosOne are obviously -- between 0 and 1785. begin bufPosTwo<= colCount*5+4; bufPosOne<= colCount*5+0; process (clk) begin if clk'event and clk = '1' then if colCount<= 25 then colCount <= colCount + 1; else colCount <= 5; end if; LineBuffer(bufPosTwo downto bufPosOne) <=UV (7 downto 3); end if; end process; end reg_transfer; ------- I have been trying to troubleshoot this problem for the past month, and have a deadline soon aproaching, so I am in desperate need of help. Is my bit of code doing anything illegal? Can you see any reason why my code should make the ISE work so hard it runs out of memory? From my experimentation, the problem does not have to do with colCount, but the indexing of LineBuffer with bufPosTwo and bufPosOne. Thanks for any help you can provide. It will be greatly appreciated! Sincerely, Andrew DoucetteArticle: 81730
I just got my copy of ISE 7.1 and noticed that I now have to click through both the GPL and the LGPL before installing... I don't remember having to do this before -- does anyone know what changed or was added? ...EricArticle: 81731
WP, Oleda tech has the tool that you are looking for. www.oledatech.com Our online tools will read your PAD output or UCF file and generate a HTML based graphical representation of your footprint. Pins with signal assignments are highlighted, plus you can point to a pin and see the signal assignment. It also lets you highlight groups of pins such as busses or pins with a common IO standard, or all the signals that begin with PCI, etc. You can save a 'live' copy on your computer or print out views of your choosing. You can contact me through the website, I'd be glad to set you up with a trial license. It will save you a great deal of time! JohnArticle: 81732
Some of the xilinx fpga pins are wired to leds. P39 for instance is wired in such a way. In my design I have a vhdl counter and want to direct ISE (v.6.3i) to tie the output of the counter to P39. What is the way to do this? It seems that PACE does this, but then Floorplanner and FPGA Editor seem to do something similar to this as well. When I tried to use PACE, I saw I could specify the Loc as "BANK6", but could not figure out how to directly assign to the pin #. In Floorplanner I could select File->Read Constraints..., but wasn't sure this would do what I wanted either. In Xilinx ECS I could create a schematic that wires together the vhdl counter. It occurs to me that this is also a possible place to assign the output to P39. Is that true? Thanks, -beagleArticle: 81733
On 30 Mar 2005 06:29:36 -0800, "lecroy7200@chek.com" <lecroy7200@chek.com> wrote: >> Well, I have read all of your posts, and everyone elses too. >> The problem is one of clarity of communications. > >Good that you know that everyone read them all. I for sure could not >make that statement. Well, this is still a clarity issue. I wrote "elses" but should have probably written "else's", as in "I have read the articles by everybody else". You read "elses" and assumed I meant "else has" which is a contraction I have never heard of :-) Philip Philip Freidin FliptronicsArticle: 81734
I imagine that the computer is synthesising a hugely complicated multiplexer out of logic gates for the frame buffer, rather than inferring that it ought to use a BRAM. I could certainly understand a design compiler running out of memory implementing a 2kbit random-access memory. Would explicitly instantiating a BRAM help? TomArticle: 81735
Hi, We've designed many PIDs. No specific difficulty. Be cautious with the derivative part however. Estimating the derivative is much trickier than it may seem !!! And be careful if you want to insert digital filters in the loop (but it's all taught in the DSP courses). It's fun to see this "prehistoric" regulator working. Afaik, it's still used in some modern designs for PLL control. We used it many time to control actuators with feedback. (In fact, one PID design has just gone through all tests successfully) Make sure you implement an easy way to adjust PID coefficients on the fly in real time (we used RS232, and also JTag with ISMCE for this purpose). If you want a board ideal for this kind of experiment, try our Tornado board ! Everything is on the obard, from ADC input to power outputs and/or RC servo control. See http://www.alse-fr.com/Tornado/Torn_Educ_us.pdf Umair Siddiqui wrote: > Hi.... I am a student of MS Systems Engineering, I have been assigned a project titled as "FPGA Based Field Controller(PID)". Currently I am in a study phase, I would be thankful if some of you send me some literature or papers that describes that how PID controllers can be implemented on FPGA. Looking for your positive response.....Umair SiddiquiArticle: 81736
I have posted an answer in the VHDL forum Bert Andrew Doucette wrote: > Hello. I am writing VHDL code to be synthesized on a Xilinx Spartan II FPGA. For the past month, I've been beating my head against one problem with synthesizing the latest version of my code. I am using the Xilinx Webpack IDE V7.1.01i available for free from <http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack>. Synthesis usually takes about a minute with my previous code versions. When I added a few lines about a buffer and references to that buffer, and try to synthesize, the synthesis goes to 66% of completion normally, but then stays there for about 15 minutes before spitting out an out of memory error: > > ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 1954536 kb. Memory problems may require a simple increase in available system memory, or possibly a fix to the software or a special workaround. To troubleshoot or remedy the problem, first: Try increasing your system's RAM. Alternatively, you may try increasing your system's virtual memory or swap space. If this does not fix the problem, please try the following: Search the Answers Database at support.xilinx.com to locate information on this error message. If neither of the above resources produces an available solution, please use Web Support to open a case with Xilinx Technical Support off of support.xilinx.com. As it is likely that this may be an unforeseen problem, please be prepared to submit relevant design files if necessary. ERROR: XST failed Process "Synthesize" did not complete. > > I have stripped my program down to the simplest version that still exhibits the problem: > > library IEEE; use IEEE.STD_LOGIC_1164.ALL; > > entity frameCapture is port ( clk :in std_logic; lineBuffer : out std_logic_vector(1780 downto 0); --will buffer most significant 5 bits of each pixel on even lines. UV: in std_logic_vector(7 downto 0)); --Digital output from camera. UV bus. end frameCapture; > > architecture reg_transfer of frameCapture is > > signal bufPosOne, bufPosTwo, bufPosThree : integer range 0 to 1785; --are five more than they needs to be to prevent negative numbers. signal colCount : integer range 5 to 25 :=5; -- I picked these values in this example so that bufPosTwo and bufPosOne are obviously -- between 0 and 1785. begin > > bufPosTwo<= colCount*5+4; bufPosOne<= colCount*5+0; > > process (clk) begin if clk'event and clk = '1' then if colCount<= 25 then colCount <= colCount + 1; else colCount <= 5; end if; LineBuffer(bufPosTwo downto bufPosOne) <=UV (7 downto 3); end if; end process; > > end reg_transfer; > > ------- I have been trying to troubleshoot this problem for the past month, and have a deadline soon aproaching, so I am in desperate need of help. Is my bit of code doing anything illegal? Can you see any reason why my code should make the ISE work so hard it runs out of memory? From my experimentation, the problem does not have to do with colCount, but the indexing of LineBuffer with bufPosTwo and bufPosOne. > > Thanks for any help you can provide. It will be greatly appreciated! > > Sincerely, Andrew DoucetteArticle: 81737
IMO, the easiest to do this is in a UCF file. If you like PACE, it will create one for you. Otherwise, take an existing (non trivial) ucf, and modify it. Beware of busses notation, between <>, (), and [] ! Make sure your ucf text file is in your projnav, attached to your top level entity. And make sure you dont ask for the option to "ignore" it !!! Bert beagle197@hotmail.com wrote: > Some of the xilinx fpga pins are wired to leds. P39 for instance is > wired in such a way. In my design I have a vhdl counter and want to > direct ISE (v.6.3i) to tie the output of the counter to P39. What is > the way to do this? > > It seems that PACE does this, but then Floorplanner and FPGA Editor > seem to do something similar to this as well. When I tried to use PACE, > I saw I could specify the Loc as "BANK6", but could not figure out how > to directly assign to the pin #. In Floorplanner I could select > File->Read Constraints..., but wasn't sure this would do what I wanted > either. > > In Xilinx ECS I could create a schematic that wires together the vhdl > counter. It occurs to me that this is also a possible place to assign > the output to P39. Is that true? > > Thanks, > -beagle >Article: 81738
I am working on a memory interface where the data path in bi-directional. I have internal signals data_write and data_read. I need to tristate data_write when data comes into the device for data_read. I have a internal tri_state signal but can't seem to figure out the correct way to code this. ThanksArticle: 81739
sk@glui.de wrote: > hi mk, thanks much for the explanation! > (couldn't figure out what ISI stands for, though) > thanks, > sk ISI is Inter-Symbol Interference. Because of finite bandwidth, filtering, ringing etc, the analog level of a logic "1" will be different depending on whether it is preceded by a "0" or a "1". The preceding symbol interferes with the current symbol, hence the name. The word "symbol" is used instead of bit because there are many modulation schemes used in the communications world that encode multiple bits into each symbol. One symbol quals the (steady) information or state during one clock period. Regards, -rajeev-Article: 81740
On Wed, 30 Mar 2005 14:17:04 -0800, xyzzy <> wrote: >I am working on a memory interface where the data path in bi-directional. I have internal signals data_write and data_read. I need to tristate data_write when data comes into the device for data_read. I have a internal tri_state signal but can't seem to figure out the correct way to code this. > >Thanks assume an IO pad similar to following: module IO(PAD, IN, OUT, OE); inout PAD; output IN; // from the pad IN to the core input OUT; // OUT from the core input OE; wire IN = PAD; wire PAD = OE ? OUT : 1'bZ endmodule and see if you connect your data and tri-state signals to the ports of the IO. Normally you just need to connect your tri-state to the data PADs and your data_write & data_read should go to the control signals of the external memory.Article: 81741
andpaoli wrote:
>I'm new to math function on FPGA, but I need to calculate exp(-x) with
>a Spartan3 in fixed point 16bit numbers. How can i do that? What's the
>best way? Can someone help
>me?[size=24:ae1f1145a8][/size:ae1f1145a8]
>
>
>
I've posted on this subject before (search google using andraka and
exp) here is one such posting that is probably the closest to what you
want:
http://groups-beta.google.com/group/comp.arch.fpga/browse_thread/thread/47feb1a180f72f78/3cfe528ea11418b3?q=andraka+exp&rnum=5#3cfe528ea11418b3
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 81742
v_mirgorodsky@yahoo.com wrote:
> Several months ago I did schematic based design, implementing median
> image filtering in Altera EP1K30TC144-2. It was running something close
> to 150MHz without any explicit constraints, except target clock
> frequency.
That is quite often all you need.
> Now we are busy with another device, capable to run at 150MHz and we
> have XC2VP4 speed grade 6 Xilinx FPGA as a data processing unit within
> the device. I rewrote design using VHDL language. During verification,
> RTL schematic of synthesized VHDL code was looking exact like schematic
> for Altera ACEX-1k device. The only issue was speed. VHDL reincarnation
> of median filter was running only 134+MHz.
You have changed not just design entry, but the
device and the function. There are lots of ways to
drop fmax from "something close to 150MHz" to 134+ MHz.
Constraints are for fine tuning.
You could evaluate other synthesis tools,
but I expect you need to make some design tradeoffs.
Maybe a faster part, or use up extra resources
for wider datapaths.
-- Mike Treseler
Article: 81743Thanks Vasanth, Can you or anyone else reccomend an SMP OS for the Virtex II? Specifically, I am working on the ML310 board. There isn't much literature on running both cores at once, so any advice is appreciated. Currently I am looking at the MontaVista preview kit to see if that will get me going in the right direction. I think the software will eventually be fine, but then organizing the FPGA correctly may be a challenge... anyone do this kind of thing already? thanks againArticle: 81744
Hi, I need to instantiate a RAM in my Spartan3 FPGA. I need to be able to address 256 spaces, each space 8 bits, and maybe 5k samples..... I am trying to set this up for DNL and INL testing. Any idea on how to set this up??? I have looked at memory symbol in Xilinx, but none seems to satisfy this condition. So basically, I have data from 0 to 256 coming in, and I need to count how many times a data hit....Like for example, if I have 0, 1, 1, 2, 3, 3, 3 4, 5, 6, 255, 256...my count for bin 0 would be 1, for bin 1 would be 2 for bin 3 would be 3, for bin 255 would be 1, etc.. Thanks, AnnArticle: 81745
On Wed, 30 Mar 2005 16:15:35 -0800, Ann <ann.lai@aol.com> wrote: >Hi, I need to instantiate a RAM in my Spartan3 FPGA. I need to be able to address 256 spaces, each space 8 bits, and maybe 5k samples..... I am trying to set this up for DNL and INL testing. Any idea on how to set this up??? I have looked at memory symbol in Xilinx, but none seems to satisfy this condition. So basically, I have data from 0 to 256 coming in, and I need to count how many times a data hit....Like for example, if I have 0, 1, 1, 2, 3, 3, 3 4, 5, 6, 255, 256...my count for bin 0 would be 1, for bin 1 would be 2 for bin 3 would be 3, for bin 255 would be 1, etc.. Thanks, Ann That's a "histogram memory". Use an ordinary 256 x 8 ram. When you get a hunk of 8-bit data "D", set the memory *address to D*; read the ram, increment that, and write back. Stopping the incrementer at 255 is a good idea. You'll need a little state machine to manage it. JohnArticle: 81746
v_mirgorodsky@yahoo.com wrote: [...] > Now we are busy with another device, capable to run at 150MHz and we > have XC2VP4 speed grade 6 Xilinx FPGA as a data processing unit within > the device. I rewrote design using VHDL language. During verification, > RTL schematic of synthesized VHDL code was looking exact like schematic > for Altera ACEX-1k device. The only issue was speed. VHDL reincarnation > of median filter was running only 134+MHz. Howdy Vladimir, I'd investigate the timing analyzer output and see what is holding the design back. Do you have 5 failing paths or 100? Are there large fanouts involved on some of the failing paths? Are there too many levels of logic on some of the paths, and if so, can a pipeline stage be moved forward or back to help break up the levels of logic? Honestly, a -6 speed grade V2Pro should pretty easily meet 150+ MHz if fanout and levels of logic are kept under control. > So, is there any guide about constraints strategy? I read the guide > about constraints, but there are too many choices. I managed to remove > couple setup errors by explicit placing combinatorial logic and > registers in adjacent slices, but it would be horrible idea to do > manual chip routing :( I agree, and in this case, I suspect it would be unnecessary. What synthesis tool are you using? What clock speed are you telling the tools? You might try a slightly faster target speed to see if it helps you come much closer to meeting your period constraint, in addition to lowering fanout limits and investigating the number of levels of logic. Good luck, MarcArticle: 81747
Now in VHDL :) "mk" <kal*@dspia.*comdelete> wrote in message news:egdm41l703gmjekhpiqgeg7tb7qfodtkk4@4ax.com... > On Wed, 30 Mar 2005 14:17:04 -0800, xyzzy <> wrote: > >>I am working on a memory interface where the data path in bi-directional. >>I have internal signals data_write and data_read. I need to tristate >>data_write when data comes into the device for data_read. I have a >>internal tri_state signal but can't seem to figure out the correct way to >>code this. >> >>Thanks > > assume an IO pad similar to following: > > module IO(PAD, IN, OUT, OE); > > inout PAD; > output IN; // from the pad IN to the core > input OUT; // OUT from the core > input OE; > > wire IN = PAD; > > wire PAD = OE ? OUT : 1'bZ > > endmodule > > and see if you connect your data and tri-state signals to the ports of > the IO. Normally you just need to connect your tri-state to the data > PADs and your data_write & data_read should go to the control signals > of the external memory. >Article: 81748
skherich wrote: > I see two potential problems with what you are trying to do. > 1. As mentioned before you can only drive one IBUF/IBUFG from a Pad. > 2. Outputs of two DCMs from same reference clock can have a phase > offset. I am not sure of your application but something that you need > to be aware of if you are using Virtex2 devices. The V2Pro spec's a max of +/-140 ps (so I guess that's really 280 ps) of phase offset between DCM's, which I wouldn't think would be a problem for most designs running at reasonable clock rates. Although it isn't stated, I believe this phase spec only applies when using CLK0, CLK180, CLK90, CLK270, CLK2X, and CLK2X180. The phase of the divided outputs (CLKDV OR CLKFX) can not be controlled. Have fun, MarcArticle: 81749
Hi, all, Thanks for your reading! My project need transfer the data from the FPGA board to the Host PC. The transfer speed is about 25-50Mbps, does anyone konw if there is some commerical IP core/or evaluation board we could use with the Xilinx fpga directly? We would like to select the interface from the PCI, USB2.0 or 1394, I am very interested in using the usb2.0 interface, however, I only found the usb1.1 IP core right now, it is a little old for the future work. If you have the experience, could you provide some hints which is the best method and where I can find the IP cores/evaluation board, really appreciate you reply....
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