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Thomas Reinemann wrote: > Gerd wrote: > >> Thomas Reinemann <thomas.reinemann@masch-bau.uni-magdeburg.de> wrote: >> >>> against the background of partial reconfiguration, I would like to >>> determine the difference between two initial configurations (NCDs). >>> Does any Xilinx tool support this? >> >> >> >> You are probably looking for >> $ bitgen version1.ncd version1.bit >> $ bitgen -r version1.bit version2.ncd diff1to2.bit > > > Ok, I have forgotten to say, it should be human readable. Apart from the graphical representation given by fpga_editor, I think xdl is the only human readable form of the NCD database. Did you try the "diff -u" on two xdl files? I'm really curious to see if you get meaningful output. XDL contains all of the mapping, placement, routing, everything, in text format, so in principle it should be possible. JohnArticle: 71926
I am using Mathworks Simulink and Xilinx ISE tools for digital designs related to wireless communications. People who are using this design flow are requested to answer/ share their experience. The descreptionof my problem is as follows: I am using Xilinx black box in a Simulink Model and am using my VHDL code for its hardware implementation. The idea is to use the Simulink model as a test bed for checking my hardware model for Wireless/ DSP based algos. I have successfully checked the behavioral simulation of my Code using HDL Co-simulation. The next stage in my design flow is to take it to the target Xilinx FPGA device and complete synthesis and place and route. At this stage, I want to go back to my Simulink model and use it to test my placed and routed model (now available in the form of flat netlist with Xilinx Simprims and SDF file (timing info file). I am able to verify post PAR outside Simulink by using my own test bench and controlling the clock myself in it. I want to do the same with the simulink model and check the results in simulink environment. Now the problem is: 1) How to control the clock that is generated automatically, whenever the simulation is started from within simulink. I dug into the files that are generated by Simulink for making a simulation model for HDL Co simulation, and found that it generated the clock with period 6.25 ns always. Question is that is it possible to change this clock period. 2) How to link the SDF file in the simulation model that is generated from within Simulink for HDL Co simulation, for doing Post PAR simulation with simulink data. 3) If all above is not possible, then is there any way to make a test bench with the simulink generated data (the data that is available right after the gateway blocks). If this is possible then I can test my model outside simulink in modelsim environment. Thanks, Mukesh.Article: 71927
A CIC filter cannot be implemented in floating point. To get it to work it must be done in non-saturating integer math, such as is done using non-saturating two's complement representation. The integer math must wrap around. Dirk A. Bell tom1@launchbird.com (Tom Hawkins) wrote in message news:<833030c0.0408030627.59752b71@posting.google.com>... > jjohnson@cs.ucf.edu (Mark) wrote in message news:<c88fa005.0408021903.4e75e599@posting.google.com>... > > I've got a minor DSP/comm task to put in an FPGA: > > > > Complex demod to baseband, CIC+decimate+FIR LPF chain, magnitude > > estimate, some FSK and DPSK data to interpolate, correlate and > > extract, plus other sundry tasks. > > > > I'd like to model this all in untimed/behavioral floating-point, have > > a quick way to evaluate filtering options (including IIR, varying > > lengths and structures/forms) and quantization effects, with automatic > > conversion to a somewhat optimal fixed-point implementation that a > > tool can automatically write out as VHDL (RTL, not behavioral). > > Parameterizable block diagram entry is a plus. Probes/sinks with FFT > > and time plots and file writes at nodes of interest are also > > desireable. (SUMMARY: design/analyze at high level, let tools do > > dirty, low-level work.) > > For architectural exploration, take a look at the new behavioral > synthesis tools coming on-line. If money is no object, consider > Mentor's CatapultC (was PrecisionC). > > CatapultC takes an untimed C model and converts it to RTL. You guide > the compilation process specifying which for-loops to unroll, which > arrays to make memories, etc. The process is fast, and you can > quickly compare alternative architectural decisions -- the tool plots > a graph of area vs. performance so you can see which decision fits > with your application. > > Other companies in this space include Forte (Cynthesizer), AccelChip, > and Celoxica. If you can't fork out $100K+, consider SPARK. It maps > untimed C to RTL. It's not free (as in open-source) and I don't know > the license restrictions. > > http://mesl.ucsd.edu/spark/ > > > For parametric designs, take a look at Confluence -- a functional > programming language for generating synchronous netlists (outputs > Verilog, VHDL, C). It's cheap (GPL) and the language was originally > designed for DSP. > > http://www.confluent.org/ > > Though the process of mapping floating-point to fixed-point is not > automated, you just have to write the conversion algorithm once. Then > afterwards, when you change coefficient values, precision, the number > of coefficients, or any other parameter, the flow is completely > push-button. > > -TomArticle: 71928
To further that thought, if you use a transformer you can remove the common mode votages, and bias them yourself on the isolated side of the transformer. This is documented in Crystal semiconductor products since digital audio uses RS 422 for transmission. See CS8415 data sheets and app notes. A couple of transient voltage suppressors as well and you're in business. "Jim Granville" <no.spam@designtools.co.nz> wrote in message news:%nTPc.1606$zS6.195491@news02.tsnz.net... > Rune Christensen wrote: > > Hello > > > > Is it possible to connect a RS422 differential signal directly to a FPGA > > instead of using a converter from RS422 to TTL voltage levels? > > Would it be possible for a FPGA to create a RS422 signal? > > > > Is there any information about this on the internet? > > Possible, yes. Practical, maybe not. > Most FPGAs have differential IP modes, so could accept RS422 IPs, > with the caveat, WITHIN their common mode range. > For true RS422/485 devices, that is around -7V..+12V, which allows > ground movement between ends of the cable. > FPGA pin common mode is much less than this, but you could extend it > with a resistor pad (which also attenuates the wanted signal ) > Then there is ESD protection. Most separate RS422/485/CAN transcievers > have higher tolerance to ESD, than FPGA. > > RS422 output needs sufficent drive current, and balanced drive, but > that is within the capability of FPGA. > For short-haul, and within-the-box signaling, this could be do-able, > but perhaps not for connection to 100m cables in a factory... > -jg >Article: 71929
"Nicolas Matringe" <matringenicolas001@numeri-cable.fr> wrote in message news:410FCA53.70701@numeri-cable.fr... > Hello all > I have just downloaded the WebPack and am terribly surprised: I can't > find how to instantiate standard IP cores such as memories. CoreGen > isn't part of WebPack, so how are users supposed to use memories and so on? by direct instantioting ?? of start the schematics editor, place the memory primitive and later look at the vhdl/verilog core generated for the schematics antti http://xilinx.openchip.orgArticle: 71930
Due to a calamtity of computer problems, including some affecting my backups, I'm suddenly in desparate need of StateCad Version 4.11 (or possibly Version 5.0) to support an active project. An evaluation version is fine. Can anyone help?Article: 71931
Hello Steven, Thanks for the input. Our Avnet distributors have been real good about providing data books and eval boards so I'm well equipped in that sense. My concerns are for moving things to production. To be totally honest with you, this is the first I've heard of the status of the 3S50ES part -- I was told that Avnet already has stock on them! I'll be sure to confirm part numbers with them. In the mean time -- I'll have to admit that the Spartan IIE appears to be a better fit for the application (3.3 compatibility required, possible 5v inputs, no need for two LDOs) as it's not logic or computationally intensive. It's just too bad it costs more than the 3S50ES part! Thanks again, Gordon "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:<cep28v$r2q1@cliff.xsj.xilinx.com>... > [snip] > > > We're looking at the Spartan-3 3S50ES part. > > I forgot to mention one other item. > > If you want to create some initial designs for your XC3S50 application > without needing to build hardware, you might want to investigate the > Spartan-3 Starter Kit Board. It has an XC3S200 FPGA in the FT256 package, > plus a host of other interfaces, 1M of SRAM, a JTAG download cable, plus > software. The board is in stock and sells for $99 plus applicable tax and > shipping. > > Spartan-3 Starter Kit Board > http://www.xilinx.com/s3boards > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/II/IIE FPGAs > http://www.xilinx.com/spartan3 > --------------------------------- > Spartan-3: Make it Your ASICArticle: 71932
On Tue, 03 Aug 2004 14:16:07 +0200, Sylvain Munaut wrote: > Matt North wrote: >> Hi, >> >> I have written VHDL code which generates standard VGA Timing signals; 640 x >> 480 resolution 60Hz refresh rate. >> My question is this; my test monitor is a SONY SDM-S93 which has a >> resolution of 1280 x 1024, the HSync, VSync and Blanking >> periods all meet with the specifications of the monitor. >> However how does the monitor know that i will only use 640 out of a possible >> 1280 dots per line, and 480 lines out of 1024? > > The monitor just sees the syncs and blank levels and get it right. He just match the time between two hync to it's full line. Idem for vsync. There is a small twist to this - the true VGA spec uses the polarities of the syncs to encode the resolutions, and some older fixed frequency monitors use this. vsync hsync vert_size + + reserved + - 400 lines - + 350 lines - - 480 lines A good way to think about this is that a monitor is ultimately an analog device - somewhere in it's guts is a pair of fancy ramp generators making high voltage sawtooth waves to sweep the electron beam(s) across the face of the tube. A fancy amplifier drives the electron beam(s) on and off. The multisync monitors adjust the frequencies of the sawtooths to match the input hsync and vsync. The video amplifiers look at the blanking level and at analog inputs and amplify what's there. Whether the dot you send shows up on the screen depends on things like how fast the video amplifiers are, how well focused the beam is, how small of a dot the picture tube can actually resolve. It's perfectly possible to drive a "640x480" monitor with 1024x768 if you keep the horizontal and vertical frequencies in spec - individual pixels just may not show up all that well. LCDs are a very different beast - they definitely have the concept of a pixel as a defined location on the display and if you don't send enough pixels, you don't fill up the screen.Article: 71933
Gupta wrote: > Got any tips on how to evaluate the various offerings ? I am looking > at about a 1 million gate design, with moderate/easy performance > requirements. Does this analysis change if I am working on a 500K > gate design ? A million "ASIC" gates or "FPGA" gates? The gate count in FPGA mfg specs are notoriously overblown when compared to an ASIC design. You should try to quantify your design size in terms of flip flops, 4-input lookup tables and ram. The granularity of a 2 input nand gate is meaningless in the FPGA world, which is how the mfg's get away with such wildly optimistic numbers. JeffArticle: 71934
Hi, I would like to know if there is any literature from Xilinx, Altera or anywhere that gives the designer a set of design guidelines in order to achieve timing closure on FPGAs. For example, I have seen some people use a guideline which says that the number of combinatorial levels in the design should not exceed say 7 levels or so. Another example is that the combinatorial delay should not exceed 50% of the clock period so that there is enough margin for routing delays. I have come across these through word of mouth. I would really like to get my hands on some literature to back these up. Thanks, Kiran.Article: 71935
Hi, Gupta <gupg@hotmail.com.NOSPAM> wrote > Lattice's website that they too have Flash based FPGAs. Does Flash > really have an advantage over SRAM (claim is that Flash is one > transistor versus 6 transistors required for SRAM) ? Flash has the advantage of storing your design even after power down. SRAM needs to load the bitstream after power up, so you usually need an additional EPROM on Boardlevel. I wouldn't bother about the transistor quantity. The questions are: - Speed - IO number - IO levels - Package (-size) - Area (usability of cells, e.g. Xillinx wouldn't allow you to use 100% of the cells) - Embedded RAM - volatile - reconfigurable - power supply (low power, different levels,...) - Software (prize) - Cost for additional HW (Download cable, programmer for fusebased Fpgas,..) First define and weight your needs, than choose the best applicable device. bye ThomasArticle: 71936
On 3 Aug 2004 23:15:30 -0700, kirandev@msn.com (Kiran) wrote:
>Hi,
>I would like to know if there is any literature from Xilinx, Altera or
>anywhere that gives the designer a set of design guidelines in order
>to achieve timing closure on FPGAs. For example, I have seen some
>people use a guideline which says that the number of combinatorial
>levels in the design should not exceed say 7 levels or so.
Ouch! I'm currently writing something that will run at > 300MHz. I'm
restricting it to 1 level of combinatorial logic and limiting the
fanout to 10 ('cause I'm in a slow speed grade part).
Obviously rules of thumb are based around certain assumptions. You
need to know how fast your chip is (w.r.t. your clock rate), whether
you are doing floorplanning, etc.
Note that FPGA flip flops are basically free. Don't be afraid to use
them to make the routing easier.
>Another
>example is that the combinatorial delay should not exceed 50% of the
>clock period so that there is enough margin for routing delays.
This one is fairly good, although floorplanning (good or bad) can make
a difference. Note that a tightly packed part will often produce a
few excessively long delays due to routing congestion.
>I
>have come across these through word of mouth. I would really like to
>get my hands on some literature to back these up.
Never seen this in writing. Experience is the key.
Regards,
Allan.
Article: 71937Check out the "Timing Closure - 6.1i" TechXclusive on the Xilinx support site. Have fun, Guy.Article: 71938
Thanks for the information I think I will go for the interface chip it looks like the most simple solution. Cheers Rune "Jason Berringer" <look_at_bottom_of@email.com> skrev i en meddelelse news:jmXPc.21006$Jq2.927116@news20.bellglobal.com... > To further that thought, if you use a transformer you can remove the common > mode votages, and bias them yourself on the isolated side of the > transformer. This is documented in Crystal semiconductor products since > digital audio uses RS 422 for transmission. See CS8415 data sheets and app > notes. A couple of transient voltage suppressors as well and you're in > business. > > > "Jim Granville" <no.spam@designtools.co.nz> wrote in message > news:%nTPc.1606$zS6.195491@news02.tsnz.net... > > Rune Christensen wrote: > > > Hello > > > > > > Is it possible to connect a RS422 differential signal directly to a FPGA > > > instead of using a converter from RS422 to TTL voltage levels? > > > Would it be possible for a FPGA to create a RS422 signal? > > > > > > Is there any information about this on the internet? > > > > Possible, yes. Practical, maybe not. > > Most FPGAs have differential IP modes, so could accept RS422 IPs, > > with the caveat, WITHIN their common mode range. > > For true RS422/485 devices, that is around -7V..+12V, which allows > > ground movement between ends of the cable. > > FPGA pin common mode is much less than this, but you could extend it > > with a resistor pad (which also attenuates the wanted signal ) > > Then there is ESD protection. Most separate RS422/485/CAN transcievers > > have higher tolerance to ESD, than FPGA. > > > > RS422 output needs sufficent drive current, and balanced drive, but > > that is within the capability of FPGA. > > For short-haul, and within-the-box signaling, this could be do-able, > > but perhaps not for connection to 100m cables in a factory... > > -jg > > > > --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.733 / Virus Database: 487 - Release Date: 02-08-2004Article: 71939
Hi, there: My Xilinx software generated a flattened netlist and SDF each over 100MB...Now NC_Verilog takes hundreds of hours to simulate that. Now if I write a perl to replace all the long wire names with some random 10-alphabet string, it will probably shrink the file size to 10MB...But will that make my simulation faster? ---sample wire \modem/bt_top/demodulator/u_demod/dif_dsp_core/u_demod/div_step_2_div_step(1 0)/F ; wire \modem/bt_top/demodulator/u_demod/dif_dsp_core/u_demod/div_step_2_div_step(1 0)/G ; Thanks. KelvinArticle: 71940
I was actually thinking about implemeting something similar, but for direct RF modulation. Plan was to have m-phases of a clock as the data pattern, update it at the modulation rate and bandpass filter the output. Haven't tried it out yet, but I imagine you end up with M-PSK around the carrier. Unfortunately Your maximum RF frequency drops precipitously as m-increases. Yeah, it's probably easier to use an LO and a mixer, but getting BPSK through S -band would be pretty nifty coming from an FPGA. Anyone tried this or any comments on feasibility? --Josh Anyone know if you could you could "Peter Alfke" <peter@xilinx.com> wrote in message news:BD354D8A.7D3A%peter@xilinx.com... > I see no reason to doubt this. In fact, I intend to do the same thing. > Note that in V2Pro the parallel interface is 10 or 20 bits wide, not 8 or 16 > bits. This requires some digital trickery once you go beyond 4-bit patterns > on the parallel side. Let me know if you run into any snags... > Peter Alfke > > > > From: "Robert Sefton" <rsefton@abc.net> > > Newsgroups: comp.arch.fpga > > Date: Tue, 3 Aug 2004 13:36:09 -0700 > > Subject: clock synthesis with RocketIO > > > > I'm looking at using a V2P RocketIO transmitter to synthesize a clock by > > bypassing the 8B10B encoder and feeding it 01010101 data words. I would > > vary the output clock frequency by varying the reference clock and/or > > the data pattern (00110011, 00001111, etc.). Is there any reason this > > would not work? > > > > Thanks, > > > > Robert > > > > (Reply email address is bogus. Please reply to group.) > > > > >Article: 71941
Hi Kiran,
The chapter on "Design Optimization for Altera Devices" in the
Quartus Handbook can answer some of your questions. It covers techniques for
both resource closure (fitting with the smallest number of resources) and
timing closure. This can be accessed from:
http://www.altera.com/literature/hb/qts/qts_qii52005.pdf
The timing reports in the Quartus tool are very useful in giving you the
delay of the critical paths, and in their breakup between Logic cell delay
and Routing Delay. Quartus II 4.1 has two tools: the Resource Optimization
Advisor and the Timing Optimization Advisor, which help you identify which
tool capabilities are applicable in achieving your optimization goals. These
are accessed from the Tools menu, and should be used after you have compiled
your design.
Hope this helps.
- Subroto Datta
Altera Corp.
"Kiran" <kirandev@msn.com> wrote in message
news:9043844f.0408032215.1129b9ec@posting.google.com...
> Hi,
> I would like to know if there is any literature from Xilinx, Altera or
> anywhere that gives the designer a set of design guidelines in order
> to achieve timing closure on FPGAs. For example, I have seen some
> people use a guideline which says that the number of combinatorial
> levels in the design should not exceed say 7 levels or so. Another
> example is that the combinatorial delay should not exceed 50% of the
> clock period so that there is enough margin for routing delays. I
> have come across these through word of mouth. I would really like to
> get my hands on some literature to back these up.
> Thanks,
> Kiran.
Article: 71942Hi, thanks for the reply, this looks very interesting. I didn't know you could control all the bits going out of the rocketIO, I thought it was made to generate some specific serial protocol pattern. Does Xilinx have an eval board for that? I really like the xilinx type of eval. board, such as the ones for virtexIIpro: http://www.xilinx.com/xlnx/xebiz/board_detail.jsp?=&category=-21482&iLanguageID=1&key=HW-AFX-FF1152-300 They are really simple with the prototype area easiliy accessible. However, they say: ''The AFX board should NOT be used when designing with or characterizing RocketIO™ transceivers'' I could only find something here: http://www.insight.na.memec.com/Memec/iplanet/link1/VirtexIIPro_FF1152_2.pdf ...but it doesn't look too appealing to me. Regards, David Peter Alfke <peter@xilinx.com> wrote in message news:<BD354F7F.7D3D%peter@xilinx.com>... > You can use RocketIO. > In Virtex-IIPro it can handle 3.125 Gbps, which means a ~320 ps bit time. > Just run the MGT with a 156.25 MHz Fref, and apply the appropriate data > pattern on the parallel ( 10 or 20-bit) side. > In Virtex-IIProX you can go more than 3 times faster... > Peter Alfke > > > From: gretzteam@hotmail.com (David) > > Organization: http://groups.google.com > > Newsgroups: comp.arch.fpga > > Date: 3 Aug 2004 14:11:48 -0700 > > Subject: Can I use RocketIO to generate pulse edge with very high precision? > > > > Hi, > > I need to generate a 1-bit signal with very high resolution on the > > position of the edges. I would need about 2 to 3GHz resolution. It is > > quite hard to have a 3Ghz clock nowadays, so I wonder if the RockedIO > > could be used for that. > > > > Thanks, > > DaveArticle: 71943
"Kelvin" <kelvin_xq@yahoo.com> wrote in message news:<41109c40@news.starhub.net.sg>... > My Xilinx software generated a flattened netlist and SDF each over > 100MB...Now NC_Verilog > takes hundreds of hours to simulate that. > > Now if I write a perl to replace all the long wire names with some random > 10-alphabet string, > it will probably shrink the file size to 10MB...But will that make my > simulation faster? > Thanks. > Kelvin My guess is that it will shorten the time needed to perform the steps that read in these files. With NC that would be compilation and elaboration. However, I expect it wouldn't really change actual simulation time because you're not changing the design. On my last chip, compiling and elaborating the gate-level netlist with SDF timing took 45 minutes to an hour, so if renaming everything reduced that even by half, it might have been worth it. Understand that your renaming script will take a while to run, because it has to read in these huge files, but if you get lots of simulation runs for each renaming pass then you should come out ahead. Only one way to really find out though, you have to try it. -cbArticle: 71944
David, The reason for the disclaimer is that some of these ML series boards are intended to show off other features, and we did not follow our own rules when bypassing, routing, and in general, supporting the MGT signals as the board wasn't intended for that purpose. The MGT works, and the board would be useful for what you want, as all you care about here is generating an output! Getting an error free channel at 3.125 Gbs over the longest XAUI backplane is definitely not supported by those boards that state so, but for basic MGT operation, they work just fine. If you bypass the 8B10B codec, then you are responsible for all the bits, which is very nice to do what you want. Austin David wrote: > Hi, > thanks for the reply, this looks very interesting. I didn't know you > could control all the bits going out of the rocketIO, I thought it was > made to generate some specific serial protocol pattern. Does Xilinx > have an eval board for that? I really like the xilinx type of eval. > board, such as the ones for virtexIIpro: > http://www.xilinx.com/xlnx/xebiz/board_detail.jsp?=&category=-21482&iLanguageID=1&key=HW-AFX-FF1152-300 > They are really simple with the prototype area easiliy accessible. > However, they say: ''The AFX board should NOT be used when designing > with or characterizing RocketIO™ transceivers'' > > I could only find something here: > http://www.insight.na.memec.com/Memec/iplanet/link1/VirtexIIPro_FF1152_2.pdf > > ...but it doesn't look too appealing to me. > > Regards, > David > > Peter Alfke <peter@xilinx.com> wrote in message news:<BD354F7F.7D3D%peter@xilinx.com>... > >>You can use RocketIO. >>In Virtex-IIPro it can handle 3.125 Gbps, which means a ~320 ps bit time. >>Just run the MGT with a 156.25 MHz Fref, and apply the appropriate data >>pattern on the parallel ( 10 or 20-bit) side. >>In Virtex-IIProX you can go more than 3 times faster... >>Peter Alfke >> >> >>>From: gretzteam@hotmail.com (David) >>>Organization: http://groups.google.com >>>Newsgroups: comp.arch.fpga >>>Date: 3 Aug 2004 14:11:48 -0700 >>>Subject: Can I use RocketIO to generate pulse edge with very high precision? >>> >>>Hi, >>>I need to generate a 1-bit signal with very high resolution on the >>>position of the edges. I would need about 2 to 3GHz resolution. It is >>>quite hard to have a 3Ghz clock nowadays, so I wonder if the RockedIO >>>could be used for that. >>> >>>Thanks, >>>DaveArticle: 71945
Hi Kevin,
Kelvin wrote:
> Hi, there:
>
> My Xilinx software generated a flattened netlist and SDF each over
> 100MB...Now NC_Verilog
> takes hundreds of hours to simulate that.
>
> Now if I write a perl to replace all the long wire names with some random
> 10-alphabet string,
> it will probably shrink the file size to 10MB...But will that make my
> simulation faster?
> ---sample
> wire
> \modem/bt_top/demodulator/u_demod/dif_dsp_core/u_demod/div_step_2_div_step(1
> 0)/F ;
> wire
> \modem/bt_top/demodulator/u_demod/dif_dsp_core/u_demod/div_step_2_div_step(1
> 0)/G ;
>
>
> Thanks.
> Kelvin
>
>
>
This will not help much, it will just speedup the simulation startup
because of less file reading.
It will help more to check if you used all performance switches (and
aviod performance degrading options like +access+rwc or linedebug ;-)).
The online documentation (cdsdoc) has a dedicated chapter ('Maximising
simulation performance') for it.
HTH
-Eyck
Article: 71946Hi Steve, Hi Eric I was trying to retrieve the errata for spartan 3 FPGAs but got this message instead. "Sorry... Technical difficulties with the Xilinx.com web site have been solved. If you are continuing to have difficulty accessing Xilinx.com, you may need to exit your browser software and restart it. Please accept our apologies for any difficulties you have experienced. " I tried restarting my browser but to of no avail. Can anybody send me the errata for Spartan 3? If there is no errata for the device XC3s1000 FG456, is it safe to assume that the device is into production and NOT Engineering Samples? thanks Krishna KumarArticle: 71947
Another possibility is to add the UART as a DCR peripheral rather than a PLB/OPB peripheral. This will keep the UltraController small, but still allow you to expand the capabilities beyond a 32-bit input/output through the BRAM Port B. Then it is up to you how you decide to implement the UART. (Add a FIFO, etc.) You will need to access it using assembly instructions (over the DCR) but you can now have a non-blocking read/write access to the UART. Cheers, Mark Xilinx -FAE Joe wrote: > Matt, > > I tried this before with no success. The Amount of changes needed to > add a PLB or OPB to the Ultracontroller causes a lot of errors unless > you are pretty experienced with EDK. > > Also, I posted this same question to the embedded processor forum on > the Xilinx website, here is the post and response: > > Matthew Ouellette "UltraController and UART" 3/10/04 10:26am > > Your best bet is probably to create a new project and add the required > busses. Try to find a MHS that has the PPC and UART from someone (I'm > in a different lab now or I'd send one to you.) Then you will need to > create a custom IP core for your logic using the IPIF. > > Good luck, > JoeArticle: 71948
In Xilinx Application Note 759 we created a DCR to OPB bridge and then instanitated a OPB Uartlite. This also kept the size of the UltraController small while giving us the same functionality that you are looking for. Check out the PPC sub-system in XAPP759 as an example on how to implement the Uartlite in hardware. Shalin- Mark Sasten wrote: > Another possibility is to add the UART as a DCR peripheral rather than a > PLB/OPB peripheral. This will keep the UltraController small, but still > allow you to expand the capabilities beyond a 32-bit input/output > through the BRAM Port B. > > Then it is up to you how you decide to implement the UART. (Add a FIFO, > etc.) You will need to access it using assembly instructions (over the > DCR) but you can now have a non-blocking read/write access to the UART. > > Cheers, > > Mark > Xilinx -FAE > > Joe wrote: > >> Matt, >> >> I tried this before with no success. The Amount of changes needed to >> add a PLB or OPB to the Ultracontroller causes a lot of errors unless >> you are pretty experienced with EDK. >> >> Also, I posted this same question to the embedded processor forum on >> the Xilinx website, here is the post and response: >> >> Matthew Ouellette "UltraController and UART" 3/10/04 10:26am >> </cgi-bin/forum?13@@.ee82d7b/0> >> >> Your best bet is probably to create a new project and add the required >> busses. Try to find a MHS that has the PPC and UART from someone (I'm >> in a different lab now or I'd send one to you.) Then you will need to >> create a custom IP core for your logic using the IPIF. >> >> Good luck, >> Joe >>Article: 71949
Thanks Rick. You are right that if the size of the transistor does not reflect, I shouldn't care on the cost metric. But what about the performance metric ? Does smaller size of the configuration memory improve the performance, because the size of the FPGA will be smaller for the same number of gates (assuming that its in the same process technology).
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