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Messages from 71875

Article: 71875
Subject: Re: FPGA Selection--
From: "Ulf Samuelsson" <ulf@atmel.dot.com>
Date: Tue, 3 Aug 2004 10:00:32 +0200
Links: << >>  << T >>  << A >>

"George" <george.martin@att.net> skrev i meddelandet
news:e9d879fa.0407211202.5f0f81ef@posting.google.com...
> I've attempting to select an FPGA for a new design.
>
> The design will have 9 of the following:
>        12 bit latches
>        12 bit down counter
>         1 bit output latch
>
> So one measure of the size might be 25 registers * 9 = 225 registers.
>
> The counting freq is 15 MHz.
>
> The latches get loaded from an existing micro.  So I need a 12 input
> pins for a data buss, 4 input pins for which register, a clock pin and
> let's say 4 pins for control lines.
> Along with the 9 output signals.
>
> So another measure is 12+4+1+4+9 = 30 pins not counting power and
> ground.
>
> It would also be desirable to be packaged in a PLCC but TQFP in ok.
>
> And the device should be reprogrammable using JTAG (add 4 more pins).
>
> Voltage is not much of an issue.  However 5 V tolerant I/O would be
> nice.
>
> I've looked at Lattice and Altera and haven't found the perfect
> solution.  I can  use larger than necessary Altera devices (ACEX1K)
> but that seems to be the wrong direction.
>
> Any suggestions/recommendations.


Check out the AT94K10 or AT94K05.
This gives you both the (AVR) micro and the FPGA.

-- 
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.

>
> Thanks
> George



Article: 71876
Subject: Re: [VHDL] Personnal type as port
From: "Alan Fitch" <alan.fitch@doulos.com>
Date: Tue, 3 Aug 2004 10:27:53 +0100
Links: << >>  << T >>  << A >>

"Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> wrote in
message news:410a7cfe$0$31463$ba620e4c@news.skynet.be...
> Hi
>
> I know how to define a personal type to use as a signal but how to
use one as a port ?
>
>

You must declare the type in a package. If you do
it all in one file, this will work...

library IEEE;
use IEEE.std_logic_1164.all;
package mytypes is
  subtype ByteT is std_logic_vector(7 downto 0);
end package mytypes;

use WORK.mytypes.all;

library IEEE;
use IEEE.std_logic_1164.all;

entity e is
 port (i : in mytype;
       o : out std_logic_vector(15 downto 0));
end entity e;

architecture a of e is

begin

  process(i)
  begin
    o <= i & i;
  end process;
end architecture a ;

This of course is a subtype rather than a type, but
the principle is the same,

regards

Alan


-- 
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223                          mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573                           Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.


Article: 71877
Subject: Re: Best tool(s) for filter float->fixed->VHDL flow?
From: "Arash Salarian" <arash.salarian@epfl.ch>
Date: Tue, 3 Aug 2004 11:38:26 +0200
Links: << >>  << T >>  << A >>
Hi,

There is a new toolbox for MATLAB called "Filter Design HDL Coder" that adds
the VHDL code generation feature to the filter design tool. As you may know,
filter design tool of MATLAB can already convert the floating point
cofficents to fix-point and this new tool box gives you the last ring of the
chain, the Code Generation. However I think you can only use it with the new
MATLAB R14 so if you are using an older version of MATLAB, maybe the whole
solution be a bit expensive.

Regards
Arash



Article: 71878
Subject: Re: Best tool(s) for filter float->fixed->VHDL flow?
From: gelbart@ICSI.Berkeley.EDU (David Gelbart)
Date: Tue, 3 Aug 2004 10:44:01 +0000 (UTC)
Links: << >>  << T >>  << A >>
I don't work in this area but I have heard of some companies
whose technology may interest you

http://www.accelchip.com
http://www.catalyticinc.com

In article <c88fa005.0408021903.4e75e599@posting.google.com>,
Mark <jjohnson@cs.ucf.edu> wrote:
>I've got a minor DSP/comm task to put in an FPGA:
>
>Complex demod to baseband, CIC+decimate+FIR LPF chain, magnitude
>estimate, some FSK and DPSK data to interpolate, correlate and
>extract, plus other sundry tasks.
>
>I'd like to model this all in untimed/behavioral floating-point, have
>a quick way to evaluate filtering options (including IIR, varying
>lengths and structures/forms) and quantization effects, with automatic
>conversion to a somewhat optimal fixed-point implementation that a
>tool can automatically write out as VHDL (RTL, not behavioral).
>Parameterizable block diagram entry is a plus. Probes/sinks with FFT
>and time plots and file writes at nodes of interest are also
>desireable. (SUMMARY: design/analyze at high level, let tools do
>dirty, low-level work.)
>
>Maybe I ask too much ;-) but it seems like this is such a common
>problem and flow that solutions would abound. However, I've been out
>of the DSP world for a while, and don't know what the best, cheapest,
>or most productive tool options are...
>
>What would the gurus of comp.dsp and comp.arch.fpga suggest?
>
>I have access to MathCad, Matlab (with FDAT), Simulink, and possibly
>LabView (National Instruments?) and (Cocentric System Studio (Synopys)
>but am not fluent with them.
>
>I've entered the design in Cadence/CoWare's SPW, but am getting
>frustrated with it -- not as easy to explore different architectures
>as I had hoped.
>
>I suppose Ptolemy is an option, if the learning curve is not
>staggering. Agilent has some Ptolemy add-ons for fixed-point analysis
>and optimization, but they're not free or in my company's budget for
>this project.
>
>Any and all constructive suggestions are very much appreciated; thanks
>in advance...
>
>MarkJ



Article: 71879
Subject: Re: NCD difference
From: Thomas Reinemann <thomas.reinemann@masch-bau.uni-magdeburg.de>
Date: Tue, 03 Aug 2004 13:56:46 +0200
Links: << >>  << T >>  << A >>
Gerd wrote:

> Thomas Reinemann <thomas.reinemann@masch-bau.uni-magdeburg.de> wrote:
> 
>>against the background of partial reconfiguration, I would like to 
>>determine the difference between two initial configurations (NCDs). Does 
>>any Xilinx tool support this?
> 
> 
> You are probably looking for
> $ bitgen version1.ncd version1.bit
> $ bitgen -r version1.bit version2.ncd diff1to2.bit

Ok, I have forgotten to say, it should be human readable.

Tom

Article: 71880
Subject: Re: VGA Signals
From: Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com>
Date: Tue, 03 Aug 2004 14:16:07 +0200
Links: << >>  << T >>  << A >>
Matt North wrote:
> Hi,
> 
> I have written VHDL code which generates standard VGA Timing signals; 640 x
> 480 resolution 60Hz refresh rate.
> My question is this; my test monitor is a SONY SDM-S93 which has a
> resolution of 1280 x 1024, the HSync, VSync and Blanking
> periods all meet with the specifications of the monitor.
> However how does the monitor know that i will only use 640 out of a possible
> 1280 dots per line, and 480 lines out of 1024?

The monitor just sees the syncs and blank levels and get it right. He just match the time between two hync to it's full line. Idem for vsync.


> Do i have to send it some control info via the DC0-3 pins?

No


> I understand that the monitor can display lower resolutions because this can
> be done inside windows!
> When selecting 640x480 resolution in windows the screen is stretched to fill
> the monitor; does this mean that the graphics card
> is always running at the 1280x1024 frequency and adds pixel data to fill the
> screen?

No

Article: 71881
Subject: Re: DDR or SDR ? Memory controller in FPGA
From: Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com>
Date: Tue, 03 Aug 2004 15:28:40 +0200
Links: << >>  << T >>  << A >>
Hi

> Even more important than avoiding T connections, is keeping them short,
> very short.  You can even drive a star arrangement if you can keep all
> traces to about 1 inch (2.5 cm) or so.  The reflections are then a small
> fraction of the rise time and will not be significant.  Or you can make
> every memory pin a separate net and use simple series resistors (which
> can be integrated in some FPGAs) on the outputs.  Point to point drivers
> are very simple and hard to screw up.

I'll try to keep as short and matched as I can.

I was a little worried because in all datasheet/application notes/... they say to simulate with IBIS models. I've tried the HyperLynx demo and that's sure looks a good tool. But I can't afford a 18000$ soft ... (and the demo is VERY limited).

 
> Also, if you are at all concerned about a long life for your product,
> you should go with DDR.  SDRAM is already on the way down the curve and
> will only get more expensive in the future (unless we have another bust
> cycle).  32 bit parts are niche parts like most SRAM, 16 bit parts are
> more mainstream, but not quite jellybean while the 8 bit parts which are
> used widely in PCs are fully commodities which will be the low cost per
> bit of any memory.  You can even get them in extra small packages (which
> are used for laptops).  I don't know if any of this is a consideration
> for you.

I'm interested in "long" life yup ;)
I was planning to use 16bits parts because 32bits are too rare/expensive/... And 8 bits, you need 4 to make a 32bits bus. That becomes a lot harder to route and get it right.


Sylvain

Article: 71882
Subject: Re: DDR or SDR ? Memory controller in FPGA
From: Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com>
Date: Tue, 03 Aug 2004 15:35:11 +0200
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> Sylvain Munaut wrote:
> <snip>
> 
>> That chip would be more that enough in fact I was planning for 
>> 8Mbytes. But with 32 bit width, I'll have 16Mb, that's ok.
>> But these are SDRam, not DDR. Well I'll see what I take because DDR 
>> seem harder to drive than SDR and I also'd like to spare space in the 
>> FPGA, else I won't have any space to put stuff that could use the 
>> extra bandwidth.
> 
> 
>  With wider memory, you get more Bytes/ns, and I would suggest a look
> at std Sync SRAM, as well as the Celluar PSRAM from Micron, as these
> are getting to this Size in a single device.
>  Package may be more an issue ?
> A single RAM device will be much easier to route, than many devices.
> -jg

Package is not a concern.
What concerns me with SyncSRAM & Cellular PSRAM would be the higher cost. But I'll have a look.


Sylvain Munaut

Article: 71883
Subject: Re: adding real UART to xilinx ultracontroller design.
From: Joe <petrone@eng.fsu.edu>
Date: Tue, 3 Aug 2004 06:53:13 -0700
Links: << >>  << T >>  << A >>
Matt, 

I tried this before with no success. The Amount of changes needed to add a PLB or OPB causes a lot of errors unless you are pretty experienced with EDK. 

Also, I posted this same question to the embedded processor forum on the Xilinx website, here is the post and response: 

Joe "UltraController and UART" 3/10/04 10:26am 


Article: 71884
Subject: Re: adding real UART to xilinx ultracontroller design.
From: Joe <petrone@eng.fsu.edu>
Date: Tue, 3 Aug 2004 06:55:19 -0700
Links: << >>  << T >>  << A >>
Matt, 

I tried this before with no success. The Amount of changes needed to add a PLB or OPB causes a lot of errors unless you are pretty experienced with EDK. 

Also, I posted this same question to the embedded processor forum on the Xilinx website, here is the post and response: 

Joe "UltraController and UART" 3/10/04 10:26am 

Good luck, 
Joe 


Article: 71885
Subject: Re: adding real UART to xilinx ultracontroller design.
From: Joe <petrone@eng.fsu.edu>
Date: Tue, 3 Aug 2004 06:57:33 -0700
Links: << >>  << T >>  << A >>
Matt, 

I tried this before with no success. The Amount of changes needed to add a PLB or 
OPB causes a lot of errors unless you are pretty experienced with EDK. 

Also, I posted this same question to the embedded processor forum on the Xilinx 
website, here is the post and response: 

Matthew Ouellette "UltraController and UART" 3/10/04 10:26am 

Good luck, 
Joe 


Article: 71886
Subject: Re: adding real UART to xilinx ultracontroller design.
From: Joe <petrone@eng.fsu.edu>
Date: Tue, 3 Aug 2004 07:04:48 -0700
Links: << >>  << T >>  << A >>
Matt, 

I tried this before with no success. The Amount of changes needed to add a PLB or OPB to the Ultracontroller causes a lot of errors unless you are pretty experienced with EDK. 

Also, I posted this same question to the embedded processor forum on the Xilinx website, here is the post and response: 

Matthew Ouellette "UltraController and UART" 3/10/04 10:26am 

Your best bet is probably to create a new project and add the required busses. Try to find a MHS that has the PPC and UART from someone (I'm in a different lab now or I'd send one to you.) Then you will need to create a custom IP core for your logic using the IPIF. 

Good luck, 
Joe 


Article: 71887
Subject: Re: Best tool(s) for filter float->fixed->VHDL flow?
From: tom1@launchbird.com (Tom Hawkins)
Date: 3 Aug 2004 07:27:18 -0700
Links: << >>  << T >>  << A >>
jjohnson@cs.ucf.edu (Mark) wrote in message news:<c88fa005.0408021903.4e75e599@posting.google.com>...
> I've got a minor DSP/comm task to put in an FPGA:
> 
> Complex demod to baseband, CIC+decimate+FIR LPF chain, magnitude
> estimate, some FSK and DPSK data to interpolate, correlate and
> extract, plus other sundry tasks.
> 
> I'd like to model this all in untimed/behavioral floating-point, have
> a quick way to evaluate filtering options (including IIR, varying
> lengths and structures/forms) and quantization effects, with automatic
> conversion to a somewhat optimal fixed-point implementation that a
> tool can automatically write out as VHDL (RTL, not behavioral).
> Parameterizable block diagram entry is a plus. Probes/sinks with FFT
> and time plots and file writes at nodes of interest are also
> desireable. (SUMMARY: design/analyze at high level, let tools do
> dirty, low-level work.)

For architectural exploration, take a look at the new behavioral
synthesis tools coming on-line.  If money is no object, consider
Mentor's CatapultC (was PrecisionC).

CatapultC takes an untimed C model and converts it to RTL.  You guide
the compilation process specifying which for-loops to unroll, which
arrays to make memories, etc.  The process is fast, and you can
quickly compare alternative architectural decisions -- the tool plots
a graph of area vs. performance so you can see which decision fits
with your application.

Other companies in this space include Forte (Cynthesizer), AccelChip,
and Celoxica.  If you can't fork out $100K+, consider SPARK.  It maps
untimed C to RTL.  It's not free (as in open-source) and I don't know
the license restrictions.

  http://mesl.ucsd.edu/spark/


For parametric designs, take a look at Confluence -- a functional
programming language for generating synchronous netlists (outputs
Verilog, VHDL, C).  It's cheap (GPL) and the language was originally
designed for DSP.

  http://www.confluent.org/

Though the process of mapping floating-point to fixed-point is not
automated, you just have to write the conversion algorithm once.  Then
afterwards, when you change coefficient values, precision, the number
of coefficients, or any other parameter, the flow is completely
push-button.

-Tom

Article: 71888
Subject: Instantiation of BUFGMUX
From: Thomas Reinemann <thomas.reinemann@masch-bau.uni-magdeburg.de>
Date: Tue, 03 Aug 2004 16:28:25 +0200
Links: << >>  << T >>  << A >>
Hello,

I have to instantiate a Xilinx BUFGMUX manually (VHDL), since Precision 
Synthesis doesn't infer it in this situation. The signal, which is the 
input for the BUFGMUX, is driven by a clock divider.

The example in
http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/vtex5.html
doesn't work.

How can I make the instantiation, but in such a way, that there is no 
need for special treatment depending on simulation or synthesis.




Tom

Article: 71889
Subject: Re: Clock generator
From: johngalil@hotmail.com (John)
Date: 3 Aug 2004 07:30:15 -0700
Links: << >>  << T >>  << A >>
Thank you Allan, I generated the .vhd code, I will test, hope it will
work.

Yes, it is a baud rate generator. it is 16*115200 Hz requirement of
the uart trans/receiver.

Best regards,
Ahmad.

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<7mcug0t01ocdbj2dibf220d5vk8asu73ce@4ax.com>...
> On 2 Aug 2004 23:17:11 -0700, johngalil@hotmail.com (John) wrote:
> 
> >Dear All,
> >
> >Is it possible to generate 1843200 Hz clock using a 10 MHz clock in
> >vhdl. If yes, would it be possible to give me the algorithm and I will
> >try to implement it. I did a clock divider, but it does work only when
> >the quotient is a power of 2.
> 
> http://fractional-divider.tripod.com/ contains a perl script that
> generates fractional-N dividers in both VHDL and Verilog.
> 
> It used 28 ff for your exact frequency ratio.
> 
> Relaxing the frequency tolerance to 0.1% (this is a baud rate
> generater, right?) reduced the size to 12 ff.
> 
> Regards,
> Allan.

Article: 71890
Subject: Re: DDR or SDR ? Memory controller in FPGA
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 03 Aug 2004 12:08:12 -0400
Links: << >>  << T >>  << A >>
Sylvain Munaut wrote:
> 
> Hi
> 
> > Even more important than avoiding T connections, is keeping them short,
> > very short.  You can even drive a star arrangement if you can keep all
> > traces to about 1 inch (2.5 cm) or so.  The reflections are then a small
> > fraction of the rise time and will not be significant.  Or you can make
> > every memory pin a separate net and use simple series resistors (which
> > can be integrated in some FPGAs) on the outputs.  Point to point drivers
> > are very simple and hard to screw up.
> 
> I'll try to keep as short and matched as I can.
> 
> I was a little worried because in all datasheet/application notes/... they say to simulate with IBIS models. I've tried the HyperLynx demo and that's sure looks a good tool. But I can't afford a 18000$ soft ... (and the demo is VERY limited).

Yes, I feel your pain.  Simulation is a good idea, but there is more
than one way to skin a cat.  A simulation is just a handy way to save
some work, but if you keep your designs very simple and follow the
rules, you won't have any real trouble.  You can even use series
termination with multiple receivers as long as the signal is not a clock
and you have your stubs total no more than an inch.  Using two chips,
you can put them on opposite sides of the board and get nearly no stub
length.  


> > Also, if you are at all concerned about a long life for your product,
> > you should go with DDR.  SDRAM is already on the way down the curve and
> > will only get more expensive in the future (unless we have another bust
> > cycle).  32 bit parts are niche parts like most SRAM, 16 bit parts are
> > more mainstream, but not quite jellybean while the 8 bit parts which are
> > used widely in PCs are fully commodities which will be the low cost per
> > bit of any memory.  You can even get them in extra small packages (which
> > are used for laptops).  I don't know if any of this is a consideration
> > for you.
> 
> I'm interested in "long" life yup ;)
> I was planning to use 16bits parts because 32bits are too rare/expensive/... And 8 bits, you need 4 to make a 32bits bus. That becomes a lot harder to route and get it right.

I don't know that 16 bit chips are or will be hard to buy.  I just know
that they are not as common as the 8 bit chips.  But then we are using
the 16 bit SDRAM chips on a board that we expect to make for at least 5
years!  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 71891
Subject: Re: 1GHz FPGA counters
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 03 Aug 2004 09:21:37 -0700
Links: << >>  << T >>  << A >>
Correct, jogging all the way in a circle around that package is >130 mm.
Jogging in wide circles may be a healthy exercise for humans, but it is not
recommended for timing-critical signals.
Peter Alfke

> 
>> 140 mm is a long distance, almost six inches in Imperial units  :-)
>> With careful lay-out you can avoid errors down to <100 ps, perhaps even 50
>> ps.
>> Peter Alfke
>> 
> 
> it's about the same as the distance around a FF1152 package ;)
> 
> -Lasse
> 
> 


Article: 71892
Subject: Re: SPARTAN-3 VCCAUX supply current
From: "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com>
Date: Tue, 3 Aug 2004 10:24:04 -0700
Links: << >>  << T >>  << A >>

"M.Randelzhofer" <techseller@gmx.de> wrote in message
news:2n8safFtosabU1@uni-berlin.de...
> Hello ng,
>
> what's the expected supply current of spartan-3 VCCAUX 2.5V ?

The expected current on the VCCAUX supply depends on the specific device
used and the application.  As described starting on page 15 of the following
document, the VCCAUX voltage input supplies the Digital Clock Managers
(DCMs), the dedicated configuration pins, the JTAG pins, the LVDS output
drivers, and forms an input reference voltage for some of the I/O standards.
http://www.xilinx.com/bvdocs/publications/ds099-4.pdf

The best method to determine power consumption is the Web Power Tool,
available online at the following link.
http://www.xilinx.com/power

This web-based calculator allows you to enter your expected operating
conditions.  Based on the numbers of functions used, the device size, and
the operating frequency, the Web Power Tool provides an expected typical
power consumption for each supply.

An even more accurate caculator, called XPower, is built into the Xilinx ISE
software.  However, XPower requires a completed FPGA design.

> I saw in the datasheet, that it's quiescent current is in the range of
> vccint.
>
> Is it in general in the range of vccint ?

At quiescent levels, VCCAUX and VCCINT are in the same general ballpark.
However, these are likely different in an operating application.

> Does it depend mainly on the usage of the DCM'S ?

Yes, the DCMs are powered by VCCAUX.

> Is a 150mA regulator sufficient ?

The answer depends on the type of application implemented in the FPGA.  The
Web Power Tool can help you decide.

> Is an analog regulator preferred over a switching type ?

Either works.  However, if you are using DCMs, especially in high
performance applications, be aware that the DCMs are powered by VCCAUX.
Noise on the VCCAUX supply adversely affects jitter on the DCM clock
outputs.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC



Article: 71893
Subject: ISE WebPack and IPs (no CoreGen)Xilinx
From: Nicolas Matringe <matringenicolas001@numeri-cable.fr>
Date: Tue, 03 Aug 2004 19:24:35 +0200
Links: << >>  << T >>  << A >>
Hello all
I have just downloaded the WebPack and am terribly surprised: I can't 
find how to instantiate standard IP cores such as memories. CoreGen 
isn't part of WebPack, so how are users supposed to use memories and so on?

Nicolas


Article: 71894
Subject: Spartan 3 errata and pricing
From: krishk24@gmail.com (Krishna Kumar)
Date: 3 Aug 2004 10:36:51 -0700
Links: << >>  << T >>  << A >>
Hello,
I am trying to choose between a Xilinx XC3S1000 FG456 and XC2V1000
FG456. Listed below is a comparison based on the parameters that I am
looking for:

            XC3S1000 FG456            XC2V1000FG456
  I/Os         333                      324
  GCK           8                        16
  Price      $47(per 100 piece)        >$120 (per 100 piece)

Now there is a vast difference in price between the 2. The user I/Os
are comparable and I think 8 GCK in spartan 3 should suffice. But my
only concern is Spartan 3 is not yet in full production. Xilinx is
manufacturing only "ES" parts which is an abbreviation for Engineering
samples. I hear from the local FAEs that ES may have some errata and
the availability is not guaranteed. What does the errata contain? Does
anybody have any info on the pricing, availability and contents of the
errata? I need to know my devices thoroughly before I can use them in
my design. Any suggestions are welcome.

thanks
Krishna Kumar
DSP System Engineer
Signalogic Inc
Dallas, TX

Article: 71895
Subject: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
From: Gupta <gupg@hotmail.com.NOSPAM>
Date: 03 Aug 2004 10:42:48 -0700
Links: << >>  << T >>  << A >>

Hi

I am new to the newsgroup and the FPGA world.  I am trying to figure
out how I should choose between the various FPGA offerings.  Xilinx
and Altera are clearly the market leaders, but the Flash-based FPGAs
from Actel seem compelling (denser than Xilinx ?), but they seem to be
a generation behind (does that matter ?).  Also, Lattice recently
announced low cost FPGAs with DSP blocks (50 bucks).  Also, I saw on
Lattice's website that they too have Flash based FPGAs.  Does Flash
really have an advantage over SRAM (claim is that Flash is one
transistor versus 6 transistors required for SRAM) ?  

Got any tips on how to evaluate the various offerings ?  I am looking
at about a 1 million gate design, with moderate/easy performance
requirements.  Does this analysis change if I am working on a 500K
gate design ?

Thanks
Sumit

Article: 71896
Subject: FPGA and RS422
From: "Rune Christensen" <rune.christensen@adslhome.dk>
Date: Tue, 3 Aug 2004 19:54:19 +0200
Links: << >>  << T >>  << A >>
Hello

Is it possible to connect a RS422 differential signal directly to a FPGA
instead of using a converter from RS422 to TTL voltage levels?
Would it be possible for a FPGA to create a RS422 signal?

Is there any information about this on the internet?

Thanks
Rune Christensen


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Article: 71897
Subject: Re: SPARTAN-3 VCCAUX supply current
From: "M.Randelzhofer" <techseller@gmx.de>
Date: Tue, 3 Aug 2004 20:42:19 +0200
Links: << >>  << T >>  << A >>
Hello Steve,

thanks for the information.
The power tool is a nice piece of SW, but fully unusable for my purposes.
I want to design a robust evaluation system.
Therefor i need a worst case maximum value for the currents for the
X3S200TQ144 and X3S400TQ144 devices.
It's not the exact value like 845,8765mA and 988,887mA i need for the given
voltages, but the general range.
I expect, there are special test patterns for your semiconductor end tests -
like all FF's toggling or shifting which needs a certain amount of current
on vccint or vccaux.
What's the average current in these 'all chip resources tests' at the
thermal limit ?

Ok, this question is rather weird because of the limit definitions, but i
hope you understand what i mean.
The Xilinx Spartan-2 Starter Kit (an excellent and low priced system) uses a
500mA regulator for the VCCAUX and a 1000mA regulator for VCCINT. Are these
ranges recommended from Xilinx, or a rough estimation of an experienced
designer ?

again thank you very much for your fast response and quality of information.

MIKE



Article: 71898
Subject: Re: SPARTAN-3 VCCAUX supply current
From: "M.Randelzhofer" <techseller@gmx.de>
Date: Tue, 3 Aug 2004 20:44:27 +0200
Links: << >>  << T >>  << A >>
Sorry, i mean the Spartan-3 Starter-Kit in the posting above.

MIKE



Article: 71899
Subject: Re: FPGAs starting with incorrect bitstream !?
From: praveen_yah@yahoo.com (praveen)
Date: 3 Aug 2004 11:45:54 -0700
Links: << >>  << T >>  << A >>
Antti,

In a recent design we came across "configuration initialization
problem"
that sounds similar to what you are noticing. But in our case it is 
a Spartan-IIE device and the failure is incorrect initialization of
the SRL.

In our design we used SRL16E to create a divide by 16 counter.
Essentially
a 16bit circular shift register loaded with 0x0001.
We have a chain of these to a create a 250ms tick from a 66MHz free 
running clock. After the successful configuration we expect the 250ms
tick
to be free running. The 250ms tick works most of the time but it fails
once in a while. We couldn't explain the failure, couldn't solve the
problem.
Fortunately we could work around the problem by replacing SRL based 
counters with FF based counters. Note that SRLs do not have any reset
pin
hence no reset dependancy.

The question I couldn't answer was if there was a corruption in bit
stream,
and FPGA CRC logic didn't catch it, why did failure only affected SRL
INIT
value? Why didn't it affect, say a SLICE configuration? Why didn't
some other
logic in FPGA mis-behave?

here are more details

More details.
- Target FPGA device is XC2S50E-6FT256C
- FPGA configuration mode is Master Serial (M2, M1, M0 == 0,0,0). The
CCLK is driven by FPGA only.
- Serial PROM used is XCF01SVO20
- RTL : Verilog
- Synthesis tool : SynplifyPro 7.5.0
- Xilinx Tool : ISE6.1i, SP3

Typical SRL usage code
------------------------------------------------------------------------------
defparam u_free_tmr0.INIT = 16'h1;
SRL16E u_free_tmr0 (
 .CLK (core_clk_out),
 .A0  (1'b1), .A1  (1'b1), .A2  (1'b1), .A3  (1'b1),
 .CE  (1'b1),
 .D   (free_out15),
 .Q   (free_out15));
------------------------------------------------------------------------------
In our design we have mutiple instantiations of SRL similar to what is
shown above. We also use the UART
macro from Xilinx listed in XAPP223. The macro also uses SRL to
implement a divide by 16.
Source clock to the SRL is from a free running osciallator (66MHz)
present on the board.

I confirmed that code was correctly implemented by checking the init
value of the SRL in fpga_editor

Experiments we carried out

Ex1 : Turn on the power. Ensure FPGA is configured (DONE=1, INIT# =
1). Check whether free running clock from SRL is running. If clock is
running, power cycle else stop.
Result : We saw failures where the SRL in our part of design didn't
oscillate. We also saw instances where the SRL
            in UART macro didn't oscillate. Some times it took 30
tries sometimes 500 tries.

Ex2 : Turn on the power. Pull PROG# pin of FPGA low. Pull PROG# pin of
FPGA high.
         Ensure FPGA is configured (DONE=1, INIT# = 1). Check whether
free running clock from
         SRL is running. If clock is running, reconfigure the FPGA by
toggling PROG#.
Result : We saw failures where the SRL in our part of design didn't
oscillate. We also saw instances where the SRL
            in UART macro didn't oscillate. Some times it took 30
tries sometimes 250 tries.

Ex3 : We replaced the SRL based "divide by 16" counters with FF based
counters in our part of the design. The UART
         macro still contained SRL based divide by 16. Repeat "Ex2".
Result : We saw failures only in the SRL macro of the UART. The divide
by 16 counters implemented using FF never
           had any failures.

The problem is seen on multiple boards.

I'm glad I found someone seeing similar symptoms that we were
struggling with
for couple of weeks.

- praveen


"Antti Lukats" <antti@case2000.com> wrote in message news:<cdfom2$1dd$03$1@news.t-online.com>...
> [snip]
> > >> Xilinx says that the old CRC was not good enough and did not catch all
> > >> errors during configuration !!  But I bet the new one is not much
>  better!
> > >>
> > >> Antti
> > >
> > >  If I read this right, you are saying that read-back does show the
> > >error, and that error persists on many read-backs until re-config ?
> >
> > Good question.  Antti, when you say that "readback" is consistent, are
> > you referring to the MicroBlaze's readback of that one register, or
> > are you saying that you are seeing an error when you perform a
> > bitstream readback?
> >
> > Bob Perlman
> > Cambrian Design Works
> 
> Microblaze starts, i.e. DCM works, BRAMs init ok, etc...
> I press HW reset and RTL revsison registers (hard-wired)
> reads 23.27 as example not 1.21 as it is wired to return.
> this wrong readback 23.27 persists after any number of
> hardware reset (reset to microblaze and all registered logic).
> after reconfing the problem is away. Some other time
> the wrong readback maybe differently wrong but again
> it remains constant until reconfig.
> 
> And yes it looks like there are chances that V2 bitstream
> can be starting even if it had errors during download.
> And yes i would like xilinx to document AutoCRC function ;)
> 
> Antti



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