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Sometimes the smart compile feature is great, but other times... I have a Stratix chip in Quartus II v4sp1. All I did was go into Assignment Editor and change a couple of pins from one I/O standard to another. There were no changes to my RTL code. As expected, it umped through synthesis in a minute. However, I expected the fitter to just take a few minutes since there was no placement or routing changes. Instead, it's taken 2 hours, and it's only at 51%. This is about as long as a full place and route. Why is it doing this!?!?!? DavidArticle: 70726
Jim wrote: > Hi all, > > i need to implement a (D) PLL in a CPLD. > > Purpose is to multiply a frequency of 32KHz to 4,096KHz. > On board PLL's don't work since the freq. is very low > > How do i start? DPLLs ( digital phase locked loops ) have phase jitter, so first step is to decide how much phase jitter you can tolerate @ 4MHz. To keep jitter reasonable, DPLLs need a time granularity well above the reqired Freq out, so you need a faster clock. You may decide an Analog PLL like a HC4046, with the divide in CPLD gives better performance. -jgArticle: 70727
I believe you can prevent the re-route and place by changing the io standards directly in the chipeditor. But that's only for a quick test of course. "David Rogoff" <david@therogoffs.com> wrote in message news:zn6sn1mi.fsf@therogoffs.com... > > Sometimes the smart compile feature is great, but other times... I > have a Stratix chip in Quartus II v4sp1. All I did was go into > Assignment Editor and change a couple of pins from one I/O standard to > another. There were no changes to my RTL code. As expected, it umped > through synthesis in a minute. However, I expected the fitter to just > take a few minutes since there was no placement or routing changes. > Instead, it's taken 2 hours, and it's only at 51%. This is about as > long as a full place and route. Why is it doing this!?!?!? > > DavidArticle: 70728
Please consider contributing to the 3rd Workshop on Application
Specific Processors. Abstracts are due in 1 week, Thurs, July 1.
See the WASP 04 website, http://dna.ucsd.edu/wasp04 for more info.
**************************************************************
Call For Papers
3rd Workshop on Application Specific Processors (WASP 2004)
Held in conjunction with the International Conference on
Hardware/Software Codesign and System Synthesis, (CODES+ISSS),
September 7, 2004, Stockholm, Sweden
Abstract due: July 1, 2004
Submission due: July 8, 2004
Acceptance notification: August 1, 2004
Final version due: August 15, 2004
Topics of interest:
* Domain-specific processors (Network, multimedia, etc.)
* Application-specific hardware accelerators
* Microarchitectural customization techniques
* (Re)configurable processor architectures
* Dynamically reconfigurable processors (Microarchitectural,
Coarse-grained, FPGA, etc.)
* Application-specific processors in System-on-a-chip (SOC)
* Application-specific customizations for low-power
* Compiler techniques for processor customizations
* OS and Middleware support for application-specific processors
Workshop website: http://dna.ucsd.edu/wasp04
************************************************************
Scott Mahlke
WASP 2004 Publicity Chair
Article: 70729Ray Andraka wrote: > > Rickman, > > Not sure where you got this idea. Xilinx reads take ONE clock cycle from > address to data out. In the case of pre-VirtexII, a write cycle copied the > write data to the read outputs as well. In the newer chips you have the choice > of what data comes out the read port during a write cycle. > > rickman wrote: > > > Peter Alfke wrote: > > > > > > Xilinx (Virtex2 or Spartan3) BlockRAM reading while writing: > > > Any write operation also performs a read, and outputs it on the Do output. > > > The user can choose: write before read (= output the data that is being > > > witten), or read before write (=output the previous content that is now > > > being overwritten) or "no change"( keep the old data on the Do lines. > > > > But it still has a two cycle delay from writing to read data out, > > right? So if I want the data that was just written on the next clock > > cycle (like in a stack) I need to use an external register and use > > separate read and write addresses. Correct? You are responding to old messages. This has already been corrected by Peter and others. Thanks anyway. Just FYI, I got confused between an edge clocked register and the data hold latch they have on the output. I am a visual guy and the app note is mainly words which can get me confused sometimes. - Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70730
I got my issues with the rams worked out and I belive I have an inferred design that will work in both Spartan 3 and ACEX chips with few changes. I am trying to compile this design in Quartus II 3.0 and need for the software to use the cascade chain to provide fast bus muxes with lots of inputs. Right now my critical speed path (and one of the LE hogs) is a four input mux which I expect to be able to do in 2*n (where n is the data bus width) LEs. Each bus has a select signal which is gated with all the bits of that bus and then all of the buses are logically OR'd to complete the mux. This OR can be done by the cascade chain if the logic is inverted appropriately. Rather than depend on the software to invert all this for me, I coded the mux as an AND of ORs rather than the normal OR of ANDs. Instead of using the simple structure I am trying to get, it is use short cascades, but not in a regular way to minimize logic and delays. Other than instantiation, is there a good way to "encourage" the Quartus tools to use the cascade chains in a structured way? If I instantiate the cascade backbone, how do I get that to simulate in Modelsim? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 70731
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:RTHCc.4326$NA1.419961@news02.tsnz.net... > Jim wrote: > > > Hi all, > > > > i need to implement a (D) PLL in a CPLD. > > > > Purpose is to multiply a frequency of 32KHz to 4,096KHz. > > On board PLL's don't work since the freq. is very low > > > > How do i start? > > DPLLs ( digital phase locked loops ) have phase jitter, so first > step is to decide how much phase jitter you can tolerate @ 4MHz. > To keep jitter reasonable, DPLLs need a time granularity well > above the reqired Freq out, so you need a faster clock. > You may decide an Analog PLL like a HC4046, with the divide in CPLD > gives better performance. The phase detector could also be implemented in the CPLD, leaving just the VCO. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 70732
> hello, > > I want to build tcp/ip-Stack as an library file. > The stack contains one tcp.hcc-file with the main-function and > and some other macros and functions. The second file is a headerfile > where all the variables are declared and the macro/functions-prototypes > are in it. Its my first time building a library file at all. > 1. I think I have to put the main-function in the file which should > later include the library file (its not allowed to have a main-function > in a library-file, or), is it right??? > 2.I did that, I made a new project which includes the tcp.hcl > the code of the project is only the tcp-mainfunction from the old > tcp.hcc file > 3. No there are a lot of errors, some var. are undeclared and > some are redifined. > > can somebody help me,thanks, It sounds like you are getting multiple definitions, which isn't allowd in C (or HandelC). The approach many people take is to create a "sentinel" in the header file so that it can only be included once. So in your header file tcp.hcc, put #ifndef TCP_HCC #define TCP_HCC /* all the code from the header you wrote */ #endif and that makes sure that if a file in your design includes tcp.hcc twice, it only really gets included once. I hope this helps, regards Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 70733
"Brannon King" <bking@starbridgesystems.com> writes: > It seems to work whether on the pad instance or the buffer instance. What I > can't figure out is how to set the PULLUP/PULLDOWN stuff in EDIF. I end up > running the FPGA editor and turning it on manually after every build. I've > tried What synthesis tool do you use? If you use DC-FPGA or DC you can do set edifout_write_properties_list "PULLUP PULLDOWN" You will most likely add lots of other properties too (LOC, IOSTANDARD, etc.) Then you can use set_attribute to set the property. set_attribute /yourdut/yourbuf PULLUP -type string TRUE Then the property will be exported to the netlist when you do write_file -f edif ... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 70734
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:<K7CCc.77080$2i5.20711@attbi_s52>... > >Jimmy" <mljiang@eee.hku.hk> wrote in message > news:cbei7k$d9i$1@hkueee5.eee.hku.hk... > > Hi, all > > Synthesizer (XST) supports the divisor to be integer power of 2. Then > > how about implementing an operation with the divisor to be 11. > > result <= data / 11; > > thanks. > > Jimmy > > > > > Division by a constant isn't too hard--just multiply by its > eciprocal. -Kevin And constant multiplication can be small and fast 1/11 in binary is: 0.00010111010001011101000..... a = (data >> 4) + (data >> 5) - (data >> 9) + (data >> 10) get you 13 digits (usding three adders) b = a + (a >> 10) gets you 23 digits (using four adders) c = b + (b >> 20) gets you 43 digits (using five adders) and so on.... Kolja SulimmaArticle: 70735
Hi! I have a question related on design flow and use of open source tools like "icarus verilog". How many of designers out there use this tools and why? thanks, SasaArticle: 70736
On Fri, 25 Jun 2004 13:38:43 +0200, "Sasa Bremec" <sasa@i-tech.si> wrote: >Hi! > >I have a question related on design flow and use of open source tools like >"icarus verilog". How many of designers out there use this tools and why? I use it sometimes when I want to use Linux on Apple Mac hardware. (Almost no serious EDA runs on Power PC processors.) Regards, Allan.Article: 70737
Hi Joerg, I've actually managed to compile the xpc4drv on Fedora Core 2 with an adapted Makefile and some editing in the sources, but I've utterly failed to get this damned windrvr6 working. The sources delivered by Xilinx are old, get the new ones at http://www.jungo.com/download/WD621LN.tgz - Jungo says, they are 2.6-enabled. Unfortunately this is not the truth, as using their Makefile doesn't use the 2.6er make-process. I've also created a small Makefile for this module, but on loading it I get a non-descriptive error-message :-P I've also tried their Makefile with some manual work and source-adapting and this isn't working either, same error-message. So until Jungo comes up with an actually working windrvr6 this isn't going so work. Best regards, Alex Joerg Ritter wrote: > Hi, > has anybody sucessfully compiled the kernel modules windrvr/xpc4drvr > under kernel 2.6 ? > The code seems to be not prepaired for kernels >2.5 > > linux_wrappers.c:43: /* only allow 2.0.x 2.2.y and 2.4.z */ > > Is there a newer verion available from xilinx rather than > > ftp://ftp.xilinx.com/pub/swhelp/ise6_updates/linuxdrivers.tar.gzArticle: 70738
I need a large FIFO memory, preferably as 2Mx32bit (150Mhz clock) and I don't want to spend the time and bucks on FPGA+memory to do this. I have a hard time finding this. Is it really that useless? Any clues?Article: 70739
I'd looked into this issue a few times over the last few years. The largest dedicated FIFO's you can find these days are 256Kx36. You usually pay through the nose for them and they usually have excessive lead times. They are manufactured by IDT with generic part number 72T36125. We settled on implementing FIFOs with an FPGA, an SDRAM, SDRAM controller IP, and a bit of custom logic. With this setup, considering what parts are commonly available with short lead times, we wound up with a 512Mx32 FIFO, which was way beyond what we were orginally looking for. The memory situation has gotten to the point where the small specialty FIFOs are very expensive and generalized memory is really, really big, but cheap as borscht. Dwayne Surdu-MillerArticle: 70740
Oops! I got my bit and word totals confused. What we wound up with was a 16Mx32 FIFO, not 512Mx32. My apologies. Dwayne Surdu-MillerArticle: 70741
javodv@yahoo.es (javid) wrote in message news:<c10cd8da.0406240644.748bc803@posting.google.com>...
> Hello,
>
> I would like to know if a two stage syncronizer is implemented in the
> following way:
>
Looks ok, but I didn't try it.
I attached a more generalized example below.
> As you can see I have included the RST signal (in my case an external
> asynchronous Reset signal), is this RST signal needed for the two
> stage synchronizer?. I mean, should I write the two stage synchronizer
> as before or:
I would leave the reset in unless there is
a real good reason not to.
> And another question about Reset and State Machine:
> the RST is coming asynchronously from the outside world. should I use
> also for the RST signal the two stage synchronizer in order to avoid
> glitches?
Yes, if the power-up reset is not already synchronized.
-- Mike Treseler
-------------------------------------------------------------------------------
-- Synchronizer Example Thu Jun 24 11:45:45 2004 Mike Treseler
-- Handles in_len inputs and outputs
-- vsim test_dqdq -do "add wave *; run -all"
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dqdq is
generic (in_len : positive := 4;
pipe_len : positive := 2); -- 2 or 3
-- normally 2 levels of synchronization [dq][dq] Watch for reg dups
-- 3 levels covers synthesis register duplication [dq][dq]-.-[dqa]
-- Provides min of two non-duplicated stages \-[dqb]
port (
clk : in std_ulogic;
rst : in std_ulogic;
raw : in std_logic_vector(in_len-1 downto 0); -- unsychronized
cooked : out std_logic_vector(in_len-1 downto 0) -- sychronized
);
end dqdq;
architecture synth of dqdq is
signal A,B,C,D : std_ulogic;
-- Example of internal synchronized signals for another process
begin
synchronize: process (clk, rst) is
-- purpose: put two d flops in line with input vector
subtype vec is std_logic_vector(raw'range);
variable cooked_v : vec;
type shft is array (1 to pipe_len) of vec;
variable pipe_v: shft;
constant clr_pipe : shft := (pipe_v'range => (vec'range => '0'));
procedure sync_this
( i_arg : in std_logic_vector; -- unsynch input vector
p_arg : inout shft; -- pipeline shifter
o_arg : out std_logic_vector) -- synched output vector
is begin
p_arg := i_arg & p_arg(1 to pipe_len-1); -- shift in i_arg vec
o_arg := p_arg(pipe_v'length); -- output vec off the end
end procedure sync_this;
begin
if rst = '1' then
pipe_v := clr_pipe;
cooked <= clr_pipe(1);
elsif rising_edge(clk) then
sync_this(i_arg => raw, p_arg => pipe_v, o_arg => cooked_v);
cooked <= cooked_v; -- output to port if need be
(A,B,C,D) <= cooked_v; -- normally wire to another process
end if;
end process synchronize;
end synth;
-------------------------------------------------------------------------------
Article: 70742
Hi all,
First of all, I'm a newbie in FPGA, so sorry if my questions are not very
smart... :-)
In a larger design, I try to use a Xilinx BlockRam for a data width
conversion between 2 clocks domains.
I look through the different Xilinx example (xapp131, xapp258, ..). As my
needs was much more simpler I try to make mine (mostly to understand).
During behavioral or post-translate simulation everything is ok. But during
Post-Place & Route Simulation. It doesn't work.
I try 2 write 2 32bits words from one side and to get on the other side a
64bits word.
In my test bench, I write
1st - 0x00000000 and 0x00000001
and the read side I get 0x0000000100000000
2nd - 0x00000002 and 0x00000003
and the read side I get 0x0000000300000002
and so on.
BUT in place and route simulation I have
In my test bench, I write
1st - 0x00000000 and 0x00000001
and the read side I get 0x0000000000000000
2nd - 0x00000002 and 0x00000003
and the read side I get 0x0000000200000001
2nd - 0x00000004 and 0x00000005
and the read side I get 0x0000000400000003
and so on.
Basically, I always miss the first value, as It is not taken into account,
and the "word" are reordered (so with the wrong pair association).
I saw on the newsgroups, that maybe I have to set the WriteEnable _before_
the rising edge, but I don't understand how and why if it's the case ?
I have isolated my problem in the two following file (testbench and
"converter")
Thanks a lot.
Arnaud
Converter
----------------------------------------------------------------------------
----------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;
entity test_fifo is
Port ( clk_wr_in : in std_logic;
clk_rd_in : in std_logic;
bus_in : in std_logic_vector(31 downto 0);
bus_out : out std_logic_vector(63 downto 0);
wr : in std_logic;
rd : in std_logic;
sr : in std_logic);
end test_fifo;
architecture Behavioral of test_fifo is
component bram_w32_r64
port (
addra: IN std_logic_VECTOR(4 downto 0);
addrb: IN std_logic_VECTOR(3 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(31 downto 0);
doutb: OUT std_logic_VECTOR(63 downto 0);
ena: IN std_logic;
enb: IN std_logic;
wea: IN std_logic);
end component;
signal addra: std_logic_VECTOR(4 downto 0);
signal addrb: std_logic_VECTOR(3 downto 0);
signal clk_rd: std_logic;
signal clk_wr: std_logic;
signal rst : std_logic;
begin
gclk1: BUFGP port map (I => clk_rd_in, O => clk_rd);
gclk2: BUFGP port map (I => clk_wr_in, O => clk_wr);
rst <= not sr;
bram : bram_w32_r64
port map (
addra => addra,
addrb => addrb,
clka => clk_wr,
clkb => clk_rd,
dina => bus_in,
doutb => bus_out,
ena => wr,
enb => rst,
wea => '1');
writer: process(sr, clk_wr)
begin
if ( sr = '1' ) then
addra <= (others => '0');
elsif (rising_edge(clk_wr)) then
if ( wr = '1' ) then
addra <= addra + 1 ;
end if;
end if;
end process writer;
reader: process(sr, clk_rd)
begin
if ( sr = '1' ) then
addrb <= (others => '0');
elsif (rising_edge(clk_rd)) then
if (rd = '1') then
addrb <= addrb + 1 ;
end if;
end if;
end process reader;
end Behavioral;
TEST_BENCH
----------------------------------------------------------------------------
----------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY test_fifo_tb IS
END test_fifo_tb;
ARCHITECTURE behavior OF test_fifo_tb IS
COMPONENT test_fifo
PORT(
clk_wr_in : IN std_logic;
clk_rd_in : IN std_logic;
bus_in : IN std_logic_vector(31 downto 0);
bus_out : out std_logic_vector(63 downto 0);
wr : IN std_logic;
rd : IN std_logic;
sr : IN std_logic
);
END COMPONENT;
SIGNAL clk_wr : std_logic := '0';
SIGNAL clk_rd : std_logic := '0';
SIGNAL bus_in : std_logic_vector(31 downto 0):= (others => '0');
SIGNAL bus_out : std_logic_vector(63 downto 0):= (others => '0');
SIGNAL wr : std_logic :='0';
SIGNAL rd : std_logic := '0';
SIGNAL sr : std_logic := '1';
BEGIN
uut: test_fifo PORT MAP(
clk_wr_in => clk_wr,
clk_rd_in => clk_rd,
bus_in => bus_in,
bus_out => bus_out,
wr => wr,
rd => rd,
sr => sr
);
-- *** Test Bench - User Defined Section ***
clk_wr <= not clk_wr after 30 ns / 2;
clk_rd <= not clk_rd after 15 ns / 2;
sr <= transport '0' after 120 ns;
tb : PROCESS
BEGIN
wait; -- will wait forever
END PROCESS;
-- *** End Test Bench - User Defined Section ***
writer: process( clk_wr, sr)
begin
if ( sr ='1' ) then
bus_in <= (others => '1');
elsif (rising_edge(clk_wr)) then
if ( bus_out /= 8 ) then
rd <= '0';
wr <= '1';
bus_in <= bus_in + 1;
else
wr <= '0';
rd <= '1';
end if;
end if;
end process writer;
END;
Article: 70743I'd suggest trying the board in an older PC that has 5-volt PCI slots. It might simply be incompatible with your newer mainboard's 3.3-volt PCI slots. Best regards, Dwayne Surdu-MillerArticle: 70744
David Rogoff <david@therogoffs.com> wrote in message news:<zn6sn1mi.fsf@therogoffs.com>... > Sometimes the smart compile feature is great, but other times... I > have a Stratix chip in Quartus II v4sp1. All I did was go into > Assignment Editor and change a couple of pins from one I/O standard to > another. There were no changes to my RTL code. As expected, it umped > through synthesis in a minute. However, I expected the fitter to just > take a few minutes since there was no placement or routing changes. > Instead, it's taken 2 hours, and it's only at 51%. This is about as > long as a full place and route. Why is it doing this!?!?!? > > David Hi David, You have several options available to speed up your compile time. 1. The first one is using the Chip Editor along with the Resource Property Editor. The Resource Property Editor is used for small ECO type changes of the type that you have described. Details of how to use these tools can be found in the Quartus Handbook. http://www.altera.com/literature/hb/qts/qts_qii53010.pdf 2. The second solution is available from the command line/DOS prompt. You will need to change directory to your project directory. Check that quartus_fit is on your path. Then type in: quartus_fit design_name --io_smart_recompile 3. Incremental fitting might work -- again it depends on if the change in IO standard will force a pin-out change due to the IOs being incompatible with their current bank. Incremental fitting only saves about 25% of the fit time on average though. This command is available from the Processing->Start->Start Incremental Fitting menu in the UI. Hope this helps. Subroto Datta Altera Corp.Article: 70745
Hi! I am new to this news group.I am doing my project work in Xilinx(ISE 5.2).I use Modelsim 5.6e for simulations. My design is in VHDL. The simulations for Behavioral and Post-Translate are coming as expected.But Modelsim is showing error when I do Post-Map simulations. Name of my entity is strem_entity and testbench is test_bench. ---------------------------------------------------- Modelsim is giving the following error: ---------------------------------------------------- # ** Error: (vsim-SDF-3250) stream_entity_map.sdf(0): Failed to find INSTANCE '/UUT'. # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./test_bench.mdo PAUSED at line 10. ------------------------------------------------------- When I open and see test_bench.mdo in note pad,it has following contents: ------------------------------------------------------------------------- ## NOTE: Do not edit this file. ## Auto generated by Project Navigator for VHDL Post-Map Simulation ## vlib work ## Compile Post-Map Model for Module streamcompression vcom -just e -87 -explicit -work work stream_entity_map.vhd vcom -skip e -87 -explicit -work work stream_entity_map.vhd vcom -just e -93 -explicit -work work test_bench.vhd vcom -skip e -93 -explicit -work work test_bench.vhd vsim -t 1ps -sdfmax /UUT=stream_entity_map.sdf -lib work testbench do test_bench.udo view wave add wave * view structure view signals view process run 0ps ## End -------------------------------------------------------------- I don't have a instance by name UUT in my design.I think that is created by project navigator.Could any one help me regarding this.I am not able to understan why is modelsim giving the message.It would you be great if any one can help me to over come this problem. Thank you, -KaviArticle: 70746
Remember, all BlockRAM operations are synchronous, activated by the clock edge (your choice of clock polarity). That means all inputs must be there at least a set-up time before that clock edge. "All" means: Address, Data, Write Enable, and ENable. Peter Alfke, Xilinx Applications > From: "Arnaud" <arnaud@trisky.com> > Organization: Guest of ProXad - France > Newsgroups: comp.arch.fpga,comp.lang.vhdl > Date: Fri, 25 Jun 2004 22:11:03 +0200 > Subject: Using a BlockRam in an async FIFO for bus width conversion ? > > Hi all, > First of all, I'm a newbie in FPGA, so sorry if my questions are not very > smart... :-) > In a larger design, I try to use a Xilinx BlockRam for a data width > conversion between 2 clocks domains. > I look through the different Xilinx example (xapp131, xapp258, ..). As my > needs was much more simpler I try to make mine (mostly to understand). > > During behavioral or post-translate simulation everything is ok. But during > Post-Place & Route Simulation. It doesn't work. > I try 2 write 2 32bits words from one side and to get on the other side a > 64bits word. > In my test bench, I write > 1st - 0x00000000 and 0x00000001 > and the read side I get 0x0000000100000000 > 2nd - 0x00000002 and 0x00000003 > and the read side I get 0x0000000300000002 > and so on. > > BUT in place and route simulation I have > In my test bench, I write > 1st - 0x00000000 and 0x00000001 > and the read side I get 0x0000000000000000 > 2nd - 0x00000002 and 0x00000003 > and the read side I get 0x0000000200000001 > 2nd - 0x00000004 and 0x00000005 > and the read side I get 0x0000000400000003 > and so on. > > > Basically, I always miss the first value, as It is not taken into account, > and the "word" are reordered (so with the wrong pair association). > > I saw on the newsgroups, that maybe I have to set the WriteEnable _before_ > the rising edge, but I don't understand how and why if it's the case ? > > I have isolated my problem in the two following file (testbench and > "converter") > > Thanks a lot. > > Arnaud > > > > Converter > ---------------------------------------------------------------------------- > ---------------------------- > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > -- Uncomment the following lines to use the declarations that are > -- provided for instantiating Xilinx primitive components. > library UNISIM; > use UNISIM.VComponents.all; > > entity test_fifo is > Port ( clk_wr_in : in std_logic; > clk_rd_in : in std_logic; > bus_in : in std_logic_vector(31 downto 0); > bus_out : out std_logic_vector(63 downto 0); > wr : in std_logic; > rd : in std_logic; > sr : in std_logic); > end test_fifo; > > architecture Behavioral of test_fifo is > > component bram_w32_r64 > port ( > addra: IN std_logic_VECTOR(4 downto 0); > addrb: IN std_logic_VECTOR(3 downto 0); > clka: IN std_logic; > clkb: IN std_logic; > dina: IN std_logic_VECTOR(31 downto 0); > doutb: OUT std_logic_VECTOR(63 downto 0); > ena: IN std_logic; > enb: IN std_logic; > wea: IN std_logic); > end component; > > > signal addra: std_logic_VECTOR(4 downto 0); > signal addrb: std_logic_VECTOR(3 downto 0); > > > > signal clk_rd: std_logic; > signal clk_wr: std_logic; > > signal rst : std_logic; > > begin > > > gclk1: BUFGP port map (I => clk_rd_in, O => clk_rd); > gclk2: BUFGP port map (I => clk_wr_in, O => clk_wr); > > rst <= not sr; > > bram : bram_w32_r64 > port map ( > addra => addra, > addrb => addrb, > clka => clk_wr, > clkb => clk_rd, > dina => bus_in, > doutb => bus_out, > ena => wr, > enb => rst, > wea => '1'); > > > writer: process(sr, clk_wr) > begin > if ( sr = '1' ) then > > addra <= (others => '0'); > > elsif (rising_edge(clk_wr)) then > > if ( wr = '1' ) then > addra <= addra + 1 ; > end if; > > end if; > > end process writer; > > > > reader: process(sr, clk_rd) > begin > if ( sr = '1' ) then > > addrb <= (others => '0'); > > elsif (rising_edge(clk_rd)) then > if (rd = '1') then > addrb <= addrb + 1 ; > end if; > > end if; > > end process reader; > > end Behavioral; > > > TEST_BENCH > ---------------------------------------------------------------------------- > ---------------------------- > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > USE ieee.numeric_std.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > ENTITY test_fifo_tb IS > END test_fifo_tb; > > ARCHITECTURE behavior OF test_fifo_tb IS > > COMPONENT test_fifo > PORT( > clk_wr_in : IN std_logic; > clk_rd_in : IN std_logic; > bus_in : IN std_logic_vector(31 downto 0); > bus_out : out std_logic_vector(63 downto 0); > wr : IN std_logic; > rd : IN std_logic; > sr : IN std_logic > ); > END COMPONENT; > > SIGNAL clk_wr : std_logic := '0'; > SIGNAL clk_rd : std_logic := '0'; > SIGNAL bus_in : std_logic_vector(31 downto 0):= (others => '0'); > SIGNAL bus_out : std_logic_vector(63 downto 0):= (others => '0'); > SIGNAL wr : std_logic :='0'; > SIGNAL rd : std_logic := '0'; > SIGNAL sr : std_logic := '1'; > > BEGIN > > uut: test_fifo PORT MAP( > clk_wr_in => clk_wr, > clk_rd_in => clk_rd, > bus_in => bus_in, > bus_out => bus_out, > wr => wr, > rd => rd, > sr => sr > ); > > > -- *** Test Bench - User Defined Section *** > > clk_wr <= not clk_wr after 30 ns / 2; > clk_rd <= not clk_rd after 15 ns / 2; > sr <= transport '0' after 120 ns; > > tb : PROCESS > BEGIN > wait; -- will wait forever > END PROCESS; > -- *** End Test Bench - User Defined Section *** > > writer: process( clk_wr, sr) > begin > > if ( sr ='1' ) then > > bus_in <= (others => '1'); > > elsif (rising_edge(clk_wr)) then > > if ( bus_out /= 8 ) then > rd <= '0'; > wr <= '1'; > bus_in <= bus_in + 1; > else > wr <= '0'; > rd <= '1'; > end if; > > end if; > > end process writer; > END; > > > >Article: 70747
Hi,
i'm trying to use a RocketIO Infiniband connection on a Virtex2-Pro (XC2VP7
in a ML-300 board) to send
data from one transceiver to another. However the data is usually not
received correctly when sending it over
the cable (a 2.5 Gbps Infiniband cable), unless the cable is twisted in a
certain way. In serial loopback mode
the transmission works just fine.
Could the cable be broken or am I doing something wrong in the code?
Thanks
Alex
architecture arch of bert is
signal brefclk, usrclk, usrclk2, rst_gt, lock, configout, configout2,
rxcommadet, rxrealign, rxrecclk, txbuferr : std_logic;
signal txcharisk, rxchariscomma, rxcharisk, rxdisperr, rxnotintable,
rxrundisp, txkerr, txrundisp : std_logic_vector(0 downto 0);
signal rxbufstatus, rxlossofsync : std_logic_vector(1 downto 0);
signal rxclkcorcnt : std_logic_vector(2 downto 0);
signal rxdata_internal, txdata_internal, rxpattern, txpattern :
std_logic_vector(7 downto 0);
begin
rxdata <= rxdata_internal;
txdata <= txdata_internal;
transmit : process(usrclk)
variable count : integer := 0;
begin
if (rising_edge(usrclk)) then
if (count < 1000) then
txcharisk <= "1";
txdata_internal <= "00111100"; -- send comma
count := count + 1;
else
txcharisk <= "0";
txdata_internal <= "10101010"; -- send data
count := count + 1;
if (count = 2000) then
count := 0;
end if;
end if;
end if;
end process;
process(brefclk)
variable cnt : integer := 0;
begin
if (rising_edge(brefclk)) then
if (cnt >= 100) then
reset <= '0';
else
cnt := cnt + 1;
reset <= '1';
end if;
end if;
end process;
U_IBUFGDS: IBUFGDS_LVDS_25
port map (
I => clk_p,
IB => clk_n,
O => brefclk
);
Inst_infiniband_one_byte_tx : infiniband_one_byte_tx PORT MAP(
CONFIGENABLE => '0',
CONFIGIN => '0',
POWERDOWN => '0',
REFCLKSEL => '0',
BREFCLK => brefclk,
BREFCLK2 => '0',
RXUSRCLK => usrclk,
RXUSRCLK2 => usrclk2,
TXCHARDISPMODE => "0",
TXCHARDISPVAL => "0",
TXCHARISK => txcharisk,
TXDATA => txdata_internal,
TXINHIBIT => '0',
TXPOLARITY => '0',
TXRESET => rst_gt,
TXUSRCLK => usrclk,
TXUSRCLK2 => usrclk2,
CONFIGOUT => configout,
TXBUFERR => txbuferr,
TXKERR => txkerr,
TXN => txn,
TXP => txp,
TXRUNDISP => txrundisp
);
Inst_infiniband_one_byte_rx : infiniband_one_byte PORT MAP(
CONFIGENABLE => '0',
CONFIGIN => '0',
ENMCOMMAALIGN => '1',
ENPCOMMAALIGN => '1',
POWERDOWN => '0',
REFCLKSEL => '0',
BREFCLK => brefclk,
BREFCLK2 => '0',
RXN => rxn,
RXP => rxp,
RXPOLARITY => '0',
RXRESET => rst_gt,
RXUSRCLK => usrclk,
RXUSRCLK2 => usrclk2,
TXUSRCLK => usrclk,
TXUSRCLK2 => usrclk2,
CONFIGOUT => configout2,
RXBUFSTATUS => rxbufstatus,
RXCHARISCOMMA => rxchariscomma,
RXCHARISK => rxcharisk,
RXCLKCORCNT => rxclkcorcnt,
RXCOMMADET => rxcommadet,
RXDATA => rxdata_internal,
RXDISPERR => rxdisperr,
RXLOSSOFSYNC => rxlossofsync,
RXNOTINTABLE => rxnotintable,
RXREALIGN => rxrealign,
RXRECCLK => rxrecclk,
RXRUNDISP => rxrundisp
);
one_byte_clk_inst : one_byte_clk_fullrate
port map(
refclkin => brefclk,
rst => reset,
usrclk_m => usrclk,
usrclk2_m => usrclk2,
lock => lock
);
gt_reset_inst: gt_reset
port map(
usrclk2_m => usrclk2,
dcm_locked => lock,
rst => rst_gt
);
end architecture;
Article: 70748Others have suggested putting attributes or instantiating the PULLx in code; have you tried putting the property in the constraints file? JTW "Brannon King" <bking@starbridgesystems.com> wrote in message news:cbevfv$qpi@dispatch.concentric.net... > This line in EDIF works to change the IOSTANDARD: > > (property IOSTANDARD (string "LVCMOS25")) > > It seems to work whether on the pad instance or the buffer instance. What I > can't figure out is how to set the PULLUP/PULLDOWN stuff in EDIF. I end up > running the FPGA editor and turning it on manually after every build. I've > tried > > (property PULLUP (string "TRUE")) > and > (property PULLUP (string "YES")) > > on both the pad and the buffer but it seems that the tools entirely ignore > it. Any ideas? > > -- > Prepend a 'b' to email me. Thanks. > >Article: 70749
Dwayne Surdu-Miller <miller@sedsystems.nospam.ca> wrote: : I'd suggest trying the board in an older PC that has 5-volt PCI slots. : It might simply be incompatible with your newer mainboard's 3.3-volt PCI : slots. I found several boards incompatible the other way round: Indicating an "universal board" by having to slots in the connector row, but not running in a boards that only supply 5 Volt. I'm glad, that I have a soldering iron and low drop 3.3V regulators :-) Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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