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Messages from 70600

Article: 70600
Subject: Re: RAM in Altera EABs and Xilinx Block Rams
From: "John_H" <johnhandwork@mail.com>
Date: Mon, 21 Jun 2004 22:22:54 GMT
Links: << >>  << T >>  << A >>

"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:40D74C3A.E31766EC@yahoo.com...
     [snip]
> Using the single port interface it appears to me that the address and
> control signals are registered.  Looking at the timing diagram for the
> WRITE_FIRST option, I see that the data output changes with one clock
> delay.  So can I consider the register to be on the input side (address,
> control) with the read data output using no register?  I belive that
> will work for a stack.  When data is being pushed, the incremented
> address is set up and the write is clocked in, while the data output is
> steady until the clock edge (old top of stack).  Following the clock
> edge, the data written will be presented on the output (new top of
> stack).  To pop the stack, the address is decremented and a read is done
> with the new data available following the clock edge (new top of
> stack).  A write (pop and push) is done by not changing the address and
> registering a new write with the read data changing after the clock
> edge.
>
> Will the single port WRITE_FIRST ram mode work this way?

     [snip]

The "write (pop and push)" is a little confusing, you may need to elaborate
that for my own edification.

For WRITE_FIRST mode, when you push a value to the top of stack, that
value - the top of stack - will be sitting on the output after the one clock
edge, ready to be used *immediately* for a POP value in the new cycle.  With
the POP command that uses the top of stack value which is waiting on the
read port, the address needs be decremented such that the *next* cycle will
have the *new* top of stack value ready for a new POP command.  If you have
a PUSH before the POP, the address is incremented for the write during the
PUSH cycle such that the clock edge will have the new top of stack ready for
a next-cycle POP.  It's because the WRITE_FIRST makes the most-recently
written value available on the read port that the stack can work well.

It's the address that needs to be manipulated combinatorially before the
clock edge for the PUSH or POP to have the value ready for POP access
whenever the POP comes up.  The setup and routing for the address is small
enough that the combinatorial delay before the BlockRAM still gives
excellent timing.



Article: 70601
Subject: Re: Interface Bidir IO datalines to dualport RAM within FPGA - URGENT
From: Paulo Dutra <paulo.dutra@NOSPAM.com>
Date: Mon, 21 Jun 2004 17:08:22 -0700
Links: << >>  << T >>  << A >>
I'm assuming a synthesis tool cannot work with the 'process'
block as you have it coded. Otherwise, you may find support
in comp.lang.vhdl forum.

You should describe the registered input path as one
process, the registered output path as another, and the
tristate as a continous assignment.

 

-- Registered Input path
process(ebmclk)
begin
if (ebmclk'event and ebmclk='1') then
   datain <= ebmdat;
end if;

-- Registered Output path with tri-state
process(ebmclk)
begin
if (ebmclk'event and ebmclk='1') then
   dataout_reg <= dataout;
end if;

ebmdat <= dataout_reg when enable = '1' else (others => 'Z') ;


> process(ebmclk)
> begin
> 
> if(ebmclk='1' and ebmclk'event)then  -- THIS IS WHERE THE SWAPPING
> HAPPENS
> 	if(ebmnwt = '0')then         -- ebmnwt is active low signal
> 	datain <= ebmdat;
> 	ebmdat <= (others =>'Z');
> 	else
> 	ebmdat <= dataout;
> 	end if;
> end if;

-- 
/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
\ \ `  Xilinx                              hotline@xilinx.com
/ /    2100 Logic Drive                    http://www.xilinx.com
\_\/.\ San Jose, California 95124-3450 USA


Article: 70602
Subject: Re: Is there a verilog version of PicoBlaze?
From: Ray Andraka <ray@andraka.com>
Date: Mon, 21 Jun 2004 20:19:19 -0400
Links: << >>  << T >>  << A >>
I haven't used picoblaze, so take my comment accordingly:  If picoblaze is placed in the source code using generates, it may not be
possible to do it in verilog and retain the placement as well as the parameterization.  If using synplify, you can compile the VHDL with
the mapped output to verilog turned on to get a structural verilog model that you can use for simulation.  Be aware that SRL16's may not
be initialized properly though (I don't know if Synplicity fixed that bug in 7.5.1).

Allan Herriman wrote:

> On 18 Jun 2004 14:33:28 -0700, henk@mediatronix.com (Henk van Kampen)
> wrote:
>
> >Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<f8f5d09c1bhectj9dm3qtv1e771tnug1j7@4ax.com>...
> >> This doesn't help the OP though, as the core itself is written in
> >> VHDL.  Steve, would there be any problem if a third party (e.g. me)
> >> were to publish a behavioural Verilog description of picoblaze[123]?
> >
> >Allan:
> >The Picoblaze cores are, although VHDL, just instantiations of LUTS
> >and FF's. So a straight translation should be possible.
>
> Possible, yes, but would it be frowned upon by Xilinx?
>
> Regards,
> Allan.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 70603
Subject: Re: RAM in Altera EABs and Xilinx Block Rams
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 21 Jun 2004 22:46:05 -0400
Links: << >>  << T >>  << A >>
John_H wrote:
> 
> The "write (pop and push)" is a little confusing, you may need to elaborate
> that for my own edification.

Push - write to location at incremented stack pointer, update register
to new data.
Pop - read location at decremented stack pointer, update register to
data read.
Write - write to location at stack pointer, update register to new data. 
write is used when an instruction modifies the top of stack without
popping. 

> For WRITE_FIRST mode, when you push a value to the top of stack, that
> value - the top of stack - will be sitting on the output after the one clock
> edge, ready to be used *immediately* for a POP value in the new cycle.  With
> the POP command that uses the top of stack value which is waiting on the
> read port, the address needs be decremented such that the *next* cycle will
> have the *new* top of stack value ready for a new POP command.  If you have
> a PUSH before the POP, the address is incremented for the write during the
> PUSH cycle such that the clock edge will have the new top of stack ready for
> a next-cycle POP.  It's because the WRITE_FIRST makes the most-recently
> written value available on the read port that the stack can work well.
> 
> It's the address that needs to be manipulated combinatorially before the
> clock edge for the PUSH or POP to have the value ready for POP access
> whenever the POP comes up.  The setup and routing for the address is small
> enough that the combinatorial delay before the BlockRAM still gives
> excellent timing.

I understand about the address.  I was not certain about the read
timing.  The data sheet talks about output latches, but now I realize
they mean transparent latches and the registers are all on the input
side. 

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 70604
Subject: New: read/write to D2SB fpga
From: "Phil Moore" <pwmpn2@umr.edu>
Date: Mon, 21 Jun 2004 20:07:23 -0700
Links: << >>  << T >>  << A >>
Hello, 

I am new to the whole Xilinx software package and I have a 
D2SB fpga board with the Spartan IIE fpga its the 2S200E 
chip pq208 or whatever that means. Also, I have the fpga 
setup to a digital I/O, DIO4. 
Well, what I'm am trying to do is to read and write numbers to the fpga. 

1.) Do I have to read and write binary numbers to different 
    addresses or can I read and write base 10 numbers to the fpga's memory? 
2.) How do I read/write to the fpga? 
3.) Do I assign the GCLK pin of the fpga to the ram symbols clock pin? 


Article: 70605
Subject: Exponential Function
From: "Phil Moore" <pwmpn2@umr.edu>
Date: Mon, 21 Jun 2004 20:12:00 -0700
Links: << >>  << T >>  << A >>
Hello, 

1.) I was wondering if there was any way that I could perform 
    exponential operations on numbers that are stored in memory! 
2.) How do I use Coregen to perform addition and multiplication 
    to numbers stored in memory in the fpga, or should I use Coregen? 


Article: 70606
Subject: Neural Network on fpga
From: "Phil Moore" <pwmpn2@umr.edu>
Date: Mon, 21 Jun 2004 20:15:54 -0700
Links: << >>  << T >>  << A >>
I'm new to the whole Xilinx software package, and my professor 
wanted me to have a simple design of a 1x1x1 feed forward neural 
network done by July 24, 2004.  So I was wondering if anyone knows 
whats the best way about doing this?(Verilog, VHDL, Schematic, other)

I have to be able to impliment an exponential function, I have to 
multiply, I have to add, and I have to read/write numbers to memory.  
Plus I have to come up with random numbers.



Article: 70607
Subject: Re: Spartan/SpartanXL Device Selection
From: t_naimesh@rediffmail.com (Naimesh)
Date: 21 Jun 2004 20:35:55 -0700
Links: << >>  << T >>  << A >>
Is it possible to interface both CMOS and TTL devices to a 3.3 V
device? This is because I have to replaced a SOC on the alreay
designed board and dont want to change the design too much.

Article: 70608
Subject: Re: CPLD mistery. Help.... reHelp.
From: hmurray@suespammers.org (Hal Murray)
Date: Mon, 21 Jun 2004 22:45:16 -0500
Links: << >>  << T >>  << A >>
>Would somebody please let me know what would be your
>usual way of writing the VHDL to make an output port out of an 8bit bus?
>with ("address"(=something) and "data" bus and "write" signals only).

I think the important decision is latch vs edge-triggered.

I think the problem you described expects a latch.  The hardware
and software in most CPLDs and FPGAs prefer edge-triggered FFs.

Can you turn your problem into something that works well with
edge-triggered FFs?  Either using one edge of your write signal
to do the work, or using another clock (which you didn't mention)
to do the work and using write and address signals to decided
what to do on each clock cycle.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 70609
Subject: Initializing data in EAB ram
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 22 Jun 2004 02:13:20 -0400
Links: << >>  << T >>  << A >>
I am using an EAB as a RAM for program storage for an MCU in an Altera
ACEX FPGA.  But I can't seem to find info on how to initialize the RAM. 
I will at least need a boot strap program to read an external Flash into
the RAM.  I found information about creating MIF files and RIF files. 
But they don't say much about how they get used.  Can anyone give me the
details?  I assume this initialization data goes into the bit stream
using the tools, no?  Is there a way to initialize the RAM in a VHDL
simulation other than to use the variable initialization of VHDL?  That
seems very messy.  

If the EABs can not be initialized, I guess I will have to provide an
external means of loading the RAM after the chip has been configured.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 70610
Subject: system verilog
From: mamta.chalana@st.com (mamtachalana)
Date: 21 Jun 2004 23:37:40 -0700
Links: << >>  << T >>  << A >>
i want to use system verilog for system modelling,kindy tellme how can
i use that and how can i write code
suppose for example i want to make model of and gate with test benches
how do i compile my code
which compiler is required?
tell me the whole details
mamta

Article: 70611
Subject: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
From: hmurray@suespammers.org (Hal Murray)
Date: Tue, 22 Jun 2004 01:55:20 -0500
Links: << >>  << T >>  << A >>
>Makefiles/Perl/CSH/etc. are great at times for FPGA implementation, 
>especially when you are doing something really unique with the way you 
>are running the tools but if anyone wants to run the Xilinx tools from 
>command-line, the easiest way is using xflow.  Xflow is a single command 
>that can run the Xilinx tools from HDL code to bitstream and most 
>everything in between including simulation netlisting. ...

There are two parts to makefiles.  One is the sequence of commands
needed to recreate something.  The other is that is collects all
the parameters/options/flags in one place.  Most software geeks
consider the makefile to be a source file and include it with the
other source files in some sort of source-code control system.

Does xflow (and friends) have a single file where that sort of info
is collected?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 70612
Subject: Re: XST: Inferring dual-port RAM from VHDL with BlockRAM
From: pmihail@gmx.net (Acciduzzu)
Date: 22 Jun 2004 00:26:35 -0700
Links: << >>  << T >>  << A >>
Yes, you were right! Actually I had done the same mod to the code
since I came to the same conclusion in the mean time. The new RAM
module has now a boolean generic which selects between the two types
of sync.

Thanks.

Article: 70613
Subject: JTAG - XC2S200E-PQ208
From: "Oleg Slonsky" <oleg@uniirt.com.ua>
Date: Tue, 22 Jun 2004 10:26:55 +0300
Links: << >>  << T >>  << A >>
Dear Sir/ Madame,



We have the following problem and we hope you could help us.



On the printed board, produced by our Institute, we have installed the
microchip XC2S200E-PQ208. In order to download our project we have installed
WebPack 6.2i and connected to XC2S200E-PQ208 via port JTAG by Parallel Cable
III.

In the program IMACT in the microchips autodetection mode this microchip was
detected as XCV200E with identification 10A1C093 .

         What is wrong? Whether the microchip is nor working correctly or
software is not correct? Or any other problem?

What is the identification of microchip XC2S200E-PQ208?



We will greatly appreciate any help of you !



With respect and the best wishes,

Oleg Slonsky.



Article: 70614
Subject: Unused signals in Modelsim
From: ALuPin@web.de (ALuPin)
Date: 22 Jun 2004 02:09:04 -0700
Links: << >>  << T >>  << A >>
Hi newsgroup users,

maybe you can help me on the following question:

Does Modelsim remove registered signals which are unused or not
connected to output pins?
Is there a possibility to avoid this without using output pins?

Kind regards

Article: 70615
Subject: Re: Xilinx XST synthesis removes input pin even though it's LOCed
From: "John Adair" <newsreply@loseinspace.co.uk>
Date: Tue, 22 Jun 2004 10:12:12 +0100
Links: << >>  << T >>  << A >>
I would check that the register isn't being removed. A synthesiser will tend
to remove anything that it thinks unused or unconnected.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk

This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.
"Matt Dykes" <mattdykes@earthlink.net> wrote in message
news:8a89c2c3.0406210453.5fd2323@posting.google.com...
> Frank Benoit <nospam@xyz.com> wrote in message
news:<pan.2004.06.19.20.15.14.179200@xyz.com>...
> > > Have a look at the SAVE NET FLAG constraint in the cgd.pdf
documentation.
> >
> > http://toolbox.xilinx.com/docsan/xilinx5/pdf/docs/cgd/cgd.pdf
>
> Using LOC and SAVE NET FLAG with no results.  The PARer gives the
> warnings:
> "logical net on "signal" has no load" and
> "Attribute LOC on "signal" is on the wrong type of object."
>
> Then looking at the project.pad_txt file, "signal" does not show up.
>
> I thought about using the dummy function, but the inputs are just
> discrete interrupts from outside that update a register that gets
> read/reset at some later time.  What better 'dummy' funtion?  I can
> see how it could get optimized out, but those inputs are needed
> whether XST thinks they are or not.
>
> Reading the docs leads me to believe the SAVE NET FLAG should do the
> job, but.....  Thanks again for the suggestions.  Knowing where to
> find that doc is worth the post!



Article: 70616
Subject: Synthesis of loops
From: ALuPin@web.de (ALuPin)
Date: 22 Jun 2004 02:15:34 -0700
Links: << >>  << T >>  << A >>
Hi,

is the following CAM-implementation 
synthezisable? How does a synthesis tool handle the for-loop
in real hardware?

http://www.geocities.com/deepakgeorge2000/cam.htm

Article: 70617
Subject: Re: JTAG - XC2S200E-PQ208
From: Amontec Team <laurent.gauch@amontecDELETEALLCAPS.com>
Date: Tue, 22 Jun 2004 11:30:55 +0200
Links: << >>  << T >>  << A >>
Oleg Slonsky wrote:
> Dear Sir/ Madame,
> 
> 
> 
> We have the following problem and we hope you could help us.
> 
> 
> 
> On the printed board, produced by our Institute, we have installed the
> microchip XC2S200E-PQ208. In order to download our project we have installed
> WebPack 6.2i and connected to XC2S200E-PQ208 via port JTAG by Parallel Cable
> III.
> 
> In the program IMACT in the microchips autodetection mode this microchip was
> detected as XCV200E with identification 10A1C093 .
> 
>          What is wrong? Whether the microchip is nor working correctly or
> software is not correct? Or any other problem?
> 
> What is the identification of microchip XC2S200E-PQ208?
> 
> 
> 
> We will greatly appreciate any help of you !
> 
> 
> 
> With respect and the best wishes,
> 
> Oleg Slonsky.
> 
> 
use service pack 3 of webpack 6.2i -> would be better !

Laurent
www.amontec.com

Article: 70618
Subject: Re: New: read/write to D2SB fpga
From: Joerg Ritter <ritter@informatik.uni-halle.de>
Date: Tue, 22 Jun 2004 11:48:44 +0200
Links: << >>  << T >>  << A >>
Phil Moore schrieb:
> Hello,
> 
> I am new to the whole Xilinx software package and I have a D2SB fpga 
> board with the Spartan IIE fpga its the 2S200E chip pq208 or whatever 
> that means. Also, I have the fpga setup to a digital I/O, DIO4.
> Well, what I'm am trying to do is to read and write numbers to the fpga.
Which interface you are "reading" from ?
There are some switches and buttons, four 7 segment displays, a simple 
vga connector only.

> 1.) Do I have to read and write binary numbers to different addresses or 
> can I read and write base 10 numbers to the fpga's memory?
???
> 2.) How do I read/write to the fpga?
???
> 3.) Do I assign the GCLK pin of the fpga to the ram symbols clock pin?
joerg

Article: 70619
Subject: Re: JTAG - XC2S200E-PQ208
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Tue, 22 Jun 2004 11:20:06 GMT
Links: << >>  << T >>  << A >>
On a sunny day (Tue, 22 Jun 2004 11:17:41 -0700) it happened "Antti Lukats"
<antti@case2000.com> wrote in <cb8tc5$pbt$05$1@news.t-online.com>:

>"Oleg Slonsky" <oleg@uniirt.com.ua> wrote in message
>news:cb8n20$nt$1@toster.Te.NeT.UA...
>> Dear Sir/ Madame,
>>
>> We have the following problem and we hope you could help us.
>
>[snip]
>...we have XC2S200 ...
>
>> In the program IMACT in the microchips autodetection mode this microchip
>was
>> detected as XCV200E with identification 10A1C093 .
>
>xilinx (sw) is wrong! simply disregard this message!
>
>xilinx.openchip.org
On that site it says to search for XAP694.
You need to search for XAPP694 however.
JP

Article: 70620
Subject: Re: CPLD mistery. Help.... reHelp.
From: peter.hermansson@sts.saab.se (Peter Hermansson)
Date: 22 Jun 2004 04:35:09 -0700
Links: << >>  << T >>  << A >>
"lc" <cupido@REMOVEmail.ua.pt> wrote in message news:<newscache$gvpnzh$ys6$1@newsfront4.netvisao.pt>...
> Many thanks for the tips, both direct and via the news group.
> 
> Not much of a progress understanding what is going on.
> Replying to some of the comments I've received I can tell:
> 
> - "octnr" was added in the sensitivity list but no effect.
> - a full MUX was done on the input (save resources but
> that part was working ok already)
> 
> - The fitter produces a quite a different thing in the two situations
> it seems that to bring this signal out of the CPLD changes a lot of things.
> - Used Quartus II instead and it doesn't work with or without testpoint.
> it behaves the same as MAX+II without testpoint.
> 
> - doesn't seem to be an electrical as all other bus operations work
> and most important of all, The SIMULATION produces the same
> strange behavior, so it is something I'm doing or the compiler/fitter
> doesn't like it ... but what ?!
> 
> 
> Would somebody please let me know what would be your
> usual way of writing the VHDL to make an output port out of an 8bit bus?
> with ("address"(=something) and "data" bus and "write" signals only).
> 
> Maybe I'm doing it all wrong.
> Many Thanks.
> 
> Luis Cupido.

Hi,

I have used latches to implement output ports in a couple of designs,
without problems. Latches are a deviation from orthodox synchronous
design but they are "cheaper" than flip-flops in some
architectures....

I would suggest that you check the margins between address/data and
the write control line from the CPU. Its essential to have sufficient
setup and hold time. Probing the internal strobe will increase the
loading on the net which may be the difference between a working and
not working design, if margins are to small. A very good demonstration
of the so called "probing effect".

/Peter

Article: 70621
Subject: Re: CPLD mistery. Problem Found... and is an interesting one !
From: "lc" <cupido@REMOVEmail.ua.pt>
Date: Tue, 22 Jun 2004 13:56:16 +0100
Links: << >>  << T >>  << A >>
Thanks for all the comments (both on the list and direct email).

Many of you suggested the use of edge trigered instead of latches
that really works fine in all situations and uses less resources.
So, from a design point of view... problem solved. Thanks.

Now, for the inquisitive minds. Just to understand what was
happening I was looking in detail into the reports to see what
was happening. In fact the equation of a
port output bit changed dramatically with and without test point.

As I had a recent design where I use latches without any problem
I started to compare the sources to see what was different and the
only fundamental difference found is the amount of signals used.
On the my previous design (working fine) I used A8 A9 and nWR
signals to control the latch while on this one I was using the
full A8 to A15 byte plus nWR.
So I cut the present design to use just A11 and nWR
and bingo it worked always fine,
then I added A8 and still works fine,
then I added A9... still working fine.
Then I added A10 and PUFF!!! stop working.

I looked into the fitter's report and the equations change dramatically,
producing something that is clearly NOT A LATCH.
I may conclude that I can only have 4 signals controlling the latch.

That is why when I used the testpoint all address lines and nWR were
combined to form my test signal and the latch equation generated used
this signal plus the A8,9,10 bits so it had only 4 inputs.
Without the test point each cell was receiving 9 signals and the synthesised
equation was quite different and therefore not working.

If this is a specific limitation of this particular CPLD or software tool
an error report or a warning would be very welcome.
The reason why only up to 4 signals produce the expected
behavior, I think only Altera can tell...
(would they bother to comment to this poor web licence user ?!)

I think I'll be another one saying to avoid latches on CPLD designs hi:)

Many thanks again for your help.

Luis Cupido.




Article: 70622
Subject: Re: Unused signals in Modelsim
From: "jtw" <wrightjt @hotmail.invalid>
Date: Tue, 22 Jun 2004 13:21:35 GMT
Links: << >>  << T >>  << A >>
Modelsim does not remove undriven/unused signals; a synthesis tool, however,
is likely to.

JTW
"ALuPin" <ALuPin@web.de> wrote in message
news:b8a9a7b0.0406220109.67a062ac@posting.google.com...
> Hi newsgroup users,
>
> maybe you can help me on the following question:
>
> Does Modelsim remove registered signals which are unused or not
> connected to output pins?
> Is there a possibility to avoid this without using output pins?
>
> Kind regards



Article: 70623
Subject: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 22 Jun 2004 15:25:46 +0100
Links: << >>  << T >>  << A >>
Brian Philofsky <brian.philofsky@no_xilinx_spam.com> writes:

> Uwe Bonnes wrote:
> 
> > Marc Kelly <marc@redbeard.demon.co.uk> wrote:
> > : Commandline tools fly, we place and route on a duel hyperthreded
> > xeon (4 : logical cpus) and setting 4 designs off in parallel gives
> > impressive : performace, made the time spent building large
> > Makefiles worth while.
> > I'd appreciated if you would post a simple command file.
> 
> 
> Makefiles/Perl/CSH/etc. are great at times for FPGA implementation,
> especially when you are doing something really unique with the way you
> are running the tools but if anyone wants to run the Xilinx tools from
> command-line, the easiest way is using xflow.  Xflow is a single
> command that can run the Xilinx tools from HDL code to bitstream and
> most everything in between including simulation netlisting.  An
> example command running xflow is the following:
> 
> xflow -implement high_effort -tsim modelsim_verilog <design>.edf
> 

When I tried XFLOW, it seemed to want to create a batch file called
xflow.bat with all the commands in it that needed running.  Next time
I typed an XFLOW command, all it did was run the old xflow.bat from
the current directory.  That had me bemused for a long time - i take
it everyone that uses it does so on Unix (where . isn't on the path
like it is in windos land).

Speaking of batch file processes - does anyone know how to find out if
XST generated any errors - in my experiments, it returns the same
ERRORLEVEL every time.

I'm sure I've seen this with other tools as well, which means that the
compilation runs through to completion on the old files!  One
hackaround I've seen from a reputable source is to do your
implementation in a clean directory every time, copying in the UCF,
EDF eetc.  But that seems nasty!

 <snip>
eers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 70624
Subject: Re: Linux.
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Tue, 22 Jun 2004 14:27:34 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <40d6db9f_1@127.0.0.1>, andrew<AT>rogerstech<DOT>co<DOT>uk wrote:
> Xilinx and Altera have free downloadable design software available for 
> their range of FPGAs, the problem is that it requires Windows.

At least some versions of Xilinx WebPACK work with at least some
versions of WINE on Linux x86.  Doesn't support all devices, but
enough to be interesting.

     - Larry



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