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Try Symplfy and HDL designer and Modelsim for tools and you might be at a better starting point for high end development. ISE and Quartus are bottom end tools. HDL designer will give you the same set of tools for both X & A. Modelsim is a must for any serious design (or a similar tool) The free versions keel over far to fast to be useful. Symplify is a real mans compiler. need I say more Simon "Giorgos P." <gpouikli@ee.duth.gr> wrote in message news:d0rqgp$707$1@nic.grnet.gr... > Hello, > > I am interested in opinions concerning advantages and disadvantages of the > hardware (FPGAs) and developing software (Quartus vs ISE) for high-end (very > demanding designs). > I was under the impression that xilinx was ahead but I've done some reading > lately and StratixII seems to have made a step ahead in comparison to > Virtex4. The devices I am interested in are Stratix and StratixII from one > side and VirtexII pro, Virtex4 on the other. > > There is not one specific parameter that I need to investigate. Procesing > power, memory and I/O data rates are all significant. > > Of cource the role of the EDA tools is important so if someone could give me > his opinion one advantages and week points of each one I would be grateful. > email: gpouikli@ee.duth.gr > Thanks > >Article: 80776
> [..] I want to implement DSP algorithms on FPGA and I think it is > better to write and test the algorithm in C/C++ then convert it to > hardware may be more easy than using VHDl. Try Confluence (www.confluent.org). Compiles into C and VHDL (and more). \ManfredArticle: 80777
Our Broaddown2 has the PCI and the capability to add on the 1394. There are discounts for students but if that would make it cheap enough I don't know. We have a project that may give a 1394 add-on board but I don't have a launch date for this yet. If you are looking at MicroBlaze as a processor then Broaddown2 currently comes with a $100 discount voucher for EDK that can be used at one of our partners in the UK. We also have a product coming that is aimed at students and is going to be aimed at the cheap end of the market. It will be PCI based and should be capable of supporting some of Broaddown2's DIL header add-ons. More details of all of this should appear on our website upgrade in 2/3 weeks time. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Nicolas Schwarzentrub" <schwn@hta-bi.bfh.ch> wrote in message news:d0pg8u$nco$1@news.hispeed.ch... > Hi everybody, > > we're two students looking for a low cost developer board for our > diploma work. we intend to plug a camera to the pci board via 1394 and > process the images throug the fpga and get the processed images from > fpga via pci. The camera we will use, uses DCAM /IICD > Now we have several problems: > -we don't have a high budget, so it should be a low cost solution. > > -we have not jet found a board that fits our need, does anybody know > something cheep that could fit our needs? > > -there would be several possibility to solve the connectivity problems: > > * best would be to find a board that fits our need, means have at least > pci, fpga and 1394 on it? any suggestions ont htat? > > * if the above point can't be reached we could probably solder our 1394 > interface ourself on a board. What would then be best for our purpose? > We could probably use a TSB12LV32 chip from ti if we don't find a board > with firewire. > (http://focus.ti.com/docs/prod/folders/print/tsb12lv32.html)? does > anybody know this? would it then be possible to implement the dcam in > the fpga? > > Thanks to everbodyArticle: 80778
Andr=E9s wrote: > Thank you for your answers, > > although I have searched for the topic "reset + release" I am still > confused. > If Mr Randolph says that there in only one global reset path > so does it make any sense to release the reset signals for the different > clock domains separately that is to synchronize the reset with the > corresponding clock and distribute different reset signals? Howdy Andr=E9s, Sorry, I wasn't very clear - but believe it or not, Paul and I aren't contradicting each other. Although all FPGA's that I'm aware of have only one global reset net, Altera has considerably more total local and global control resouces. Just take a look at the block diagram for their LE. I had somehow forgotten about Altera's LAB level resets LABCLR1 and LABCLR2 (in addition to chip level clear). I must defer to Paul Leventis for the details on how you can use them (after all, he works for Altera), but hopefully he'll confirm that you can run your reset net through a series of synchronoizing FF's before you put it onto one of the LAB (or global) reset nets so that when the reset is deasserted, it isn't asynchronous to the clock. Paul? Have fun, MarcArticle: 80779
Antti Lukats wrote: > > In generic almost all the comparison from Austin where valid, ok he > forgot to mention the StratixGX and ARM stripe, but if only looking > at latest products in comparison then Altera does not MGTs > and hardcore processors in last families Howdy Antti, I'm not sure why you have to only compare the latest familes, but if that's what's being done, then so be it. In that case, there have been press releases on the Virtex-4 having MGT's, but no-one outside of Xilinx can lay their hands on one. Thanks for the follow-up, MarcArticle: 80780
I'm trying to perform a simulation of my OPB peripheral. I have done the following steps: 1. Opened bfm_system.xmp project in XPS. 2. Clicked Options -> Project Options ... to open up the Project Options and modified 3. Clicked Tools -> Generate Simulation HDL files in XPS to generate the BFM simulation platform. This is the console log: (Console Log) PM_SPEC -- Xilinx path component is <C:/EDK> Project Opened. At GMT date and time: 2005:3:11:13:10:38 Command bash -c "cd /xygdrive/c/edk_user_repository/MyProcessorIPLib/pcores/opb_lcd_display_v1_00_a/devl/bfmsim/; /usr/bin/make -f bfm_sim_xps.make simmodel; exit;" Started... * ******************************************** Create behavioral simulation models ... * ******************************************** simgen bfm_system.mhs -p xc3s200ft256-5 -lang vhdl -lp ../../../../../ -mixed yes -s mti -X C:/ISE_Lib/ -E C:/EDK_Lib/ -m behavioral Simulation Model Generator Xilinx EDK 6.3 EDK_Gmm.10 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. PM_SPEC -- Xilinx path component is <C:/EDK> Command Line: simgen -p xc3s200ft256-5 -lang vhdl -lp ../../../../../ -mixed yes -s mti -X C:/ISE_Lib/ -E C:/EDK_Lib/ -m behavioral bfm_system.mhs MHS file : \...\devl\bfmsim\bfm_system.mhs Language (-lang) : VHDL Simulation Model (-m) : Behavioral Simulator (-s) : ModelSim (MTI) Part (-p) [ family ] : xc3s200ft256-5 [ spartan3 ] Output directory (-od): C:\edk_user_repository\MyProcessorIPLib\pcores\opb_lcd_display_v1_00_a\devl\bfms im\ Edklib (-E) : C:\EDK_Lib\ Xlib (-X) : C:\ISE_Lib\ Library Path (-lp): C:\edk_user_repository\ Simulation Model Generator started ... Reading MHS file ... lp : C:\edk_user_repository\ ERROR:MDT - Path 'C:\edk_user_repository\' already added. make: *** [simulation/behavioral/bfm_system.do] Error 1 Done. What I could do to solve the troulbe? Thanks MarcoArticle: 80781
"Marc Randolph" <mrand@my-deja.com> schrieb im Newsbeitrag news:1110546757.696144.85280@o13g2000cwo.googlegroups.com... > > Antti Lukats wrote: > > > > In generic almost all the comparison from Austin where valid, ok he > > forgot to mention the StratixGX and ARM stripe, but if only looking > > at latest products in comparison then Altera does not MGTs > > and hardcore processors in last families > > Howdy Antti, > > I'm not sure why you have to only compare the latest familes, but if > that's what's being done, then so be it. In that case, there have been > press releases on the Virtex-4 having MGT's, but no-one outside of > Xilinx can lay their hands on one. > > Thanks for the follow-up, > > Marc > LOL, yes the FX12 has no MGT and I am one of those who really wants to see the new V4 MGTs but those are not yet in devices that are deliverable IMHO, there is some info that the V4 MGTs are better than the RocketIO-X but how far that is to be seen AnttiArticle: 80782
Hallo, I have developed a OPB peripheral with some cores created with CORE GENERATOR. When I synthetize with ISE everything goes. When I use the peripheral in EDK, I receive the following error during BITSTREAM GENERATION: ERROR:NgdBuild:604 - logical block 'opb_lcd_display_0/opb_lcd_display_0/USER_LOGIC_I/VIDEO_RAM_I' with type 'video_ram' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'video_ram' is not supported in target 'spartan3'. HERE the component: component video_ram port ( addra: IN std_logic_VECTOR(14 downto 0); addrb: IN std_logic_VECTOR(13 downto 0); clka: IN std_logic; clkb: IN std_logic; dinb: IN std_logic_VECTOR(7 downto 0); douta: OUT std_logic_VECTOR(3 downto 0); web: IN std_logic); end component; VIDEO_RAM_I : video_ram port map ( addra => r_addr_read, addrb => r_addr_write, clka => clk_2_s, clkb => BUS2IP_CLK, dinb => r_din, douta => r_dout, web => r_we); What is the trouble? Thanks MarcoArticle: 80783
Where is dowlodable Webpack 7.1? Uwe Bonnes ha scritto: > Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com> wrote: > >>Hello, > > > >>I've just tried the WebPack 7.1 under linux for the first time. > > ... > > >>Go & Try it ! > > > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DS-ISE-WEBPACK > > still tells: > > " ISE WebPACK 7.1i is coming soon!" > > Where did you find "Xilinx ISE 7.1"? > > ByeArticle: 80784
yes, where did you find it? Uwe Bonnes ha scritto: > Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com> wrote: > >>Hello, > > > >>I've just tried the WebPack 7.1 under linux for the first time. > > ... > > >>Go & Try it ! > > > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DS-ISE-WEBPACK > > still tells: > > " ISE WebPACK 7.1i is coming soon!" > > Where did you find "Xilinx ISE 7.1"? > > ByeArticle: 80785
"antonio bergnoli" <bergnoli@pd.infn.it> schrieb im Newsbeitrag news:42319bba$1_3@x-privat.org... > Where is dowlodable Webpack 7.1? Thats the trick!!! there is none, you have order the CDs pay for shipment, for custome duty and local VAT maybe too. And wait and wait. NO DOWNLOAD (not yet) AnttiArticle: 80786
Marc, >I had somehow forgotten about Altera's LAB level resets LABCLR1 and >LABCLR2 (in addition to chip level clear). I must defer to Paul >Leventis for the details on how you can use them (after all, he works >for Altera), but hopefully he'll confirm that you can run your reset >net through a series of synchronoizing FF's before you put it onto one >of the LAB (or global) reset nets so that when the reset is deasserted, >it isn't asynchronous to the clock. >Paul? The "global" networks can be driven by the general routing in the chip, which in turn can be sourced from any logic block in the chip. So you can bring in a reset on a normal I/O, whip it through synchronizers, and then pass the synchronized signal(s) through the global low-skew network to distribute to all the affect nets. Or you can route the resulting synchronized signal on normal routing with an appropriate timing constraint to ensure that all flops will be released on the same clock cycle. I don't think we have a dedicated chip-level clear, but I could be wrong... I thought that a chip-wide clear is implemented just by driving a global network directly from a user or clock I/O. But its not my area of specialty -- I'll ask around to confirm. BTW, the Quartus 4.2 timing analyzer software will perform Recovery and Removal Analysis for asynchronous paths. Regards, Paul Leventis Altera Corp.Article: 80787
Hi Antti, Yes, there will be a Stratix II GX family. Stay tuned. There is a reason why we don't haven't made a chip with a hard processor since Excalibur. Basically, once you have a highly flexible and well-accepted soft processor like Nios, there are very very few designs that can benefit from a hard processor. Paul Leventis Altera Corp.Article: 80788
ezpcb.com wrote:
>Hi all
>I want to design a 1024 poles FIR filter on FPGA. But I had no
>experiences on large scale FPGA programming. Can anybody tell me which
>chip should I use?
>
>mike
>
>
>
>
You need more information before you can decide on an approach:
what is the sample rate? what is the clock rate? can you use a
multiplied clock? How many bits per sample? How many bits do you need
per tap coefficient?
The number of taps is high enough that a fast convolution using overlap
and add FFTs might yield better density.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 80789"The JTAG state machine is organized such that it will always return to the Test-Logic-Reset state in at most 5 TCLK cycles if TMS is held high." Again, this is not what the specification states. "At most" would be a maximum, "at least" is a minimum. "No matter what the original state of the controller, it will enter Test Logic Reset when TMS is held high for at least five rising edges of TCLK" If it could reach test mode on one clock, I can see where this could be a potential problem. Again, I just want to make sure that Xilinx has done their homework on this and that pulling the clock pin high will not introduce problems on any of their devices.Article: 80790
Mook Johnson wrote:
>I'm looking to implement four, 150 tap FIR filters in an Actel MX series
>FPGA. The filters I'm designing are 16 data bit input, 16 bit coeffienencs
>and
>1khz sample rate. FPGA will be clocked with a 10MHz clock and will have a
>state machine to retrieve the samples from the A2D following a 1khz
>HW interrupt.
>
>How do I estimate the resource requirements to implement the filter section?
>Any
>special hurdles in implelenting FIR filters in a Actel MX series FPGA?
>
>MX series is a fixed quantity and cannot be changed.
>
>thanks
>
>
>
>
You have 10,000 clocks per sample to work with, which gives you 66
clocks per tap for one filter, or 16 clocks per tap per filter for all
four, to compute the tap products. This means you don't need to
construct a full parallel multiplier. Instead, your filter consists
simply of a pair of accumulators. The first one is a scaling
accumulator multiplier (see http://www.andraka.com/multipli.htm ), which
performs a 16xN multiply every 16 clocks. The second one accumulates
the products. you have fours sums of products to compute for each
incoming sample period. The sample data will need to be serialized. The
resulting logic is quite small (about 50 FFs), and will fit in all but
the smallest of the MX devices. Arithmetic is awkward in the MX family,
but for a 10 MHz clock, shoud not be a problem. The sticking point is
going to be memory: you need 600x16 memory for the data delay plus
150x? for each unique set of coefficients. Since there are two unique
sets of coefficients, you'll need 1Kx16 of memory. The MX family does
not have internal memory, nor do any of the devices have a sufficient
number of flip-flops to provide 16K bits of storage. Hopefully, you can
add an external SRAM to the design.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 80791Hi, so I was playing for the first time with the DCM of a Spartan 3. It worked fine but as soon as I used the CLKFX output, the DCM failed to lock. The problem was that I had mistyped the name of the CLKFX_MULTIPLY generic in the component instantiation as CLKFX_MULT. xst, map, par, bitgen all ran without complaining although the DCM component in unisim.vcomponents has no generic named CLKFX_MULT. Correcting the typo solved the problem, of course, but it was by pure luck that I noticed it. Does this match your experience? Is that how the ISE tools are supposed to be "easy"?Article: 80792
http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=7500055955 Antti PS Paul was interested to Know (from first hand) that my guess about S2-GX was right :) And yes I agree sometimes its wise to delay with some things...Article: 80793
Symon wrote:
>Go for it all you early adopters of the 'latest and best'! And let me know
>when you've reported enough bugs to fill a service pack 2 release. ;-)
>In the depths of cynicism, Syms.
>
>
>
FWIW, I don't even load a mjor release anymore until service pack 1 is out. Better to let someone else find the easy bugs!
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 80794ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0503110036.1b73c25c@posting.google.com>... > Hello @ VHDL people out there, > > I have the following problem. Maybe someone of you has experienced the same: > > The signal "input_data" comes from a 12MHz clock domain. > Now I want to sample that signal that way that I generate one sample-enable > which is close to the center position of the bits. > One possibility to do so is to use a over-sampling clock, let us assume > 48MHz. > > > The problem: 90 is not a multiple of 12. > Is there a possibility to sample the 12MHz signal right in the center ? > Hi, 90/12 = 7.5 and fractional division may be performed by dividing by 7 one cycle and 8 the next. If the jitter is acceptable, the resulting divisor is 7.5. /PeterArticle: 80795
In my Virtex2 design, I have an external clock coming into an IBUFG, with the output connected to CLKIN of a DCM. Two of the DCM outputs (CLK1X and CLKFX) are connected to BUFGs. So what should I declare on the "Clocks" tab of SCOPE in Synplify Pro? The input port, the net at the IBUFG output, the two BUFG instances, or what? I am having trouble getting Syn Pro 8.0 to understand my clocks.Article: 80796
Paul, Well, when you have a confused and changing processor strategy (hard?, soft?, I?, II?, you offend your potential customers, and they go away. Nearly half of the V2 Pro users use the 405PPC. Software takes longer to write, gets reused, has lots of previous IP. That is why when we looked at a processor choice, we chose one that had a 1/3 market share, and had that market share primarily in the markets we address. Now the PPC has >>1/3 market share. One comment I heard was "Xilinx has done more to promote the PPC in one year than was done in the previous ten years." Half is a lot of business (you lost). Austin(a)* *Never been called a 'she' before....Article: 80797
Simon Peacock wrote:
> Try Symplfy and HDL designer and Modelsim for tools and you might be at a
> better starting point for high end development.
I agree that a good hdl editor, simulator and synthesis are the key.
If you are comfortable without graphical editing,
emacs vhdl-mode can cover HDL designer's turf for free.
> ISE and Quartus are bottom end tools.
For design entry and simulation, I agree.
For place+route they are essential.
Their hdl synthesis is quite good for the money,
certainly worth a try after simulation is complete.
> HDL designer will give you the same
> set of tools for both X & A.
This is true whenever and however you
generate code using generic
hdl and no vendor black boxes.
> Modelsim is a must for any serious design (or
> a similar tool) The free versions keel over far to fast to be useful.
Modelsim or similar. I agree. A fully licensed hdl simulator is where
a designer spends time most productively.
> Symplify is a real mans compiler. need I say more
Synplify is a fine synthesis tool. There are others.
Once you have a good set of design rules and
simulation process, synthesis becomes just
an important detail.
-- Mike Treseler
Article: 80798lecroy7200@chek.com wrote in news:1110552324.463013.313590 @l41g2000cwc.googlegroups.com: > "The JTAG state machine is organized such that it will always return to > the Test-Logic-Reset state in at most 5 TCLK cycles if TMS is held > high." > > Again, this is not what the specification states. "At most" would be a > maximum, "at least" is a minimum. It depends upon your viewpoint. If you look at it from the standpoint of the TAP controller, you see that it will take at most 5 clocks to get yourself from any state back to test-logic-reset. If you look at it from the standpoint of the system designer, you see that you will need to provide at least 5 clocks to guarantee that the TAP controller is in test-logic-reset (provided you have no knowledge of the current state of the TAP controller). If I were you, I would stop parsing the text of the document (which can be fuzzy) and go directly to the TAP controller state diagram (which is not): http://www.inaccessnetworks.com/projects/ianjtag/jtag-intro/jtag- state-machine-large.png > > "No matter what the original state of the controller, it will > enter Test Logic Reset when TMS is held high for at least five rising > edges of TCLK" > > If it could reach test mode on one clock, I can see where this could be > a potential problem. > > Again, I just want to make sure that Xilinx has done their homework on > this and that pulling the clock pin high will not introduce problems on > any of their devices. > -- ---------------------------------------------------------------- Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 80799
Thanks Mike, methinks that what you suggested is the right thing to do. To extend your suggestion, suppose i have 5 levels of hierarchy-A,B,C,D and E. 'A' being the top module and E being the leaf-level module. An output 'OUT' from 'E' needs to propagate to 'A' passing as output of 'D', 'C' and 'B' blocks. In this case, 'OUT' is an output of each module right from 'E' to 'A'. My question is if I use your advice, I would be registering 'OUT' at each level, is that what I should do? Thanks MORPHEUS
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z