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Andrew Whyte wrote: > With XST, what I can do is read in a .mif file and then parse the data > to create init values for my memory elements. Synplify does not appear > to able to do the file read. This subject has been discussed on comp.lang.vhdl http://groups-beta.google.com/groups?q=vhdl+treseler+rom+array+constant -- Mike TreselerArticle: 80651
Mike, Sounds good, but I believe it doesn't work that way. If you know you are going to use part A, or part X, you will then use the powerful built in features that each vendor offers. For example, Xilinx SRL16's are great for many DSP and signal processing tasks. The Xilinx/IBM PPC are also very useful. Many of these features define an architecture. Altera has a similar portfolio. Pick a generic HDL, and code without regard for these special features, and then you are at the mercy of the HDL compiler to somehow find the best structures in each FPGA. For high end designs, you will have to take advantage of the manufacturer's device specific feature set to get the performance you want for the least cost (smallest) and fastest device/design. Austin Mike Treseler wrote: > Giorgos P. wrote: > >> I am interested in opinions concerning advantages and disadvantages of >> the >> hardware (FPGAs) and developing software (Quartus vs ISE) for high-end >> (very >> demanding designs). > > > Consider deferring the vendor and part selection until after you > have prototyped and simulated a substantial portion > of your design in vendor-agnostic hdl. Use synthesis > to pick a device from each vendor and then get quotes. > > -- Mike TreselerArticle: 80652
Hi, I searched the newsgroup but wasn't able to find anything!! It seems like somebody before me requested it! So thanks anyway! Thanks, PrebenArticle: 80653
pablo wrote: > Hi, > Check the availability of BUFG's in your device(do you exceed?). No, I'm using only 4 out of 16 BUFG available. > There are some other options like taking the clk to I/O pin and > bringing > back the clk and using a DLL to adjust the skew as required(which is > best > option i think, with assumption that you have spare I/O pins and DLL's > available in your device). I'd like to change the original VHDL the less I can (you know, the aim is to validate it, not just obtaining a working design...) but it seems a good idea and I think I'll try it out if I can't find anything less invasive, thanks a lot.Article: 80654
Hello,
I've just tried the WebPack 7.1 under linux for the first time.
Globally, I'm very happy not to have to start vmware or another
machine each time I want to have some work done !
I haven't yet tried it in depth, just small things, see what has
changed, etc ...
The whole thing seem still based on WindU though ...
Some negatives :
- The RTL schematics generated by "View RTL schematics" are
... wrong ! At first I thought the synthesis was completly
off but finally viewing the technology schematics, I saw it's
in fact the RTL schematics generator itself that's way off.
(Not all time, just on a few quite simple case, it just got
it wrong imho)
- When in the technology schematic, viewing lut content shows
nothing at all.
- Spartan 3 support for > 1500 is gone ... but we knew that
would be the case.
- It's not _that_ pretty ;) (far from eye candy like macosx)
I still need to do more advanced test like see if there is any gain
compared to previous version.
Go & Try it !
Sylvain
Article: 80655> Consider deferring the vendor and part selection until after you > have prototyped and simulated a substantial portion > of your design in vendor-agnostic hdl. Use synthesis > to pick a device from each vendor and then get quotes. Good advice. But be sure to use the post P&R performance and logic-utlization results to select a device. Synthesis estimates are less accurate and while they can be pretty good on average, for any given design could be far off the mark. Also, register packing (grouping logic & registers) for Altera devices happens in the P&R flow, which will substantially reduce your logic requirement. Regards, Paul Leventis Altera Corp.Article: 80656
Hi everyone,
I'm stuck implementing a hardware design on a Spartan3 Starter Board
which uses a xc3s200 fpga.
After several times trying to include an opb_ethernet core on to the
design I never acheive to generate the bitstream.
I get the following messages whilst mapping:
Design Summary:
Number of errors: 1
Number of warnings: 83
Logic Utilization:
Total Number Slice Registers: 3,035 out of 3,840 79%
Number used as Flip Flops: 3,034
Number used as Latches: 1
Number of 4 input LUTs: 3,739 out of 3,840 97%
Logic Distribution:
Number of occupied Slices: 2,625 out of
1,920 136%
(OVERMAPPED)
Number of Slices containing only related logic: 2,180 out of
2,625 83%
Number of Slices containing unrelated logic: 445 out of
2,625 16%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 4,466 out of 3,840 116% (OVERMAPPED)
Number used as logic: 3,739
Number used as a route-thru: 154
Number used for Dual Port RAMs: 280
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 293
Number of bonded IOBs: 62 out of 173 35%
IOB Flip Flops: 58
Number of Block RAMs: 12 out of 12 100%
Number of MULT18X18s: 3 out of 12 25%
Number of GCLKs: 2 out of 8 25%
Number of BSCANs: 1 out of 1 100%
Number of RPM macros: 5
Total equivalent gate count for design: 887,513
Additional JTAG gate count for IOBs: 2,976
Peak Memory Usage: 113 MB
Does this mean I cannot use an ethernet core in my design??
Is there any way of reducing the logic used by the ethernet core??
Could anybody please help me out?
I have tried using ethernet lite core but it's no use to me since I have
to be using lwIP library which isn't supported with ethernet lite.
Thankyou.
Adrian
Article: 80657I think his main problem is that the full flag doesn't deassert when data is read out because the full flag logic isn't being clocked. It asserts OK. Besides, the method described will yield catastrophic errors. Comparing non-Gray-coded pointers across domains during a transition will result in reading values that are neither the current nor next value, meaning that the full flag can be deasserted when the FIFO is full, causing the user to write data into the bitbucket. Symon wrote: > Paul, > Hang on, isn't this easy? Only the write side is interested in the Full > Flag, right? The write side is throttled. That makes it a lot easier. > So, you have a binary coded incrementing write pointer. It points to where > the next data will be stored. You have a binary coded incrementing read > pointer. It points to where the next read comes from. Use a combinatorial > comparison to see if the read pointer is one more than the write pointer. If > so, report full to the write side. This 'full flag' can only be seen as > metastable by the write side if a read has just happened. In which case > write or don't write doesn't matter. There will be space. On the read side > use a combinatorial comparison to see if the read pointer is equal to the > write pointer. This means empty. This 'empty flag' will only be seen as > metastable by the read side if a write has just happened. In which case a > read or not read cycle is OK, there will be data to read. > No Gray code nonsense needed as long as you don't mind a few transient false > fulls and empties. You could add extra stuff if you wanted to fill the thing > right to the brim, because then the full and empty conditions both have the > pointers equal. > You also need to make sure, when empty, the write cycle completes before the > read side can see the 'empty flag' go away. And vice-versa. > Cheers easy, Syms. > p.s. My spell checker suggests detestable instead of metastable. How > appropriate! > > > "Paul Davis" <rft56@dsl.nospam.pipex.com> wrote in message > news:a5tr21drgcgc5k6okiakgf22cjv0646of1@4ax.com... > >>Yet another async FIFO question... :( >> >>I've inherited an async FIFO that doesn't work. This is, I think, a >>fairly standard implementation. On the write port, a clock and a write >>enable increment a write pointer, and write the write data into a RAM. >> >>The read pointer is Gray-coded, clocked into a reg on the write clock, >>inverse coded, and then compared with the write pointer, to give a >>write-side full flag. >> >>The read side is simply the inverse of the write side. >> >>So far, so good. The problem is that this design assumes a >>free-running write clock, and my write clock is not free-running; I >>simply generate a clock when the (unpredicatable) write data appears. >>The write enable is therefore effectively redundant. >> >>The problem arises because the 'fifo full' flag is generated by the >>*write* clock. If, on write X, the comparator determines that the FIFO >>is full, then the full flag is generated, and I don't create any more >>write clocks. The read side might empty the FIFO, but this information >>never gets back to the write port, because the register that samples >>the Gray-coded read pointer is clocked by the write clock. >> >>Any ideas on how I re-design this to cope with a write clock which >>isn't free-running? >> >>TIA - >> >>Paul > > >Article: 80658
> When will we have a Linux Quartus web edition ? What does it mean a "web" edition? Does it mean we can use it via HTML browser? What is the reason to bother about local OS then?Article: 80659
valentin tihomirov wrote: >>When will we have a Linux Quartus web edition ? > > > What does it mean a "web" edition? Does it mean we can use it via HTML > browser? What is the reason to bother about local OS then? > > No, that's the version you can download freely from the web ... They called it "web edition" ... SylvainArticle: 80660
Austin Lesea wrote:
> Mike,
>
> Sounds good, but I believe it doesn't work that way.
It does for me.
> If you know you are going to use part A, or part X, you will then use
> the powerful built in features that each vendor offers.
Many do, but I don't.
If the feature can't be inferred from code
for both vendors, I'd rather not use it.
-- Mike Treseler
Article: 80661
Paul Leventis wrote:
> Good advice. But be sure to use the post P&R performance and
> logic-utlization results to select a device.
I agree. I run both place and routes from time to time
to make sure I am on track.
-- Mike Treseler
Article: 80662You can use a standard text editor to edit the ucf file :-) Well, a RPM is a group of elements, whose location relative to each other, is fixed, but their absolute location is undefined. This may be a register bank, whose single registers are placed in a column, or something else. You can use the Xilinx floorplanner to place whatever your design contains, either fixed, or relatively (by grouping). The result can be saved in the ucf, and this ucf can be used to reproduce the desired placement in the next implementaion. You would only want to do this for speed, control or the beauty of the design :-) Try to google this group, a lot of infos can be extracted from old posts. BR, Chris Thomas Reinemann wrote: > Hello, > > I'm going to create a RPM after PAR, for a Xilinx Virtex2. Following XAPP422 > I have to launch floorplanner to create the ucf and ngc. Since I don't > change the placement I hit only some menu items and and exit it. The ngc > can be created via ngcbuild. Is there any command line tool for generating > the ucf? > > > Furthermore, what stands RPM for. XAPP422 says Relationally ... but XAPP416 > Relatively ...:-) > > > Bye TomArticle: 80663
each of these tools as you know is specific to their FPGA vendor. So I dont think you can really compare them.Article: 80664
Hi - So, is this some kind of "deadly embrace" situation, in which the full flag gates off the write clock, and the write clock is needed to update/deassert the full flag? Bob Perlman Cambrian Design Works On Tue, 08 Mar 2005 21:42:22 +0000, Paul Davis <rft56@dsl.nospam.pipex.com> wrote: >On Tue, 08 Mar 2005 20:47:29 GMT, Bob Perlman ><bobsrefusebin@hotmail.com> wrote: > >>Hi - >> >>What's clocking the logic that's looking at the full flag? Is it by >>any chance an ungated version of the write clock? > >No - it's just the write clock that gets supplied to the FIFO. I do >create the clock myself, though - it's a combination of various >signals from two other clock domains. There isn't a free-running >precursor to this signal in one of the two domains (presumably that's >what you meant?) > >- PaulArticle: 80665
I thought more often than not it would be largely decided by past experience of your EEs on the project since the A v X varies over time as new parts are released. Have you asked your group members what they prefered? regards johnjakson at usa dot comArticle: 80666
Mike, Then you are not a high end user. Austin Mike Treseler wrote: > Austin Lesea wrote: > >> Mike, >> >> Sounds good, but I believe it doesn't work that way. > > > It does for me. > >> If you know you are going to use part A, or part X, you will then use >> the powerful built in features that each vendor offers. > > > Many do, but I don't. > If the feature can't be inferred from code > for both vendors, I'd rather not use it. > > -- Mike TreselerArticle: 80667
Austin Lesea wrote:
> Mike,
>
> Then you are not a high end user.
We are a pretty boring group
here at Danaher/Fluke Networks.
We do packet processing for WAN/LAN
monitors at OC3/OC12/DS3/GigE.
We don't do much with the multipliers
and the on-chip CPUs, but we are
pretty good at negotiating
FPGA prices.
-- Mike Treseler
Article: 80668Mike, The synthesis tools are pretty good at inferring multipliers/MACs from HDL, as well as other higher-level primitives. So your "vanilla" approach to design may still take advantage of some of the hard blocks available. I should point out that you should see very good performance in Stratix-II without any architecture-specific coding. Quartus will automatically balance multipliers between LEs and DSP blocks, and also automatically handles the mapping of generic RAMs into the three available RAM types in the device. We like to make things as easy as we can on our users, otherwise these features would go unused in many designs! Regards, Paul Leventis Altera Corp.Article: 80669
Mike, You know your business, that is for sure. And based on that, you make decisions. We have a number of customers who treat FPGAs as a commodity. Use no special features. Generic HDL only. Not my favorite model, but I know some folks use it. Austin Mike Treseler wrote: > Austin Lesea wrote: > >> Mike, >> >> Then you are not a high end user. > > > We are a pretty boring group > here at Danaher/Fluke Networks. > We do packet processing for WAN/LAN > monitors at OC3/OC12/DS3/GigE. > We don't do much with the multipliers > and the on-chip CPUs, but we are > pretty good at negotiating > FPGA prices. > > -- Mike TreselerArticle: 80670
Hi Andres Why do you need to have the reset signal sync'd?? Usually a reset is a pretty 'abrupt' sort of action, with no return, so you dont need it to be sync'd, and it can go over many clock domains.. process: (gsr, sys_clk) if (gsr = '1') then --reset elsif rising_edge(sys_clk) then --sync signals... end if; end process; Or am I not understanding you properly??Article: 80671
Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com> wrote: > Hello, > I've just tried the WebPack 7.1 under linux for the first time. ... > Go & Try it ! http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DS-ISE-WEBPACK still tells: " ISE WebPACK 7.1i is coming soon!" Where did you find "Xilinx ISE 7.1"? Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 80672
spacexxspace@yahoo.com wrote: > Hi All, > > Do you know what are the advantages and disadvantages / differences > between the FPGA development tools such as > Actel Libero IDE, Never used it. > Xilinx ISE The free version of ISE is good enough from small to medium size projects. It can synthesize up to 1.5 M gates with Spartan 3 chips. The paid version support larger chips and additional features such as FPGA editor and the CoreGenerator. You can buy the discounted student version of ISE, which is basically the same with the professional version, except that you aren't eligible for tech support and you can't use it to make money. You will need to download seperate ModelSim Xilinx Edition (also free), that simulates at full speed when your code is 500 lines or less. After that, the simulation will slow down but still works. If you don't like ModelSim, you can use other Simulators of your choice. > and Altera MAX+PLUS II? Really sucks! It has very clumsy user interface, and it doesn't support HDL based TestBench at all. Some Prof at my college forced us to use it. My experiences of using this jurassic tool has always been a nightmare. If you have a choice, stay away from it! Altera Quartus might be better, but I have a feeling that if it has built in simulator, it doesn't support HDL based testbench either! HendraArticle: 80673
According to their spec, the built in simulator is not included with Webpack. HendraArticle: 80674
dwerdna wrote: > Hi Andres > > Why do you need to have the reset signal sync'd?? Usually a reset is a > pretty 'abrupt' sort of action, with no return, so you dont need it to > be sync'd, and it can go over many clock domains.. If you don't have a reset pulse within your FPGA, you'll have to reload the device everytime you want to get back to a known good condition. Although it may be unnecessary with FPGA's most people tend to pulse reset at the beginning of action, not just at the end... and/or they pulse it to recover from error conditions, or reinitialize after a reboot. Granted people tend to overuse resets, but even so, most designs need to be able to recover from them. To answer the OP's question, all FPGA's that I'm aware of have a single global reset net. And despite what many say, a co-worker has found a very smart way to use it (at least on V2Pro and newer), even for designs with multiple domains. If you don't end up using it, then you'll chew up quite a few resources if there are many loads Have fun, Marc
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Compare FPGA features and resources
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