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Hi Arlet, You can use a coe. file (memory coefficient file) that will be attached to your BRAM. The Xilinx "core generator GUI" has internal tool called "Memory Editor" it's under the Core generator "Tools" menu. Using this tool you can easily create memory init files that can be attached to your memory. Regards, Moti.Article: 80451
On 04 Mar 2005 18:18:17 -0800, Eric Smith <eric@brouhaha.com> wrote: >"Falk Brunner" <Falk.Brunner@gmx.de> writes: >> Yeah, but what about tolerances? The 1,25V reference of the good ole LM317 >> ist exactly 1,25V. Are the tolerances within the +/-5 % of the 1,2V for the >> core? > >No. The reference voltage specification for the LM317 is min 1.20V, max >1.30V (page 5 of data sheet from National, dated July 2004). So for any >given LM317, you *might* be able to adjust to within the rating of an >XC3S (1.14V to 1.26V), or you might not. The LM317A has a tighter >range, 1.225V to 1.270V, which is still potentially out of spec. From the above, -50mv on the reference pin would bring the LM317 into spec... - BrianArticle: 80452
I'm developing a state machine to read and write data into block ram. When I make reading operation, the state is always the same, s0, and it is reassigned every time ram address changes. The processes to detemine next_state and state operations are state sensitive. If state does not change, that processes are executed in any case? Thanks MarcoArticle: 80453
Hi Marco, if I understand you correctly your next_state generation process is of the form process (this_state) begin ... next_state <= ... ... or the equivalent always @(this_state) in Verilog. This is an implicit wait for an event on the signal this_state, i.e. your process is only triggered if 'this_state' changes. If you want the process to execute on every change to ram_address you must add ram_address to the sensitivity list. A possible alternative which is often used is to trigger the process on each clock. Here the sensitivity list would look like process (clk) . . . . or even process (clk, reset) You can then recalculate your next_state on every clock tick in your system Hope this helps, CharlesArticle: 80454
Your state machine should reacte to any transition in the clock (rising or falling) making it sensitive to clock change. However the reaction nature (FSM functionality) should be according to the present state. the clock sensitive process is usually the one that is responsible for the state transitions (state <= next_state). if your outputs are state dependent only (mealy machine) then you don't want them to change as long as you stay in a specific state. If your outputs are state and input dependent (moore machine) then you can change your outputs (using the inputs) and still stay in the same state. You just have to choose what kind of machine will do the trick.. Regards, MotiArticle: 80455
On Sat, 5 Mar 2005 21:49:42 -0000, "Stephen Lannard" <s.l@nospamplease.com> wrote: >Hi. > >I'm trying to do two basic things with a 22v10 but seem to be getting >nowhere with them and would appreciate some help. > >I need the 22v10 to do the following: > >1) Divide a 2mhz clock signal by 2 and output a 1mhz signal. Assuming the clock is coming into the global clock line pin 20 = clkout; clkout.d=!clkout; >2) Output a high pulse for a duration of X clock cycles, triggered by an >input going high. There are various ways to do this. one way would be to have a synchronous up-counter of the required number of bits, preloaded with -X when the input goes high and clearing the output when the counter rolls to zero after the required number of cycles. I'm sure there are some exaples of counters in the demo files.Article: 80456
Hello I need information about Discret cosinus transform algorithms implemented in FPGA structures. Any links, doc`s? Best RegardsArticle: 80457
KJ wrote:
> For those (like me) who has no experience in FPGA programming, can you
> suggest which SW tool(s) (free or low-cost) would be good to start with for
> vendor independent learning ?
I agree with Hendra. Choose your simulator first.
For vendor independent design, choose vhdl or verilog design entry.
Brands A and X have low cost versions of modelsim for either HDL.
Once you have written code and tested in using a simulation
testbench (more code), you can port your design to any device
on any fpga board. Avoid the wizards and core generators.
For vhdl you can try the free version of sonata at
http://www.symphonyeda.com/proddownloads.htm
and the design and testbench example at
http://home.comcast.net/~mike_treseler/
Good luck.
-- Mike Treseler
Article: 80458Many Thanks to everyone! Your help is very useful! MarcoArticle: 80459
Hi, > Assuming the clock is coming into the global clock line > > pin 20 = clkout; > clkout.d=!clkout; Thanks for that. >>2) Output a high pulse for a duration of X clock cycles, triggered by an >>input going high. > > There are various ways to do this. > one way would be to have a synchronous up-counter of the required number > of bits, preloaded with -X > when the input goes high and clearing the output when the counter rolls to > zero after the required > number of cycles. From what I can see with counters, they seem to eat-up output pins? > I'm sure there are some exaples of counters in the demo files. Indeed there are examples, but i don't find them too helpful. They kind of assume you have an idea of what you're doing and at the moment i don't. :( I'm new to this and maybe i'm expecting too much of the 22v10. StephenArticle: 80460
On Sun, 6 Mar 2005 15:25:40 -0000, "Stephen Lannard" <s.l@nospamplease.com> wrote: >Hi, > >> Assuming the clock is coming into the global clock line >> >> pin 20 = clkout; >> clkout.d=!clkout; > >Thanks for that. > >>>2) Output a high pulse for a duration of X clock cycles, triggered by an >>>input going high. >> >> There are various ways to do this. >> one way would be to have a synchronous up-counter of the required number >> of bits, preloaded with -X >> when the input goes high and clearing the output when the counter rolls to >> zero after the required >> number of cycles. > >From what I can see with counters, they seem to eat-up output pins? Yes - one macrocell per bit. >> I'm sure there are some exaples of counters in the demo files. > >Indeed there are examples, but i don't find them too helpful. They kind of >assume you have an idea of what you're doing and at the moment i don't. :( > >I'm new to this and maybe i'm expecting too much of the 22v10. Depends on your likely range of X.....Article: 80461
>>Indeed there are examples, but i don't find them too helpful. They kind of >>assume you have an idea of what you're doing and at the moment i don't. >>:( >> >>I'm new to this and maybe i'm expecting too much of the 22v10. > > Depends on your likely range of X..... 12ms will need 12 bits @ 1mhz i think. I'll stick with a one shot, seems easier. StephenArticle: 80462
Hi all,
I'd like to create a plugin for the S3 starter kit board that adds (say)
32 or 64 MBytes of SDRAM via ports A1 and A2. Not having much experience
using (for me, at least) such high frequency parts I was wondering if it
was even possible...
I'd like to run the microblaze processor synchronously, so clock
frequency will be ~87MHz. I was thinking of using plain jane SDRAM not
DDR SDRAM because it's simpler (although perhaps if I use half the cpu
clock speed, it might make it easier on the signal integrity ?) I'm
assuming that (as long as I meet the SDRAM refresh requirements) I can
scale down the frequency to suit the processor.
I downloaded XAPP134 (the only one I could find that dealt with SDRAM :)
and I'm having some problems understanding table 8, Hopefully Xilinx
won't mind me reproducing it here. The timing terms aren't defined - I
guess I'm supposed to know already. Oh well :-(
Device T(OH) T(AC) T(SU) T(HOLD) T(CYC)
SDRAM-8 3.0 6.0 2.0 1.0 8 ns (125 MHz)
Virtex 1.0 3.9 1.7 0.0 8 ns (125 MHz)
S31000 2.95 0.0 11.5ns (@ 87MHz)
To try and understand the timings, I was comparing the datasheets for
Virtex and S3, and I *think* the T(SU) of the virtex (labelled as
T(PSDLL) in the Virtex datasheets) is the same as T(PSDCM) for the S3,
SU presumably refers to SetUp. I couldn't find equivalent correlations
for OH or AC though. CYC is pretty obviously the clock frequency :-)
In any event, the worst case timings appear to be on a read cycle, where
SDRAM T(AC) + board delay + S3 T(SU) < T(CYC)
6.0 + board delay + 2.95 < 11.5
board delay < 2.55 ns
This gives hope, even with the board's physical layout resulting in the
SDRAM signal lengths being around 4 or 5 inches from the S3. Getting
source termination resistors even vaguely close to the FPGA will be
impossible though - I'm not sure how important this will be.
Any help much appreciated - am I even in the right ballpark ? I feel as
though I'm building a house of cards in an earthquake zone [grin] The
XAPP refers to IBIS models and board design tools to help, but I don't
know how to use the models or what benefits they'd give me - if they'd
be useful, I'd appreciate a pointer to a decent tutorial or 'howto'-like
document...
Thanks a bunch for any input :-)
Simon.
Article: 80463Stephen Lannard wrote: >>>Indeed there are examples, but i don't find them too helpful. They kind of >>>assume you have an idea of what you're doing and at the moment i don't. >>>:( >>> >>>I'm new to this and maybe i'm expecting too much of the 22v10. The 22V10 is at the bottom end of the scale, only the 16V8 is below it .... >> >>Depends on your likely range of X..... > > > 12ms will need 12 bits @ 1mhz i think. > I'll stick with a one shot, seems easier. Easier, but not as precise. You could also look at the ATF750, which is pin-pin with the 22V10, but has 20 Macrocells, and if physical details are not nailed down, the 32 Macrocell devices like ATF1502ASL et al... -jgArticle: 80464
Wojtek wrote: > Hello > I need information about Discret cosinus transform algorithms implemented in > FPGA structures. > > Any links, doc`s? > > Best Regards Did you check out http://www.opencores.org? Quick look I found: Video Compress: http://www.opencores.org/projects.cgi/web/video_systems/overview JPEG Hardware Compressor http://www.opencores.org/projects.cgi/web/jpeg/overview DerekArticle: 80465
Hal Murray escribió: >>I have a Spartan-3 Starter Board with an ethernet module on one of the >>expansion ports and working with EDK 6.3. >>My intention is to use the ethernet module on my project to be able to >>send/recieve TCP/IP frames using lwIP but I'm not quite sure how to map >>the pins of the ethernet module to the pins of the expansion port for >>the design to work. >>How can this be done correctly? >>It might be quite simple but I am quite a newbie on FPGA design so I >>would be very grateful for any help. > > > Get the schematics for both boards and the data sheet for the > big chip on the Ethernet card. Pick some interesting pin > on the big chip and follow it over to the connector. Find > the corresponding pin on the other connector and trace it back > to the FPGA. > > If you are lucky, you can find some documentation that does > that for you. > > Beware, it's far from uncommon to get pin numbers scrambled > on connectors. For example, pins will be numberd 1-40 on one > connector, but the corresponding pins will be numbered 40-1, > or 2,1,4,3, ... Or 1,3,5... An ohmmeter may help you trace > wires, or verify that you have things correct. > Thanks for the advice. It has been quite helpful. The big chip on the ethernet module is Ubicom IP 2022. Looking at the schematic of the ethernet module http://www.digilentinc.com/Data/Products/Net1/DmodNet1_sch.pdf I have finally reached the conclusion that the pins that need to be mapped (TX+, Tx- ,RX,...) are those that are connected that RE4,RE5,RE6,RE7,RG4 and RG5 on the IP2022 chip. OK. But, how are these pins communicated with the board's connector? After this it will be quite simple following the Spartan-3 board's connector's pins back to the FPGA. Does the ethernet module have to be programmed independedantly? I am quite stuck with this issue an I don't really know if this is the correct sequence to follow. I would really appreciate any advice. Thankyou, Adrian.Article: 80466
Where I can find that guide? Is it included into EDK 6.3i? MarcoArticle: 80467
KJ wrote: > For those (like me) who has no experience in FPGA programming, can you > suggest which SW tool(s) (free or low-cost) would be good to start with for > vendor independent learning ? Xilinx offers their free version of synthesis tool called Webpack which can be downloaded at www.xilinx.com/ise/webpack . In the webpage, you can also download a third party simulator called ModelSim for free. The free software are more than enough for beginners. Webpack supports up to 1.5 Million gates, which is quite HUGE. ModelSim free version simulates at full speed up to 500 lines of code, after that it slows down but still works. If you want to spend a little bit of money you can buy Xilinx 6.3i Student Version from Prentice Hall vig.prenhall.com/catalog/academic/product/0,1144,0131858394,00.html >From what I have been told, the Student Version is basically the same with the professional version called Xilinx ISE BaseX but at huge discount price. The only limitation is you can not use it for commercial purposes and you are not eligible for tech support. The software are very much vendor independent, as long as you don't use the vendor specific primitive library or the Core Generator. Just use standard Verilog or VHDL keywords. Altera also offers their free old software called MaxPlusII and newer one called Quartus. But the simulator that comes with MaxPlusII has severe limitation, it doesn't supports testbench at all. I won't recommend it for anyone. Perhaps the free version of Quartus doesn't have such limitaton, I don't know, you can try. HendraArticle: 80468
<Marco> wrote in message news:ee8c76b.-1@webx.sUN8CHnE... > Where I can find that guide? > > Is it included into EDK 6.3i? I'm not sure if this is what you're looking for or not but ... UG111: Embedded System Tools Reference Manual http://www.xilinx.com/ise/embedded/est_rm.pdf I'd agree that this isn't an easy document to find on the Xilinx web site. I'll see what we can do to remedy this. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 80469
"paul" <paul_sereno@hotmail.com> wrote in message news:1110062577.195830.218960@o13g2000cwo.googlegroups.com... > > Any of you has concrete numbers of the insurge current for the > XC3S1000? how long does it take to go through the high current period? > > I'll appreciate any feedback. Any of the more modern Xilinx architectures (Virtex-II, Virtex-II Pro, Spartan-3/-3E) do not have a power-on surge current requirement in order to power on the FPGA. The current requirements are essentially the same as the maximum quiescent requirements listed in the data sheet. For example, the XC3S1000 limits are described in Table 7, page 5 of the following document. http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 80470
"Simon" <news@gornall.net> wrote in message news:ZPKdnUHu3bmT1LbfRVn-rw@comcast.com... > Hi all, > > I'd like to create a plugin for the S3 starter kit board that adds (say) > 32 or 64 MBytes of SDRAM via ports A1 and A2. Not having much experience > using (for me, at least) such high frequency parts I was wondering if it > was even possible... > [ ... snip ... ] While it _may_ or may not be possible, I'd recommend against it. The A1 and A2 connectors are not well suited to high-frequency signals. There are few ground connections. The best use of time and money is probably to use one of the other Spartan-3 development boards on the market that already include SDRAM or DDR RAM already designed into the board. Here are a few examples. I'm sure that there are others out there. NuHorizons HW-AFX-SP3-400-DB ($199) http://www.nuhorizons.com/products/xilinx/spartan3/development-board.html XC3S400, 64Mbits SDRAM XESS XSA-3S1000 ($199) http://www.xess.com/prod035.php3 XC3S1000, 32Mbyte SDRAM Memec Design Spartan-3MB ($795) http://www.memec.com/?cmd=detail&articleid=1479 XC3S1500, 16Mx16 DDR SDRAM --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.Article: 80471
Hi there, I am actually trying to develop an FPGA design with EDK 6.3 to work on a Spartan-3 Starter board with a Digilent NET1 Ethernet Module connected to one of the expansion ports. I have included an opb_eternetlite core on my hardware design to access control of the ethernet module. Could anoyone explain which ethernetlite net ports should de included in the design and which should be declared external? About the external ports, how should these be declared in the .ucf file? Has anybody acheieved interfacing the external NET1 module correctly on an EDK design? I woud be very grateful for any advice on this respect. Thnakyou in advance. Adrian.Article: 80472
>>>>I'm new to this and maybe i'm expecting too much of the 22v10. > > The 22V10 is at the bottom end of the scale, only the 16V8 > is below it .... I chose the 22v10 because it was a basic unit, I hoped to learn on this before embarking upon anything of note. I'm basically trying to replace a timing pulse and a bunch of ttl logic as my first step into PLD. > Easier, but not as precise. > You could also look at the ATF750, which is pin-pin with the 22V10, but > has 20 Macrocells, and if physical details are not nailed down, the 32 > Macrocell devices like ATF1502ASL et al... If I manage to work out this CUPL those chips will be added to my list of things to play with :-) It's proving a little difficult at the moment to grasp the language. StephenArticle: 80473
Steven K. Knapp wrote: > "Simon" <news@gornall.net> wrote in message > news:ZPKdnUHu3bmT1LbfRVn-rw@comcast.com... > >>Hi all, >> >>I'd like to create a plugin for the S3 starter kit board that adds (say) >>32 or 64 MBytes of SDRAM via ports A1 and A2. Not having much experience >>using (for me, at least) such high frequency parts I was wondering if it >>was even possible... >> > > [ ... snip ... ] > > While it _may_ or may not be possible, I'd recommend against it. The A1 and > A2 connectors are not well suited to high-frequency signals. There are few > ground connections. Mmm. I meant to ask about that actually - I've seen it raised before. I was intending to use the starter kit board to develop/debug individual peripherals before taking the plunge and building my own. It seemed to be easier to debug any problems on a known-working board - just to remove one of the variables. > The best use of time and money is probably to use one of the other Spartan-3 > development boards on the market that already include SDRAM or DDR RAM > already designed into the board. Here are a few examples. I'm sure that > there are others out there. > > NuHorizons HW-AFX-SP3-400-DB ($199) > http://www.nuhorizons.com/products/xilinx/spartan3/development-board.html > XC3S400, 64Mbits SDRAM > > XESS XSA-3S1000 ($199) > http://www.xess.com/prod035.php3 > XC3S1000, 32Mbyte SDRAM > > Memec Design Spartan-3MB ($795) > http://www.memec.com/?cmd=detail&articleid=1479 > XC3S1500, 16Mx16 DDR SDRAM I've been looking - the problem is that all of them seem to use a 16-bit interface to memory, and while I could write an interface that fetched 2 words before returning it to the microblaze (use burst mode, hold of RDY until both returned, done), it wouldn't model what I ultimately want, and of course it'd be slower :-( The Xess one was looking perfect (the '1000 part, SDRAM, no ethernet, but it had enough pin headers to add it). It even had a 3 bit/colour VGA resistor DAC rather than the S3 1 bit/colour interface. But the memory is only 16-bit. Why, Dave, WHHHYYYyyyy? [grin] The to-be-released S3E starter kit has 32MB DDR SDRAM (though whether it'll be 32-bit wide remains to be seen), but the Xilinx board is 'only' half the size, using the 500k part. I assume others (digilent) will step in and up the gate count. There's the broaddown-2 board (except I've just moved away from the UK to the US, typical!), with tantalising hints of a lower-cost version being released soon. Even the AVnet S3 development kit board ($750) has a 16-bit interface to the SDRAM (but a 32-bit interface to its' SRAM!) These guys have no excuses, there are god-knows-how-many spare i/o on that board ... [Sigh], if the ground issues on A1/A2 are likely to cause problems, then perhaps the slow-but-steady double-read approach might be better... Cheers, Simon.Article: 80474
"Alex Gibson" <me@privacy.net> wrote in message news:38vqkjF5s3au9U1@individual.net... > > Xilinx S3 starter kit is a lot cheaper US$99 versus US$236 Hmm, yes, that is a big difference. What's the explanation? Are Digilent selling them at cost price? Tony seems a fair guy, I doubt he would overcharge. > but Tony Burch does free FPGA replacement if you blow your chip up. That's reassuring to know. Personally I like the physical format of the BurchEd boards. If I were to make a project with LEDs and switches I would want to have them mounted where I want and in my choice of colours, not fixed on the FPGA board itself. The less pins the FPGA decides to use, the more freedom I have to use them. > also a S3e board on the way from DigilentInc / Xilinx > http://www.xilinx.com/products/spartan3e/s3eboards.htm
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