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We have a NIOS design running at a clock speed of 92 MHz in a Stratix part that will have Flash and SRAM. All of our program memory is to reside in SRAM(IDT714V416L) after boot from flash. We are able to run the debugger on one out of 10 of our boards but the other 9 seem to be having problems just getting started. Almost looks like we are in a permanent reset(reset has been verified to be inactive). We did a test on one of the non working boards by puting a little "Hello World" test in onboard M4K and that worked fine but will not run the same test running form SRAM. To me this points to timing problems acessing SRAM. Aother thing that is puzzling is that when you look at the memory through the debugger, it appears that the SRAM has correct data in it. Am I getting fooled by the debugger somehow? We also run the Altera memory test which supposedly verifies the SRAM interface and that works correctly. We do not have any constraints on any of the I/O going to the SRAM/Flash. The assumption is that since these are registered I/O that it would not be necessary. Is this assumption correct? Any help would be appreciated resolving this issue.Article: 80601
First I apologize for a typo: FULL gets reset by the read clock (of course,not the write clock!) The fall-through FIFO that you mention was my Fairchild 3341 design (or copy thereof). It was a real self-clocking asynchronous shift register. AMD later second-sourced it, but further FIFOs were all dual-ported-RAM based. I have fiddled with FIFOs for 35 years. And the best one (and the most thoroughly tested one) is the FIFO controller in every Virtex-4 BlockRAM. 500 MHz asynchronous operation, tested with 10e14 "asynchronously-going-empty" cycles, and no glitch! Peter Alfke, Xilinx ApplicationsArticle: 80602
Peter Alfke wrote: (snip) > I have fiddled with FIFOs for 35 years. And the best one (and the most > thoroughly tested one) is the FIFO controller in every Virtex-4 > BlockRAM. 500 MHz asynchronous operation, tested with 10e14 > "asynchronously-going-empty" cycles, and no glitch! Asynchronous, meaning to phase relationship between the two clocks? (And hope they don't phase lock by themselves.) How about a PLL to lock onto exactly the worst part of the cycle to make the transition? I am not so sure what to put into the phase comparator, but it would seem that it might be possible. -- glenArticle: 80603
Why? The two clocks can have any frequency or phase relationship, or non-relationship. That's what I mean by asynchronous. But both should be a reasonably steady stream of clocks. Need not be of a fixed frequency. And all that only to resolve FULL and EMPTY. Otherwise you can use any clocks or strobes you want. Peter AlfkeArticle: 80604
We compile newlib with -mrelocatable-lib option. This produces code that contains pointers stored in the .text, instead of the .data. Since, reading from the OCM on Virtex 2P is not supported, such code will not work. malloc is one of our library routines that will fail. This is a known limitation. Please move such library routines into other readable memories. Then your code will work. thanks, netpit wrote: >Hello, > > I use a Virtex II Pro Development board (2VP7 - FG456 Rev 3) with XPS and >ISE version 6.2.03. Since I use OCM memory instead of PLB or OPB memory , >the malloc functions doesn't work anymore (the program write it on SDRAM >memory instead of D-OCM). Also, I don't understand where are exactly the >stack, heap and data zone ? (in spite of the LinkerScript file). > >Does someone have the same problem as me or know why? > > > >Best Regards > > > >Pierre > >Article: 80605
"Peter Alfke" <peter@xilinx.com> writes: > FULL gets set by the write clock, which is ideal, since only the write > side is interested in FULL. > But FULL gets reset by a write clock, and that is inherently > asynchronous to any write operation. Unless I'm very confused, you must have meant to write that FULL gets reset by a read clock.Article: 80606
"Peter Sommerfeld" <psommerfeld@gmail.com> wrote in message news:1110295700.990283.300930@f14g2000cwb.googlegroups.com... > Great, thanks for the link. Their results are that the sync and async > versions of the same processor have the same area, speed, and power > consumption except that the async version apparently has less EMI. I > was hoping the async design would have advantages in other areas, but I > guess not. Don't give up hope yet. One guy tried making an asynch version of the ARM, called Amulet. The first attempt actually used _more_ power than the synchronous ARM! Later attempts used less power, after he'd sussed the reasons. I get the feeling things will have to go asynch eventually, if only to get rid of a 40W RF transistor thrashing a global clock network.Article: 80607
"Kryten" <kryten_droid_obfusticator@ntlworld.com> wrote in message news:PGtXd.744$n33.40@newsfe4-gui.ntli.net... > > I get the feeling things will have to go asynch eventually, if only to get > rid of a 40W RF transistor thrashing a global clock network. > The first field buffer I used (in 1976) took 60 Amps of clock at 12 MHz.Article: 80608
"Pete Fraser" <pfraser@covad.net> wrote in message news:112ssmdbnlbe11e@news.supernews.com... > The first field buffer I used (in 1976) took 60 Amps of clock at 12 MHz. Crikey. Do tell more! Regarding CPUs, I think there is much more scope for efficiency. Even without moving to asynch CPUs. As I type this on my laptop, the fan is still blowing. A friend of mine knows the Psion very well, and says it spends almost all its time asleep waiting for events to wake it up - eg. keypresses. On a PC, there is always a display controller accessing loads of pixel data. Maybe that should be tackled first? K.Article: 80609
As Jim says, for embedded apps, lower EMI, less heat are good things to do but for high perf Async design is IMHO a wasted effort. This issue comes up every so often, some think async will cure the ills of digital design, to show for its results there is very little. There is one little company in San Diego IIRC that does async asics, even a couple of pretty die shots on site, and there was the Amulet and a book or two. SInce as Peter/Xilinx keep saying the asic is dead and long live the FPGA, we have to stick with global clocking, even more so for FPGA than Asics for obvious reasons. Atleast with Asics you could hand craft everything so you could justify any clocking, power management scheme to get the job done Also look at the EDA world, name a single async tool vendor out there. Also consider that par busses are dying and getting replaced by the fastest possible serial busses, its one thing to do async sub clock busses, can't see how you could do PCIe, Sata, FW, USB2/3 in a async world. I f that damn Moore guy hadn't had that "double every 18months" comment we might still be exploring 1ucmos design space and then async design actually would have a place to shine but we're are in a geometry rat race and async lost its chance to make any real show. just my 2c regards johnjakson at usa dot comArticle: 80610
Hi All, Do you know what are the advantages and disadvantages / differences between the FPGA development tools such as Actel Libero IDE, Xilinx ISE and Altera MAX+PLUS II? Thanks.Article: 80611
<spacexxspace@yahoo.com> schrieb im Newsbeitrag news:6219c8d3.0503082229.7239af9d@posting.google.com... > Hi All, > > Do you know what are the advantages and disadvantages / differences > between the FPGA development tools such as Actel Libero IDE, Xilinx > ISE and Altera MAX+PLUS II? > > Thanks. YES. 1 Libero is real pain 2 MAX+PLUS is obsoleted (replaced by Quartus) 3 ISE just works Antti PS Quartus is OK tooArticle: 80612
Hi You can get Service Packs at http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp But you must first Register!Article: 80613
Hi Kirilov Ok, i'm now experiment on the DMA too. The Problem is, i think that you know, that this Area is new and thera are not so mutch tutorials on this. But that is no problem, because we have this super portal :-), but what i want to say that what you want to know is too mutch for short description and than you need a good tutorial. What i see, you have general problems to understand the IPIF. I saggest you to try at first simple thinks how Interrupt, some registers system and so on becaue the dma is a little bit difficulter. And when you get this, you can try the DMA. Until yet i understand DMA so: The DMA Register control the IPIF DMA. This register must you setup via software on you programm. The addresses (source and destination) must you setup witch registers, too. When I get a Tutorial i will say to you! cauArticle: 80614
> 3 ISE just works > PS Quartus is OK too Soon, the free ISE Webpack 7.1 will be released with linux support ! When will we have a Linux Quartus web edition ? SylvainArticle: 80615
B. Joshua Rosen wrote: > > They screwed up the installer on 7.1 and made it distribution dependent. > Specifically the installer requires some out of date libraries. I wasn't > able to install 7.1 on Fedora Core 3 or Mandrake 10.1 because of library > issues. I ended up putting Whitebox Linux on one of my older machines > (Whitebox is RHEL 3.0) and doing the install there. Once I'd done the > install on the WB system I rsynced the directory over to my FC3 systems > and it works fine. The tools themselves don't seem to have any > distribution dependencies, the cock-up is limited to the installer. I wonder if xilinx could provide an updated installer (only) so that we all could install the tools on our favorite linux distro. It should be just a recompile of xilsetup ... How about it ? I'll volunteer to beta test on 32 and 64 bit AMD platforms ... Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 80616
As you said "this is a known limitation", can you tell me where this is written in the documentation ? (I knew the IOCM is a 32-bit write only port for the Virtex II Pro but I didn't read anything about relocation). thanks Pierre Vasanth Asokan <vasanth.asokan@xilinx.com> wrote in message news:<422E5CDA.6080206@xilinx.com>... > We compile newlib with -mrelocatable-lib option. This produces code that > contains pointers stored in the .text, instead of the .data. Since, > reading from the OCM on Virtex 2P is not supported, such code will not > work. malloc is one of our library routines that will fail. This is a > known limitation. Please move such library routines into other readable > memories. Then your code will work. > > thanks, >Article: 80617
Hi newsgroup people, one question regarding global reset paths in different FPGAs: I have found out that in the new EC/ECP FPGAs from Lattice there is only one global asynchronous reset paths. There is one component called "GSR" (global set / reset) which has to be fed with the reset signal which is used as global asynchronous reset. This component can be instantiated only once in the top level. So what about the idea to synchronize one asynchronous reset signal into different clock domains ? If there is only one global reset paths the synchronization with different clocks would make no sense then ? What about Altera and Xilinx FPGAs ? Do they have more than one global reset path ? Thank you for your information. Rgds AndrésArticle: 80618
"Ben Twijnstra" <btwijnstra@gmail.com> wrote in message news:W2oXd.336885$PH1.270015@amsnews05.chello.com... > Hi Jock, > > > For the Xilinx we used the .rbt file which is an ASCII version of the .bit > > file. > > > > Does anyone know what the Altera equivalent of the .rbt file is? > > That would be the .ttf file. You can find it under > Assignments->Device->Device and pin options->Programming files. > > Best regards, > > > Ben > Thanks for that Ben, after a bit of debugging on Labview, we've managed to get the .ttf file to work.Article: 80619
Worth looking at Platform Flash for size and price. Usually much cheaper than the older programming prom families. If this is a new board then go the further stage and use Spartan-3 your design. You will have to protect the Spartan-3 against 5V and may need 5V level shift if you have 5V CMOS level logic but you will benefit still from cost savings etc. Spartan-2E will need the similar protection and level shifting so no advantage over Spartan-3 in this respect. Spartan-2E is generally dearer than Spartan-3. It is also worth getting in contact with the Xilinx University Program if you are a student or within an academic department. They can help out various aspects FPGA selection etc. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Jon Elson" <jmelson@artsci.wustl.edu> wrote in message news:422E2EC2.6000401@artsci.wustl.edu... > Hello, all, > > I am working on an update for a board that now uses an original 5-V Spartan > (XCS30) part. To reduce cost, I'm looking at using the Spartan II XC2S30 > part, which is less than half the price. (I'd go with the Spartan IIE, > but the smallest > is 50K gates, and config bitstream is about double the 2S30's > requirement, which > negates the price advantage.) Anyway, there are some 512KBit serial PROMs > available from some other makers that are 1/10th the cost of the Xilinx > parts. > But, they max out at 400 Kbits/second, and the SpartanII starts > configuring at > 2.5 MBits /second in master serial mode. I think I have come up with a very > simple circuit to divide my system clock down and sync INIT/ to it, so > that I can > run the SpartanII in slave serial mode with a clock rate appropriate for > the slow > SPROM. I think I can do it in 2 74HCxx packages. Does anyone have any > comments > on this? Have you done something similar? > > (This particular product has no CPU onboard. I suppose I could come up > with a way > to configure the FPGA from a host CPU, but there are a few reasons I > might want > to avoid that.) > > Thanks, > > Jon >Article: 80620
Hi Swamy, swamydp@yahoo.com wrote: > Hi > > what algorithm does xpower use to calculate the freqency of internal > nodes in a netlist ? is it some kind of transition density propagation > but that method requires activity factor for primary inputs and also > probabilities of primary inputs. > > Also is the interconnect power dissipation taken into account ? The most basic method is through user i/p. Others include importing simulation information and also the use of a probability algorithm in how primary i/ps are propagated. The interconnect power dissipation is definitely taken into account. Brendan > > > Thanks for any help > swamyArticle: 80621
Paul, Hang on, isn't this easy? Only the write side is interested in the Full Flag, right? The write side is throttled. That makes it a lot easier. So, you have a binary coded incrementing write pointer. It points to where the next data will be stored. You have a binary coded incrementing read pointer. It points to where the next read comes from. Use a combinatorial comparison to see if the read pointer is one more than the write pointer. If so, report full to the write side. This 'full flag' can only be seen as metastable by the write side if a read has just happened. In which case write or don't write doesn't matter. There will be space. On the read side use a combinatorial comparison to see if the read pointer is equal to the write pointer. This means empty. This 'empty flag' will only be seen as metastable by the read side if a write has just happened. In which case a read or not read cycle is OK, there will be data to read. No Gray code nonsense needed as long as you don't mind a few transient false fulls and empties. You could add extra stuff if you wanted to fill the thing right to the brim, because then the full and empty conditions both have the pointers equal. You also need to make sure, when empty, the write cycle completes before the read side can see the 'empty flag' go away. And vice-versa. Cheers easy, Syms. p.s. My spell checker suggests detestable instead of metastable. How appropriate! "Paul Davis" <rft56@dsl.nospam.pipex.com> wrote in message news:a5tr21drgcgc5k6okiakgf22cjv0646of1@4ax.com... > Yet another async FIFO question... :( > > I've inherited an async FIFO that doesn't work. This is, I think, a > fairly standard implementation. On the write port, a clock and a write > enable increment a write pointer, and write the write data into a RAM. > > The read pointer is Gray-coded, clocked into a reg on the write clock, > inverse coded, and then compared with the write pointer, to give a > write-side full flag. > > The read side is simply the inverse of the write side. > > So far, so good. The problem is that this design assumes a > free-running write clock, and my write clock is not free-running; I > simply generate a clock when the (unpredicatable) write data appears. > The write enable is therefore effectively redundant. > > The problem arises because the 'fifo full' flag is generated by the > *write* clock. If, on write X, the comparator determines that the FIFO > is full, then the full flag is generated, and I don't create any more > write clocks. The read side might empty the FIFO, but this information > never gets back to the write port, because the register that samples > the Gray-coded read pointer is clocked by the write clock. > > Any ideas on how I re-design this to cope with a write clock which > isn't free-running? > > TIA - > > PaulArticle: 80622
Ulrich Kloidt wrote: > Hello Jens, > > Altium is offering an eval board with a Xilinx® SpartanT-3 FPGA Device > (XC3S400-4FG456C) for EUR 99,-. You can order it from the local Altium > office located in germany. More info about this board is available at: > > http://www.altium.com/livedesign/ > > It comes with a 1 moth eval license of the Altium Nexar Software. But in > case you don't want to purchase the Nexar software afterwards you can > still use the board as a 'normal' evaluation board together with the > Xilinx software. Yes, I found this board yesterday and I think, I will order it. Does Altium somewhere confirm, that the board is usable with the Xilinx software? JensArticle: 80623
Hello people. Since some of you started asking about the Java programs I use to control the BSC registers in my designs that I mentioned in a post last week, I have released them as a Java.net project. The official URL is http://jjtag.dev.java.net/, but while it receives approval you can access a temporary repository at my web site, http://bleyer.org/jjtag/. Basically, the tool consists of a JTAGController class that defines the API and works over 'String' or 'Bits' objects. There is an example for a JNI Wiggler-like parallel port interface that implements the TAP pins control routines. There is also a 'Scan' utility class that packs/unpacks JTAG bitstreams and aids in the development of boundary scan register descriptions. The complete package has been licensed under the BSD license. It has been used successfully to implement an ARM JTAG/ICE debugger and debug interfaces for a couple of custom FPGA designs. I also have a USB JTAGController class that uses my jd2xx package with FTDI USB chips via their MPSSE interface (http://jd2xx.dev.java.net/). I look forward to release it as soon as I work out some licensing issues with my previous employer (which reminds me -- I could really use some knowledge about currently open positions ;) ). Don't hesitate to write me if you have any questions or problems using it. Enjoy. -- PabloBleyerKocik / pablo /"Simplicity is prerequisite for reliability." @bleyer.org / -- Edsger Wybe DijkstraArticle: 80624
Andy Main wrote: > > I looked on the web for XCF01SVO20C and got a web price of $3.15 > >> If this is expensive to you, I don't see what you're going to do with >> the AT29 flash. This is a 1Mbit part big enough to program about 5 >> of your XC2S15's if you chain them. It has JTAG and works with the >> Xilinx iMPACT software. Good luck doing better with less effort. > > > Much better, though I can't find any in the UK (RS/Farnell) - only the > huge Virtex proms that made me think all this in the fist place. If > anybody knows a suitable supplier for low quantity purchases please let > me know. I'd be very grateful. > > Andy. Hi Andy, Maybe goto www.nuhorizons.com Laurent Gauch www.amontec.com
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