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Messages from 71675

Article: 71675
Subject: Re: New WinFilter Digital Filter design freeware tool release available.
From: Ray Anderson <reanderson@sbcglobal.net>
Date: Tue, 27 Jul 2004 14:23:39 GMT
Links: << >>  << T >>  << A >>
I was able to download it fine to my XP system running Mozilla, but when 
trying on a Win98 system with the same browser I get a cryptic error 
message.

-Ray Anderson


Article: 71676
Subject: Re: New WinFilter Digital Filter design freeware tool release available.
From: phuture_project@yahoo.fr (phuture_project)
Date: 27 Jul 2004 07:36:52 -0700
Links: << >>  << T >>  << A >>
> There are two downloads, one works and one doesn't.

Yes but the version i want to downlaod is the 0.7 .

Article: 71677
Subject: Re: IOBs in NGC - problem with OBUFT
From: Brian Philofsky <brian.philofsky@no_xilinx_spam.com>
Date: Tue, 27 Jul 2004 10:03:57 -0600
Links: << >>  << T >>  << A >>


Joko wrote:

> Using .ngc files for sub-modules would be a good solution - not only
> in your case !! But problems arises soon after you try it - not only
> with the iobufs:
> i.e.: how do you want to provide a 'good' simulation-netlist?
> backannotating your netlist to a vhdl-netlist using "ngdbuild" and
> "netgen" results in a very poor performance of your simulation,
> because of the timing-information within that simulation-netlist
> driving modelsim 'almost' crazy...
> Any tips from "xilinx", how to use this interesting design-flow?
> 
> Cheers
> Joko


There is an unsupported flow now that is better than ngdbuild --> netgen 
and there will be a better supported flow soon for this.  In the 6.2i 
software, there is an executable called ngc2hdl than can transform an 
.ngc file to a UNISIM-based structural VHDL or Verilog file.  The UNISIM 
library does not contain timing and is a bit faster and easier to use 
than the SIMPRIM-based structural netlist you would get after ngdbuild. 
  I mention this is an unsupported flow which means that it is there and 
you can use it and if you have any problems you can even file bugs but 
we may not be as responsive in answering questions or fixing problems 
with this as we would with a standard flow and it is a some-what "use at 
your own risk" flow.  It is also an undocumented flow at this time 
however fairly easy to figure out yourself.  To my knowledge there is no 
problems with ngc2hdl however it is new and we did not want to open the 
flood gates to its use yet so it is not advertised, documented and not 
officially supported by Xilinx.

In a future release, we plan to integrate ngc2hdl into netgen so that 
you can run netgen directly on the ngc file and get the UNISIM netlist 
and at that time it will be officially supported.  We will remove 
ngc2hdl (which we can do more easily since it was never officially 
supported or documented).  We also have some enhancements around the 
corner for the UNISIM library that should significantly improve its 
speed over today and thus give an even faster simulation netlist 
although it likely never will be close to the speed of a true behavioral 
or RTL model.  I do suspect it will be very usable however for IP like 
this and should enhance the use of ngc files over what can be done today.

Xilinx is working towards continually improving simulation and this is 
only one facet of some of the improvements you will be seeing in future 
releases.  If you have any ideas for improvements or feedback on 
simulation, you can send them directly to me and I guarantee they will 
be read and considered.  It is my job to do the future planning for 
Xilinx simulation and I am always open to hear feedback from users to 
assist in my work.


--  Brian Philofsky
--  Xilinx Technical Marketing




Article: 71678
Subject: ramdon noise generation
From: linical@yahoo.com (linical)
Date: 27 Jul 2004 10:24:15 -0700
Links: << >>  << T >>  << A >>
I need to use FPGA to generate a normal distributed noise. Any idea? I
know that we can convert a even distributed ramdon sequence to a
normal distributed one. But I forgot the algorithm and I am not sure
if it is suitable to implement it in a FPGA.

Article: 71679
Subject: Re: ramdon noise generation
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 27 Jul 2004 10:47:30 -0700
Links: << >>  << T >>  << A >>
1) Take FPGA and remove its legs.
2) Use a marker to write 'Heads' on one side, 'Tails' on the other.
3) Throw it up in the air.
4) See which side lands face up.
5) Repeat 3) and 4) until you have enough data.

Or try Google / Google Groups for LFSR, Random, etc. ;-)
Also check out the Random article here
http://www.xilinx.com/xlnx/xweb/xil_tx_home.jsp

HTH, Syms.

"linical" <linical@yahoo.com> wrote in message
news:885ef3e9.0407270924.53025943@posting.google.com...
> I need to use FPGA to generate a normal distributed noise. Any idea? I
> know that we can convert a even distributed ramdon sequence to a
> normal distributed one. But I forgot the algorithm and I am not sure
> if it is suitable to implement it in a FPGA.



Article: 71680
Subject: On-Chip Oscillator
From: dhruvish@gmail.com (Drew)
Date: 27 Jul 2004 10:52:41 -0700
Links: << >>  << T >>  << A >>
Hello Guys,

Have anybody tried to make On-Chip Oscillator on Altera EPLD/CPLD? I
am using Altera Max family parts. I was wondering we can program it
using VHDL? Another question I have is, How do I reduce the Rise Time
of clock output from CPLD? I need rise time of < 2ns. I need external
circuitry but not sure what?

Feedback please!
Drew

Article: 71681
Subject: Re: xilinx ngdbuild old command flow problem
From: accellera2@yahoo.com (Pine)
Date: 27 Jul 2004 11:07:07 -0700
Links: << >>  << T >>  << A >>
Duane, thanks for your help.

So you means I need to re-install webpack through wine? Or I just need
to run that .xinstall/setup.exe.

I wonder if you know any specific file I missed under wine (Did
installer put some files under system32)? Then I can copy them and
try.

Thanks a lot,

PZ
Duane Clark <junkmail@junkmail.com> wrote in message news:<cdm2r112klu@news3.newsguy.com>...
> Pine wrote:
> > I'm using ise webpack 6.2.03i through wine on redhat 9.
> > 
> > ...
> > Or does I miss any file in linux? I just copied the whole folder of
> > ise6 to my linux machine.
> > 
> 
> You really need to run the Webpack installer under Wine.

Article: 71682
Subject: Re: 1GHz FPGA counters
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 27 Jul 2004 11:17:01 -0700
Links: << >>  << T >>  << A >>
Here are my thoughts for a fairly simple implementation. If I recall, the
original post asked for a report of the arrival time of input pulses (let's
assume rising edges) with a resolution of 1 ns.

I suggest a synchronous design running at 250 MHz (synchronous counter,
transfer to BlockRAM etc) augmented with a small "prescaling" front-end.
The input line gets clocked into four flip-flops in parallel, each clocked
on a different quadrant of the 250 MHz clock. Using the flip-flop clock
polarity option, this requires only two global lines driven by one DCM.

Now that we have captured the input edge in 4 flip-flops, we have to figure
out where it was captured first. For that, we must move the four staggered
signals into the same clock domain, and we should move any signal only by a
quarter clock per step (to avoid excessively tight delay requirements). This
takes half a dozen flip-flops, followed by a 1-of-4 decoder that defines the
position of the leading edge, and is used as the two LSBs for the timer.

This circuit would have problems if two pulses arrive within 4 ns, but I
hope that is physically impossible.

Counter trickery is really not necessary. It's all synchronous to 250 MHz.
 It's only the sub-one-nanosecond resolution that requires some trickery.

Peter Alfke

> 


Article: 71683
Subject: Re: xilinx ngdbuild old command flow problem
From: Duane Clark <junkmail@junkmail.com>
Date: Tue, 27 Jul 2004 12:42:37 -0700
Links: << >>  << T >>  << A >>
Pine wrote:
> Duane, thanks for your help.
> 
> So you means I need to re-install webpack through wine? Or I just need
> to run that .xinstall/setup.exe.

You should run the entire installer.

> 
> I wonder if you know any specific file I missed under wine (Did
> installer put some files under system32)? Then I can copy them and
> try.
> 

The installer puts a lot of registry entries in the registry. I suspect 
that is the problem, though I don't know for sure. In general, the main 
the you want to copy over from Windows is msvcrt.dll, and configure Wine 
to use it.

I guess I don't understand why you would not want to run the installer. 
It only takes a couple of minutes.

-- 
My real email is akamail.com@dclark (or something like that).

Article: 71684
Subject: Re: ramdon noise generation
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 27 Jul 2004 13:23:04 -0700
Links: << >>  << T >>  << A >>
Symon,

Your method is greatly flawed.  In addition to being very slow, it is 
subject to the imbalance of the weight of the device.  You would first 
have to add weight or trim weight to make sure the toss was fair.

Better to implement something a bit more elegant:

http://support.xilinx.com/xlnx/xweb/xil_tx_home.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1209667&iLanguageID=1

"That is So Random!"

Austin

Symon wrote:
> 1) Take FPGA and remove its legs.
> 2) Use a marker to write 'Heads' on one side, 'Tails' on the other.
> 3) Throw it up in the air.
> 4) See which side lands face up.
> 5) Repeat 3) and 4) until you have enough data.
> 
> Or try Google / Google Groups for LFSR, Random, etc. ;-)
> Also check out the Random article here
> http://www.xilinx.com/xlnx/xweb/xil_tx_home.jsp
> 
> HTH, Syms.
> 
> "linical" <linical@yahoo.com> wrote in message
> news:885ef3e9.0407270924.53025943@posting.google.com...
> 
>>I need to use FPGA to generate a normal distributed noise. Any idea? I
>>know that we can convert a even distributed ramdon sequence to a
>>normal distributed one. But I forgot the algorithm and I am not sure
>>if it is suitable to implement it in a FPGA.
> 
> 
> 

Article: 71685
Subject: Re: ramdon noise generation
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 27 Jul 2004 14:09:33 -0700
Links: << >>  << T >>  << A >>
Austin,
That's why Actel devices are superior to Xilinx FPGAs in this application.
You can keep blowing fuses until the part 'balances'.
As for the slowness of the method, you guys at Xilinx are always saying how
FPGAs can speed things up using parallel processing. Just get 1000 parts,
and throw them all at the same time.
Cheers, Syms.
p.s. Good TechX article, BTW!
"Austin Lesea" <austin@xilinx.com> wrote in message
news:ce6dhn$r892@cliff.xsj.xilinx.com...
> Symon,
>
> Your method is greatly flawed.  In addition to being very slow, it is
> subject to the imbalance of the weight of the device.  You would first
> have to add weight or trim weight to make sure the toss was fair.
>



Article: 71686
Subject: Re: ramdon noise generation
From: Pierre Wadier <peewee@melix.net>
Date: Tue, 27 Jul 2004 23:26:48 +0200
Links: << >>  << T >>  << A >>
There are at least two methods :

1) generate normaly distributed samples (quantized box-muller algorithm),
add a few of them (4 may be enough), according to the central limit
theorem, it increases the generator's precision

here is an interesting paper 
http://lester.univ-ubs.fr:8080/~boutillon/articles/ICECS_00_Emul.pdf


2) set the quantization of the noise you wish to produce, generate tables
storing values of the integrated density of probability (by software).
To generate a noise sample, generate uniformly distributed samples, search
in the tables for the nearest element and return this element's index. The
indexes returned should be normaly distributed. This is sometimes called the
thresholds method.

I may not be very clear but it works perfectly (I've tried it)

Pierre



Article: 71687
Subject: Re: On-Chip Oscillator
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Tue, 27 Jul 2004 22:45:58 +0100
Links: << >>  << T >>  << A >>
"Drew" <dhruvish@gmail.com> wrote in message
news:ad2011c0.0407270952.23895c31@posting.google.com...
> Hello Guys,
>
> Have anybody tried to make On-Chip Oscillator on Altera EPLD/CPLD? I
> am using Altera Max family parts. I was wondering we can program it
> using VHDL?


I vaguely remember trying something like this a few years ago by creating
two inverters and using them to implement an oscillator with a crystal and a
couple of resistors.

Leon



Article: 71688
Subject: Re: ramdon noise generation
From: nweaver@soda.csua.berkeley.edu (Nicholas Weaver)
Date: Tue, 27 Jul 2004 22:17:04 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <ce6dhn$r892@cliff.xsj.xilinx.com>,
Austin Lesea  <austin@xilinx.com> wrote:
>Symon,
>
>Your method is greatly flawed.  In addition to being very slow, it is 
>subject to the imbalance of the weight of the device.  You would first 
>have to add weight or trim weight to make sure the toss was fair.

Nah, a biased coin is perfectly fine:

Flip twice:
HH -> try again
HT -> Heads
TH -> Tails
TT -> try again.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 71689
Subject: Re: ramdon noise generation
From: Austin Lesea <austin@xilinx.com>
Date: Tue, 27 Jul 2004 15:18:33 -0700
Links: << >>  << T >>  << A >>
Symon,

Gosh, I never thoguht of that:  throw a million devices into the air at 
once!

Austin

Symon wrote:
> Austin,
> That's why Actel devices are superior to Xilinx FPGAs in this application.
> You can keep blowing fuses until the part 'balances'.
> As for the slowness of the method, you guys at Xilinx are always saying how
> FPGAs can speed things up using parallel processing. Just get 1000 parts,
> and throw them all at the same time.
> Cheers, Syms.
> p.s. Good TechX article, BTW!
> "Austin Lesea" <austin@xilinx.com> wrote in message
> news:ce6dhn$r892@cliff.xsj.xilinx.com...
> 
>>Symon,
>>
>>Your method is greatly flawed.  In addition to being very slow, it is
>>subject to the imbalance of the weight of the device.  You would first
>>have to add weight or trim weight to make sure the toss was fair.
>>
> 
> 
> 

Article: 71690
Subject: Re: 1GHz FPGA counters
From: Jim Granville <no.spam@designtools.co.nz>
Date: Wed, 28 Jul 2004 10:59:15 +1200
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> Here are my thoughts for a fairly simple implementation. If I recall, the
> original post asked for a report of the arrival time of input pulses (let's
> assume rising edges) with a resolution of 1 ns.
> 
> I suggest a synchronous design running at 250 MHz (synchronous counter,
> transfer to BlockRAM etc) augmented with a small "prescaling" front-end.
> The input line gets clocked into four flip-flops in parallel, each clocked
> on a different quadrant of the 250 MHz clock. Using the flip-flop clock
> polarity option, this requires only two global lines driven by one DCM.
> 
> Now that we have captured the input edge in 4 flip-flops, we have to figure
> out where it was captured first. For that, we must move the four staggered
> signals into the same clock domain, and we should move any signal only by a
> quarter clock per step (to avoid excessively tight delay requirements). This
> takes half a dozen flip-flops, followed by a 1-of-4 decoder that defines the
> position of the leading edge, and is used as the two LSBs for the timer.
> 
> This circuit would have problems if two pulses arrive within 4 ns, but I
> hope that is physically impossible.
> 
> Counter trickery is really not necessary. It's all synchronous to 250 MHz.
>  It's only the sub-one-nanosecond resolution that requires some trickery.

  Here is a real-world example - gives an indication of what is 
technically possible (not sure if this is entirely in a FPGA), and why 
time-domain is easier to push than frequency domain.

http://www.pendulum.se/Text.htm/CNT-90.htm

  This specs 100ps resolve, 12 Digits/sec and 300MHz std,
with prescalers to some GHz.
  12 digits/sec is == reading at 100KHz, and getting 7 digit results on 
each reading.

-jg


Article: 71691
Subject: Re: Xilinx EDK PCI
From: widding@birger.com (Erik Widding)
Date: 27 Jul 2004 17:38:33 -0700
Links: << >>  << T >>  << A >>
"Jackson Pang" <jacpang@cisco.com> wrote in message news:<1089908158.304115@sj-nntpcache-3>...
> Hello
> 
> I'd like to know if anybody had any success in using Xilinx OPB/PCI bridge
> core using EDK.  I set up the project and configured all the core parameters
> correctly. I also double checked the constraint file for pin assignments for
> the PCI finger. The compile and programming process goes well without any
> error, but I cannot even get my host PC to recognize my development board
> with the PCI bitmap. I am using Avnet's Virtex II PCI Development Board.
> Thanks for your input in advance.

Jackson,

From your other email I noticed that you are using v1_00_b of the 
opb pci.  It was our experience with this version of the core that 
the PCI target read transactions will hang the PCI bus.  This bug 
was reported Nov 2003.  I did a very cursory search of the answers 
database, and did not see an entry on the topic.

IIRC, config cycles worked okay on the core, so this is not your 
current problem.  I would recomend that you use a more recent 
revision of the core than v1_00_b.  I would assume that this bug is 
fixed by now, but you might want to ask.

As we could not wait for the bugs to be fixed, we developed a PCI 
to PLB, and PCI to OPB bridge, with DMA (pci master) support on 
the PLB side.  This core supports bursting on all but the OPB buses 
at present.  We can make this available on a commercial basis.  It
is wrapped around the Xilinx PCI logicore, which I should note is 
one of the best documented, most flexible, pieces of IP we have 
ever used.


Regards,
Erik Widding.

---
Birger Engineering, Inc. -------------------------------- 617.695.9233
100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com

Article: 71692
Subject: Re: nios-run: waiting for target.......?
From: hauyuanwen1980@yahoo.com (Jasmine Hau)
Date: 27 Jul 2004 18:07:29 -0700
Links: << >>  << T >>  << A >>
Have you try to download your hardware configuration to APEX chip
using JTAG first before you download your hardware design to APEX
using UART???

Besides, have you erase the user configuration in flash memory
content??? If i not mistaken...
  e180000
     .
     .
  e1b0000
  r180000

If still waiting for target...., try to press the reset button on the
APEX board then observe what message on Nios SDK Shell....

Article: 71693
Subject: Re: configuration SRAM cells in Xilinx/Altera FPGAs
From: rajarsheeb@yahoo.com (raj)
Date: 27 Jul 2004 21:38:07 -0700
Links: << >>  << T >>  << A >>
Thanks Rick for your inputs. 
Can you suggest some pointers regarding these?
--raj




rickman <spamgoeshere4@yahoo.com> wrote in message news:<410660E4.D29D86B6@yahoo.com>...
> raj wrote:
> > 
> > Hello  everybody,
> > 
> > I am not new to the world of FPGAs but have not found enough
> > literature regarding the SRAMs used for configuration.
> > I need  some inputs, help or pointers(papers, articles) from the FPGA
> > community
> > regarding these. There are very few literature relating to this(May be
> > I am not looking in the right places).
> > 
> > 1. Are these SRAM cells arranged in a big nxn array like normal SRAM
> > memory, or they are in small chunks of memories distributed all over
> > the  FPGA layout.
> 
> Physically they are scattered all over the chip.  Each bit of memory
> controls a single transistor or mux input in the chip.  The (pass)
> transistors are used to control routing or are used in the LUT ram mux. 
> The muxes are used inside the logic elements to connect different inputs
> and outputs to provide the exact configuration of logic and FFs that you
> need.  
> 
> > 2.Are they physically placed adjacent to their  corresponding
> > CLB/Switch
> >  boxes.
> 
> Yes, or even integrated.  
> 
> > 3. As interconnects are fixed after configuration i guess they should
> > always be read only mode, hence should be different from LUTs SRAM
> > cells.
> 
> In reality they don't typically distinguish between routing and LUT
> config memory.  Both can be read back.  This is useful for high
> reliability systems where the device is read back to verify the
> configuration has not changed due to electrical noise and/or radiation.  
> 
> -- 
> 
> Rick "rickman" Collins
> 
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 71694
Subject: vhdl code : altera vs xilinx
From: Shahab <sinamdar@mail.usf.edu>
Date: Tue, 27 Jul 2004 22:07:05 -0700
Links: << >>  << T >>  << A >>
Hi.. 

I have one question regarding xilinx ise webpack. 

Why it doesn’t give any error of type missing source code . bcoz I tried to run some codes on xilinx ise webpack and then on altera maxpllus II. 

On altera I was continuously getting messges like missing source code "C0" while the same code was running fine on xilinx tool. 

the code is : 

library ieee; 
use ieee.std_logic_1164.all; 

entity fib is 
   port (Clock,Clear: in std_ulogic; 
         Load: in std_ulogic; 
         Data_in: in std_ulogic_vector(15 downto 0); 
         S: out std_ulogic_vector(15 downto 0)); 
end entity fib; 

architecture behavior of fib is 
    signal Restart,Cout: std_ulogic; 
    signal Stmp: std_ulogic_vector(15 downto 0); 
    signal X, Y: std_ulogic_vector(15 downto 0); 
signal C : std_ulogic_vector (15 downto 0 ); 
    signal Zero: std_ulogic; 
    signal CarryIn, CarryOut: std_ulogic_vector(15 downto 0); 

begin 
    P1: process(Clock) 
    begin 
        if rising_edge(Clock) then 
             Restart <= Cout; end if; end process P1; 

Stmp <= X xor y xor CarryIn; Zero <= '1' when Stmp = "0000000000000000" else '0'; 

CarryIn <= C(15 downto 1) & '0'; CarryOut <= (Y and X) or ((Y or X) and CarryIn); C(15 downto 1) <= CarryOut(14 downto 0); Cout <= CarryOut(15); 

P2: process(Clock,Clear,Restart) 
    begin 
        if Clear = '1' or Restart = '1' then 
            X <= "0000000000000000"; Y <= "0000000000000000"; elsif rising_edge(Clock) then if Load = '1' then X <= Data_in; elsif Zero = '1' then X <= "0000000000000001"; else X <= Y; end if; Y <= Stmp; end if; end process P2; 

S <= Stmp; end behavior; 

I would like to know what is the addition in xilinx ise which altera maxplus II doesn’t have? 

Waiting for your reply. 

Shahabuddin Inamdar 


Article: 71695
Subject: Re: configuration SRAM cells in Xilinx/Altera FPGAs
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 28 Jul 2004 01:40:09 -0400
Links: << >>  << T >>  << A >>
I'm not sure what you mean by pointers.  If you mean references, then I
could recommend the data sheets.  But most of what you are asking about
is not needed to use the chips, so it is not talked about a lot.  The
readback operation is discussed in app notes mainly.  Check the Xilinx
and Altera web sites for app notes on your topic.  Also, if you can get
your hands on a paid copy of the Xilinx software, they have a chip level
editor that shows a pretty accurate layout of the chip.  But even this
will not really show you details of the config memory, it is just
assumed to be there and work invisibly.  


raj wrote:
> 
> Thanks Rick for your inputs.
> Can you suggest some pointers regarding these?
> --raj
> 
> rickman <spamgoeshere4@yahoo.com> wrote in message news:<410660E4.D29D86B6@yahoo.com>...
> > raj wrote:
> > >
> > > Hello  everybody,
> > >
> > > I am not new to the world of FPGAs but have not found enough
> > > literature regarding the SRAMs used for configuration.
> > > I need  some inputs, help or pointers(papers, articles) from the FPGA
> > > community
> > > regarding these. There are very few literature relating to this(May be
> > > I am not looking in the right places).
> > >
> > > 1. Are these SRAM cells arranged in a big nxn array like normal SRAM
> > > memory, or they are in small chunks of memories distributed all over
> > > the  FPGA layout.
> >
> > Physically they are scattered all over the chip.  Each bit of memory
> > controls a single transistor or mux input in the chip.  The (pass)
> > transistors are used to control routing or are used in the LUT ram mux.
> > The muxes are used inside the logic elements to connect different inputs
> > and outputs to provide the exact configuration of logic and FFs that you
> > need.
> >
> > > 2.Are they physically placed adjacent to their  corresponding
> > > CLB/Switch
> > >  boxes.
> >
> > Yes, or even integrated.
> >
> > > 3. As interconnects are fixed after configuration i guess they should
> > > always be read only mode, hence should be different from LUTs SRAM
> > > cells.
> >
> > In reality they don't typically distinguish between routing and LUT
> > config memory.  Both can be read back.  This is useful for high
> > reliability systems where the device is read back to verify the
> > configuration has not changed due to electrical noise and/or radiation.

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 71696
Subject: Re: vhdl code : altera vs xilinx
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 28 Jul 2004 02:01:04 -0400
Links: << >>  << T >>  << A >>
Shahab wrote:
> 
> Hi..
> 
> I have one question regarding xilinx ise webpack.
> 
> Why it doesn’t give any error of type missing source code . bcoz I
> tried to run some codes on xilinx ise webpack and then on altera
> maxpllus II.
> 
> On altera I was continuously getting messges like missing source code
> "C0" while the same code was running fine on xilinx tool.
> 
> the code is :
> 
> library ieee;
> use ieee.std_logic_1164.all;
> 
> entity fib is
>    port (Clock,Clear: in std_ulogic;
>          Load: in std_ulogic;
>          Data_in: in std_ulogic_vector(15 downto 0);
>          S: out std_ulogic_vector(15 downto 0));
> end entity fib;
> 
> architecture behavior of fib is
>     signal Restart,Cout: std_ulogic;
>     signal Stmp: std_ulogic_vector(15 downto 0);
>     signal X, Y: std_ulogic_vector(15 downto 0);
>     signal C : std_ulogic_vector (15 downto 0 );
>     signal Zero: std_ulogic;
>     signal CarryIn, CarryOut: std_ulogic_vector(15 downto 0);
> 
> begin
>     P1: process(Clock)
>     begin
>         if rising_edge(Clock) then
>              Restart <= Cout; 
>         end if; 
>     end process P1;
> 
> Stmp <= X xor y xor CarryIn; 
> Zero <= '1' when Stmp = "0000000000000000" else '0';
> 
> CarryIn <= C(15 downto 1) & '0'; 
> CarryOut <= (Y and X) or ((Y or X) and CarryIn); 
> C(15 downto 1) <= CarryOut(14 downto 0); 
> Cout <= CarryOut(15);
> 
> P2: process(Clock,Clear,Restart)
>     begin
>         if Clear = '1' or Restart = '1' then
>             X <= "0000000000000000"; 
>             Y <= "0000000000000000"; 
>         elsif rising_edge(Clock) then 
>             if Load = '1' then 
>                X <= Data_in; 
>             elsif Zero = '1' then 
>                X <= "0000000000000001"; 
>             else 
>                X <= Y; 
>             end if; 
>             Y <= Stmp; 
>         end if; 
>     end process P2;
> 
> S <= Stmp; 
> end behavior;
> 
> I would like to know what is the addition in xilinx ise which altera
> maxplus II doesn’t have?
> 
> Waiting for your reply.

This is a good example of why single letter names are not a good idea. 
I wanted to search on all occurances of your signal "C".  But obviously
this would be pointless.  

After reformatting the code to make it more readable, I see that C is
declared as a vector 15 downto 0, but you never assign a value (or use
the result) of element 0.  My guess is that the Altera tool was giving
you a warning, and then ignoring element C(0).  The Xilinx tool was just
ignoring element C(0) without a warning.  I don't think any synthesis
tool would consider this an error unless you have it configured for
that.  

To fix the problem you can either define C as a vector of 15 downto 1,
or assign C(0) a constant value like you did for CarryIn.  

One other note; you are creating Restart as a synchronous signal, but
using it to async reset X and Y.  That will reset X and Y in the current
clock cycle (async reset), but will hold it in reset until after the
next clock.  Is that what you intended?  You may have intended to reset
it on the next clock edge once Cout is asserted.  If so, you can remove
signal Restart and replace it with Cout.  This will reset X and Y on the
same clock cycle as before, but will not hold it in reset for the extra
clock period.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 71697
Subject: VHDL file equation
From: "buke2" <cubah@tlen.pl>
Date: Wed, 28 Jul 2004 09:54:43 +0200
Links: << >>  << T >>  << A >>
Hello all,
anybody knows how can I extract equations from Xilinx schematic?
I tried in Schematic Editor: Option->ExportNetlist and VHD file has been
generated...but to get clear equations (Out=f(In)) I must translate whole of
file...

Maybe somhere is tool for extracting euations from VHDL file?

Regards
Kuba



Article: 71698
Subject: Dcm clock for fpga
From: madhukar@matrixviewindia.com (madhukar)
Date: 28 Jul 2004 01:46:39 -0700
Links: << >>  << T >>  << A >>
hi,
  Iam using virtex2 fpga for my application.I want to interface
microblaze to the sram.
In my board sramsize is 2mb.But i will be able to access 64kb only.
I want to use 2mb for my application.I want mhs file for this
interfacing microblaze to sram.

Article: 71699
Subject: I need a cheap PC/104 FPGA module
From: "Rune Christensen" <rune.christensen@adslhome.dk>
Date: Wed, 28 Jul 2004 10:54:21 +0200
Links: << >>  << T >>  << A >>
Hello

Does anyone know a cheap PC/104 FPGA module?

Thanks
Rune Christensen


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