Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I am trying to infer a RAM for a EPF10K100A with Synplify 5.1.5a.
I used the following example from Synplicity for a single port RAM:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram_test is
port (q:out std_logic_vector(3 downto 0);
d:in std_logic_vector(3 downto 0);
addr:in std_logic_vector(2 downto 0);
we :in std_logic;
clk:in std_logic);
end ram_test;
architecture rtl of ram_test is
type mem_type is array(7 downto 0) of std_logic_vector(3 downto 0);
signal mem:mem_type;
begin
q <= mem(conv_integer(addr));
process(clk,we,addr)
begin
if rising_edge(clk) then
if (we='1') then
mem(conv_integer(addr))<=d;
end if;
end if;
end process;
end rtl;
Synplify always wants to map this RAM to a dual port RAM (altdpram), when
10KE is selected. Since the 10KA devices do not support dual port ram
the technologie mapper maps the RAM to flipflops.
Does anybody know how to tell Synplify to use a single port RAM?
Regards
Rainer
--
-----------------------------------------------------------------
Rainer Becker rainer@pentatec.de
PentaTec GmbH Tel. +49 89 456918-21
Hermann-Oberth-Str. 18, 85640 Putzbrunn Fax +49 89 6884310
Article: 27001
There is a product called A|RT Designer Pro from Frontier Design
(http://www.frontierd.com) which fulfulls all requirements except
probably the price.
The A|RT builder tool performs a one to one mapping between
standard C code (possible extended with limited precision types) and
VHDL or verilog code.
As an example the following C code
int f(int a,int b) { return a + b;}
will generate vhdl code for a 32 bit adder.
The A|RT designer Pro tool takes as algorithmic description the
same C code and an initial description of the datapath in terms
of alus, multipliers and rams.
It then augments the architecture with the bus network and maps the C
program on that processor. Also C functions mapped with A|RT builder
can used as processing elements in the datapath. The result is a VLIW
like processor running your program.
The design services department of Frontier and different customers have
used this tool to map differenct very complex algorithms on FPGA.
Jan Guffens jan_guffens@frontierd_r.com
and please remove the _r from the domain address
Peter Dennett <pdennett@padsoft.com> wrote in message
news:D80554580569F2EE.743E0A7942AB9796.7CA462C6B0873E38@lp.airnews.net...
>
Article: 27002Tobin Fricke <tobin@pulsar.CS.Berkeley.EDU> wrote: > >What is the proper way to do these things in ViewLogic's ViewDraw? > > o Merge multiple buses. Eg, say that I have A[31:0] and B[31:0]. > I'd like to form C[31:0] from A[31:16] concatenated with B[15:0]. > Is there an elegant way of doing this without making a VHDL block? > Place two BUF components and set a component attribute of $array=16 on each (look up Component Arrays in the help). Connect a short wire to the input and output pins but leave the ends on the wires unconnected. Label the input wires A[31:16] and B[15:0] and the output wires C[31:16] and C[15:0]. Job done. > o Set a bus to a constant value. Say I want F[31:0] to be set to > the constant value 0xDEADBEEF. How is this done in the schematic > editor without resorting to a VHDL block? > You could create a subsheet and use GND and VDD components, you can bring the bus out of the subsheet through a single symbol pin. Horrible I know but probably preferable to VHDL if it's the only VHDL block you are left with. Regards Julian Julian Cox Hardware Development ABB August Ltd Fault Tolerant Industrial Controls Observe antispam measure in my email address (CoxJA@)Article: 27003
Is there any possibilty to create a bistream for a Xilinx spartan XCS30 with a unique serial nr (e.g. in a register or hardwired)? I need approx 25000 systems/year and can not afford an extra component like the Dallas serial nr components. I'm not very optimistic it can be done, but I hope to get some usefull suggestions. StefaanArticle: 27004
Rainer,
You are using q to read and d to write to the RAM. This leads to a
dual port RAM inferrence. You should use one signal that is tristateable to
do both read and write.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"Rainer Becker" <rainer@pentatec.de> wrote in message
news:3A07BF9F.F131CB99@pentatec.de...
> I am trying to infer a RAM for a EPF10K100A with Synplify 5.1.5a.
> I used the following example from Synplicity for a single port RAM:
>
> library ieee;
>
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;
>
> entity ram_test is
>
> port (q:out std_logic_vector(3 downto 0);
> d:in std_logic_vector(3 downto 0);
> addr:in std_logic_vector(2 downto 0);
> we :in std_logic;
> clk:in std_logic);
> end ram_test;
>
> architecture rtl of ram_test is
>
> type mem_type is array(7 downto 0) of std_logic_vector(3 downto 0);
> signal mem:mem_type;
>
> begin
>
> q <= mem(conv_integer(addr));
>
> process(clk,we,addr)
> begin
> if rising_edge(clk) then
>
> if (we='1') then
> mem(conv_integer(addr))<=d;
> end if;
> end if;
> end process;
> end rtl;
>
>
> Synplify always wants to map this RAM to a dual port RAM (altdpram), when
> 10KE is selected. Since the 10KA devices do not support dual port ram
> the technologie mapper maps the RAM to flipflops.
>
> Does anybody know how to tell Synplify to use a single port RAM?
>
> Regards
>
> Rainer
>
> --
>
> -----------------------------------------------------------------
> Rainer Becker rainer@pentatec.de
> PentaTec GmbH Tel. +49 89 456918-21
> Hermann-Oberth-Str. 18, 85640 Putzbrunn Fax +49 89 6884310
>
Article: 27005As a rule of thumb, I never let the tools place the I/O pins automatically. They do an exceptionally poor job at it, and create pin locking problems when you go to modify the design later. Instead, you should be assigning the pins manually, as you seem to have discovered yourself. Either of your solutions will work, Interspersing them will use up less of your routing, but may cause the IO pitch to not match your internal logic pitch. Arrange your busses with the lsbs at the bottom of the chip (as viewed in the floorplanner) to avoid twists when connecting to carry chain logic. George Pontis wrote: > > Hello FPGA users, > > I am trying my best to intelligently lock at least some of the pins in a > design using a Spartan XL, in this case it is the XCS20XL-4TQ144. The > compiler does not produce an attractive design, in that the buses are > ordered in a seemingly random fashion. Also, it does not appear to > produce an optimum placement from the standpoint of routing, even though > it probably meets the requirements of the design. > > The pins that I seek to lock are for several 16 bit buses. The design > contains a 16b bidirection data bus D[15:0], a buffered version of it > that is enabled for certain operations BD[15:0], an input bus from an ADC > that can drive onto the data bus ADC[15:0], and an output bus that can > latch data from the data bus L[15:0]. > > My first thought is to place D[] and BD[] at opposite ends of horizontal > longlines. Then intersperse ADC[] with D[] on one side, and L[] with BD[] > on the opposite side. Alternatively one could put intersperse ADC[] and > L[], and place them at the top and bottom of the chip to take advantage > of splitting the vertical longlines. (Say ADC[7:0]/L[7:0] at the top and > ADC[15:8]/L[15:8] at the bottom.) > > But I am quickly getting beyond my understanding of the device and the > subtleties of routing. Can someone offer a suggestion on this specific > layout ? Or perhaps better for all, give us a pointer to some general > information on human-assisted pin locking ? > > Any suggestions or discussion on the subject will be much appreciated ! > > -- > George Pontis -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27006
In article <3A08039F.8A28CF34@andraka.com>, ray@andraka.com says... > Subject: Re: Need help locking pins for Spartan XL > From: Ray Andraka <ray@andraka.com> > Newsgroups: comp.arch.fpga > > As a rule of thumb, I never let the tools place the I/O pins automatically. > They do an exceptionally poor job at it, and create pin locking problems when > you go to modify the design later. Instead, you should be assigning the pins > manually, as you seem to have discovered yourself. Either of your solutions > will work, Interspersing them will use up less of your routing, but may cause > the IO pitch to not match your internal logic pitch. Arrange your busses with > the lsbs at the bottom of the chip (as viewed in the floorplanner) to avoid > twists when connecting to carry chain logic. > LSB at the bottom ... great suggestion that would have escaped me. I've been experimenting with some simple designs to see how the buses are routed, and even when I hand the thing to the compiler on a silver platter it makes surprising routes on 30% of the signals. I expect that it would run the data lines across the chip on HLONGs, but it uses less efficient routes for that 30%. Perhaps it is reserving some HLONGs for another purpose ? In a case like this, do you just leave the pins locked in a logical manner and move on ? Or would you go into the floorplanner and try to force specific routing down to that level ? Geo.Article: 27007
They are so much less expensive. We've started working them into our designs over FLEX10KE parts simply for the cost savings. I recently finished a design for a 1K100 device and the options and design flow felt identical to a FLEX10KE target. The board's sitting in the lab but I haven't had a chance to work with it yet. I doubt the ACEX part will hold any suprises. In article <memo.20001104184528.1328M@steve.rsn-tech.co.uk>, steve@rsn-tech.co.uk wrote: > In article <3a02ce1a.2445236103@news.trw.com>, martin.j.thompson@trw.com > (Martin Thompson) wrote: > > > Can anyone tell me what the difference between the ACEX and FLEX > > families of Altera devices is? As far as I can tell, the only > > difference is the number of packages supported... > > Funny, I was just about to ask the /exact/ same question! > > There are slight differences in timing parameters, but it's not as simple > as one being faster than the other! Take a look at the example circuit > benchmarks in the data sheets and you'll see that the 1K is a bit slower > on simple functions but faster on some complex ones compared to the 10KE > equivalent. > > -- > Steve Rencontre http://www.rsn-tech.co.uk > //#include <disclaimer.h> > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27008
I am trying to include a LogiCore 64-FFT into my VHDL design. But when synthesizing the design with Foundation I am getting a warning: Dpm: Warning: Cannot link cell 'fft_top/fft_core' to its reference design 'vfft64'. (FPGA-LINK-2) Dpm: Warning: The cell '/ver1/fft_core' is not linked to any design. (FPGA-CHECK-4) The process finishes without errors, but it seems (from the number of slices during implementation) that the core is not included. Can anybody give an advice what's going wrong ? -- +----------------------------------+----------------------------------+ | Dirk Galda | | | | | | TU Hamburg-Harburg | | | Department of Telecommunications | Phone: (++49)-40-42878-2745 | | Eißendorfer Straße 40 | Fax: (++49)-40-42878-2281 | | 21073 Hamburg | mailto:galda@tu-harburg.de | | Germany | http://www.et2.tu-harburg.de | +----------------------------------+----------------------------------+Article: 27009
I've got a design using a Spartan II and a XC18V01, and I need about 32 bits of storage for a serial number. Is there a clean way to do this? For now I've put an extra EEPROM in a socket connected to the FPGA, but it's such a hassle to milk the bits out of it, and with 1.3 megabits inside the Xilinx chip there ought to be some way to put the serial number into it in a production environment, e.g., where I don't have to re-do the place and route for each unit. I'd appreciate any suggestions... -- Gary Watson gary2@nexsan.com Nexsan Technologies Ltd. Derby DE21 7BF ENGLAND http://www.nexsan.comArticle: 27010
My pin locs are based on my PCB needs. I like the PCB routing to flow out radially away from the FPGA in all directions. I can route directly to memory/ buses / ADCs/ DACs etc. with next to no vias. Its a beautiful thing. Only if the design is going to challenge the FPGA do I reconsider this approach. DanArticle: 27011
I have just posted the article "NP Complete: An Introduction to Network
Processing" to the Netrino website. It can be found at the following URL:
http://www.netrino.com/Articles/NetworkProcessors/
The first generation of network processors has finally arrived. This
article introduces the technology and shows what they are good for and
how they can be used. It also gives an overview of each of the major
products in this emerging category of special-purpose CPUs.
This article was published in the November 2000 issue of Embedded
Systems Programming. For more information about the magazine, or to
sign up for a free subscription, please visit:
http://www.embedded.com/
The Netrino Consultants Network encourages its partners and associates
to share their technical expertise by writing magazine articles and books
and by speaking at industry conferences. Whenever possible we retain the
right to publish these materials on our website. An index of our many
publications can be found at the following URL:
http://www.netrino.com/Publications/
I hope you will find these resources valuable, and relevant to this
newsgroup.
Sincerely,
Michael Barr
Article: 27012Hi Karl, Macros can only be used if you have a schematic flow- If you had a supported schematic tool you could use them in an HDL flow by creating a netlist w/ hierarchical ports and instantiating that in your code, but as of now schematic entry in WebPACK only supports CPLDs. Regards, Tim Karl Olsen wrote: > Hello all, > > I am using the WebPACK 3.2 to do a Spartan2 design in VHDL. > Is the "Xilinx Unified Library" present in WebPACK 3.2i? > > I have been able to instantiate a RAMB4_S8 by manually having a component > declaration, probably because RAMB4_S8 is a primitive. But the compiler > won't recognize other design elements, such as the ADSU4 macro. Is there > any way of using the ADSU4 macro from VHDL? > > Regards, > Karl OlsenArticle: 27013
Hi Dirk, This warning is normal and should be expected. It simply means that the core is a black box into which the synthesizer cannot see. Things to check: Look at the edif netlist to ensure that the instantiated component is there. Look at the map.mrp file to see what logic has been trimmed. You could also do a post-route simulation. Regards, Tim Dirk Galda wrote: > I am trying to include a LogiCore 64-FFT into my VHDL design. But when > synthesizing the design with Foundation I am getting a warning: > > Dpm: Warning: Cannot link cell 'fft_top/fft_core' to its reference > design 'vfft64'. (FPGA-LINK-2) > Dpm: Warning: The cell '/ver1/fft_core' is not linked to any design. > (FPGA-CHECK-4) > > The process finishes without errors, but it seems (from the number of > slices during implementation) that the core is not included. Can anybody > give an advice what's going wrong ? > > -- > +----------------------------------+----------------------------------+ > | Dirk Galda | | > | | | > | TU Hamburg-Harburg | | > | Department of Telecommunications | Phone: (++49)-40-42878-2745 | > | Eißendorfer Straße 40 | Fax: (++49)-40-42878-2281 | > | 21073 Hamburg | mailto:galda@tu-harburg.de | > | Germany | http://www.et2.tu-harburg.de | > +----------------------------------+----------------------------------+Article: 27014
My group is doing an open re-write of our Streams-C compiler (described in FCCM 2000). It consists of three SUIF 1.3 passes and translates a subset of C into VHDL. The suif passes will be available in source form, and have the same sort of copyright as suif - freely available for non-commercial use. We're planning on an initial release at the end of this calendar year, accessible through rcc.lanl.gov. Maya Jan Gray wrote: > > > Is there any GNU or like open source system for conversion of > > > C to VHDL? Or for that matter any other higher level language. > --------------------------------------------------------------------------- Maya B. Gokhale Group NIS-3, Space Data Systems, Mail Stop D440 505-665-9095 Office Nonproliferation and International Security Division 505-665-4197 FAX Los Alamos National Laboratory, Los Alamos, NM 87545 505-996-3113 Pager maya@lanl.gov ---------------------------------------------------------------------------Article: 27015
On Tue, 7 Nov 2000 11:16:00 +0100, "Stefaan Vanheesbeke" <stefaan.vanheesbeke@planetinternet.be> wrote: > >Is there any possibilty to create a bistream for a Xilinx spartan XCS30 with >a unique serial nr (e.g. in a register or hardwired)? > > >I need approx 25000 systems/year and can not afford an extra component like >the Dallas serial nr components. > > >I'm not very optimistic it can be done, but I hope to get some usefull >suggestions. I haven't implemented this myself but I think theoretically it can work. What you need to do is to implement a ROM with coregen and use an EDF file for the contents. Then you implement this design with PAR. When you have a final floorplan, you save it and then create new EDF files with different contents and run it again. This should give you unique bit files with only the ROM contents different. I think this can be done faster than trying to find where the ROM contents go in the bit file. Running PAR with a full floor-plan should be very quick. Muzaffer http://www.dspia.comArticle: 27016
I bought Michale Barr's book on using c/c++ for embedded systems a while back, and thought it was great. The nutrino web site is also full of excellent information and I would say it's definitely worth a look if you do embedded work. -- Gary Watson gary2@nexsan.com Nexsan Technologies Ltd. Derby DE21 7BF ENGLAND http://www.nexsan.com "Michael Barr" <mbarr@netrino.com> wrote in message news:3A082649.29B95FF@netrino.com... > I have just posted the article "NP Complete: An Introduction to Network > Processing" to the Netrino website. It can be found at the following URL: > > http://www.netrino.com/Articles/NetworkProcessors/ > > The first generation of network processors has finally arrived. This > article introduces the technology and shows what they are good for and > how they can be used. It also gives an overview of each of the major > products in this emerging category of special-purpose CPUs. > > This article was published in the November 2000 issue of Embedded > Systems Programming. For more information about the magazine, or to > sign up for a free subscription, please visit: > > http://www.embedded.com/ > > The Netrino Consultants Network encourages its partners and associates > to share their technical expertise by writing magazine articles and books > and by speaking at industry conferences. Whenever possible we retain the > right to publish these materials on our website. An index of our many > publications can be found at the following URL: > > http://www.netrino.com/Publications/ > > I hope you will find these resources valuable, and relevant to this > newsgroup. > > Sincerely, > Michael BarrArticle: 27017
What kind of work are you looking to get done specifically? -Jeremy Vincent Jachetta - Multidyne wrote: > Looking for Xilinx FPGA designer on Long Island. Slary open, benefits. > Call (516)671-7278 ext 103 > www.multidyne.comArticle: 27018
I have done designs with the Xilinx chips before, mostly schematic capture but some VHDL designs. But that was like a year ago and I only used the student version of their software. I am getting back into digital design and was wondering if anyone could suggest a better chip and design software package that's worth purchasing and getting to know? Thanks, -JeremyArticle: 27019
Michael Barr wrote: > > I have just posted the article "NP Complete: An Introduction to Network > Processing" to the Netrino website. It can be found at the following URL: > > http://www.netrino.com/Articles/NetworkProcessors/ > ... Michael, A good pun is priceless! I hope, though, that you don't mean to imply that Network Processing is isomorphic to the Traveling Salesman Problem. Jerry -- Engineering is the art of making what you want from things you can get. -----------------------------------------------------------------------Article: 27020
Hello, We have used Synplicity's Synplify. It is a relatively reasonably priced synthesis solution. If you are one using Xilinx, Synplify-Lite might be a good fit as well. It is much more reasonable, but only target's Xilinx devices. This is ONLY synthesis however. Another option if you are going to use Xilinx-only (or Altera only) is to purchase a design package from Xilinx/Altera. Xilinx's Foundation ships with schematic entry, HDL entry, synthesis and a simulator. It is all bundled into a design enviornment. I think that the quality of results may be a little less than if you used a "real" sythesis tool (like Synplify) but it would allow you to get your feet wet again and get pretty good results. (I doubt that most who uses the Xilinx tools complains too much about the quality of results??? Although I am sure I will get many responses to the contrary.) Best of luck. Mark Sasten Avocent Corp. "Jeremy Cooke" <jercooke@yahoo.com> wrote in message news:3A084FB6.DD6EFCA3@yahoo.com... > I have done designs with the Xilinx chips before, mostly schematic > capture but some VHDL designs. But that was like a year ago and I only > used the student version of their software. I am getting back into > digital design and was wondering if anyone could suggest a better chip > and design software package that's worth purchasing and getting to know? > > > > Thanks, > > -Jeremy >Article: 27021
"Maya" <maya@lanl.gov> wrote in message news:3A082E14.4E30A5D3@lanl.gov... > My group is doing an open re-write of our Streams-C compiler (described in FCCM > 2000). It consists of three SUIF 1.3 passes and translates a subset of C into > VHDL. The suif passes will be available in source form, and have the same sort > of copyright as suif - freely available for non-commercial use. We're planning > on an initial release at the end of this calendar year, accessible through > rcc.lanl.gov. I'd sure be interested if there is a paper to read on what was presented at FCCM 2000. This seems to be exactly what I'm looking for. -- Peter Dennett Email: pdennett@padsoft.com 61 Harbor Lane Web: www.padsoft.com Kemah, TX 77565 Web: www.boatbrains.com Voice: 281 334 3800 Cell: 713 899 6100 Fax: 281 521 1032Article: 27022
> Is there any possibilty to create a bistream for a Xilinx spartan XCS30 with > a unique serial nr (e.g. in a register or hardwired)? > > I need approx 25000 systems/year and can not afford an extra component like > the Dallas serial nr components. Somebody else asked the same thing on another thread. This seems like a good topic for a Xilinx APP note. It sounds like a reasonably straight forward thing to do. Just put the serial number in a ROM. You can either re-run the Xilinx tools to make the special bit stream for each device or you can work out how to do modify the basic bitstream. If I wanted to do it myself, I'd do something like this: Put all 0s in the ROM. Make your bits. Change the ROM contents to 1. Make the bits again and see which bit(s) changed. Repeat for all the other bits on the ROM. The bit stream may have a CRC to complicate things. I couldn't find the details in the Virtex data sheet. You can probably just XOR those changed bits too. (CRCs are nice that way.) But you should really think about doing this. You now have to make a separate bit stream for each device. You have to make sure you get it right. How bad is it if you get it wrong, for example by shipping two boxes with the same serial number? Also look into Ethernet HostID ROMs. -- These are my opinions, not necessarily my employers. I hate spam.Article: 27023
These days I failed to connect www.xilinx.com from here, does anybody have the same experience? -- Zhengfan XieArticle: 27024
Here I have a signal-- REALCONTROL,
it changes at the rising clock cycle,
and if it changes, the next following clock cycle
other signals need to be changed correspondingly
so I use
elsif REALCONTROL'event then
CHANGEC:='1';
elsif REALPHASE'event then
CHANGEP:='1';
end if;
end process COUNTER_Gen;
However sysopsis told me
Checking...
Error L139/C0 : #0 Error: The 'event or 'stable attribute ( on line 139 )
is supported only when the attribute is used in conformance with the style
described in the Synopsys manual for the VHDL compiler. (VHDL-2160)
1 error(s) 0 warning(s) found
Can anyone do me a favor to tell me how to fix it?
Thank you very very much!
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z