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Hello; Now ,i am doing simulation with NC-VERILOG,but ,during compiling and simulation ,the question is occrued: ncelab:*E,CUVHNF (./pos_bench.v,13|27):Hierarchical name component look up failed at 'test_convert', wire GSR=glbl.GSR; ncelab:*E,CUVHNF (./time_sim.v,7026|22):Hierarchical name component look up failed at 'glbl', wire GTS=glbl.GTS; ncelab:*E,CUVHNF(./time_sim.v,7027|22);Hierarchical name component look up failed at 'glbl', what's meaning? how do i? Thanks a lotArticle: 27651
Magnus Homann wrote: > Ray Andraka <ray@andraka.com> writes: > > > Use GSR to initialize all your FF's, but then have only one point in > > your design depend on when the GSR is released. For example, use a > > synchronized version of GSR to hold a master state machine in reset > > after GSR is released, then after GSR is safely gone away let the > > thing start going. > > Sounds like a resonable way of doing it. I'll remember that until next > time. > > Doesn't that mean you have to make a fairly structured design, though? > :-) > > Homann > -- > Magnus Homann, M.Sc. CS & E > d0asta@dtek.chalmers.se Given the poorly spec'ed & timed nature of the GSR shouldn't we really be discussing how to disable it & do any necessary start-up stuff by generating a sync reset tree [Synplify's automatic replication is useful here]? I agree with Magnus that unless there are compelling reasons otherwise all resets should be synchronous. The question is: If I instantiate the startup block, and connect the GSR pin to GND does this turn off the GSR function altogether ? or does it still get asserted during the configuration process ? If its not possible to turn it off altogether then I consider this dangerous esp if there's any prospect of an ASIC conversion. Even without that I consider that the chip start-up process should always be considered as part of the design and should not rely on features of the underlying technology.Article: 27652
Marc Roche wrote: > Yes the JTAG interface be used to configure and readback the FPGA on Xilinx. > > Xilinx provide a wide range of FPGA sush as VIRTEX, VIRTEX-E, VIRTEX-EM that > offers you the possibility to carry out the prototype of your ASIC. > > My company has some good experiment in prototyping ASICs on Virtex family. > > Regards > > Marc ROCHE > -- > Design Ingeneer > Multi Video Designs > 106 av des Guis > 31830 Plaisance du Touch > France > Tel.: +33(0) 5 62 13 52 32 > Fax.: +33 (0) 5 61 06 72 60 > mailto : marc.roche@mvd-fpga.com > http://www.mvd-fpga.com You may have to be careful here. Although readback & verify can be done via the JTAG port the JTAGProgrammer s/w may not support it. It certainly wasn't supported in the 2.1i programmer but this may have changed for 3.1/2i. See the note at the bottom of page 14 of XAPP139. If you understand enough Java I think you can use the Jbits s/w instead of the JTAGProgrammer. The only sure way of getting readback is to use a MultiLinx cable connected to the SelectMap port. Fig 2-10 in the Hardware User Guide shows the connections.Article: 27653
Hello, Is is possible to drive the input of a DLL with the output of another DLL ? I need to multiply by 4. A DLL will only multiply by 2. Will the resultant 4X clock have poor characteristics if I do this? (unstability/ bad jitter/ loss of lock ......) ? Also, I may want to use tw DLL to get multiply by 1.3333 ( 1st DLL 2X, 2nd DLL /1.5) Sincerely Daniel DeConinck High Res Technologies, Inc.Article: 27654
On Fri, 01 Dec 2000 10:52:28 +0000, Rick Filipkiewicz <rick@algor.co.uk> wrote: >The question is: If I >instantiate the startup block, and connect the GSR pin to GND does this >turn off the GSR function altogether ? or does it still get asserted >during the configuration process ? It still gets asserted. I instantiate startup anyway, even if I've got nothing to OR into GSR. That way I know exactly what the name of the GSR net is, and I don't have to rely on the synth understanding my intention. >If its not possible to turn it off altogether then I consider this >dangerous esp if there's any prospect of an ASIC conversion. Even without >that I consider that the chip start-up process should always be considered >as part of the design and should not rely on features of the underlying >technology. If you're doing an ASIC, then you can put in a global net for a power-up reset without much impact on the design. I don't know that I want to do this in an FPGA - routing is just too expensive. I'm still in favour of using GSR, since it's free, but making sure that you get out of reset in some synchronous way. EvanArticle: 27655
I must admit I can't justify the expense at the moment either! I think I'll put up with my PIII 500 for a few more months! "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3A24E1DB.3A0EFAF3@algor.co.uk... > > > Phil Martin wrote: > > > Hi Rick, > > > > Why not upgrade to a Athlon 1.2GHz, with 133MHz DDR? > > > > Then you can tell me whether or not I should do the same! > > > > Cheers, > > > > Phil Martin > > > > That's what I'd do if I had the opportunity but we're building an office in > Cambridge so all £££ decisions are subject to questions. That said the DDR > Athlon boards are very much cheaper now than they were even 6 month ago & I > expect a bread&butter 900/133DDR would do almost as well. > > > >Article: 27656
I want to generate a 32 bit parity for which the delay is to be 4 ns maximum.I use Leonardo spectrum 2000.I do not insert pads since this is a sub-module in my hierarchy.How do I acheive this in VirtexE architecture.Leonardo gives me 14 ns delay.After implementation in Xilinx I get 25% logic delay and 75 % routing delay which is 5 ns logic and 8 ns routing.I do manual placement in the floorplanner only to see Dr.watson error when I re-implement the design.Using Synplicity RLOC constraint Is a better option which gives me 4 ns logic delay while synthesis but the xilinx tool does away with the RLOC constraint and spreads the logic haphazardly once again. How can I acheive this 4ns delay through the parity logic with Leonardo-xilinx alliance combination. I have only eval license of synplicity.Article: 27657
I want to generate a 32 bit parity for which the delay is to be 4 ns maximum.I use Leonardo spectrum 2000.I do not insert pads since this is a sub-module in my hierarchy.How do I acheive this in VirtexE architecture.Leonardo gives me 14 ns delay.After implementation in Xilinx I get 25% logic delay and 75 % routing delay which is 5 ns logic and 8 ns routing.I do manual placement in the floorplanner only to see Dr.watson error when I re-implement the design.Using Synplicity RLOC constraint Is a better option which gives me 4 ns logic delay while synthesis but the xilinx tool does away with the RLOC constraint and spreads the logic haphazardly once again. How can I acheive this 4ns delay through the parity logic with Leonardo-xilinx alliance combination. I have only eval license of synplicity.Article: 27658
Dan wrote: > > Hello, > > Is is possible to drive the input of a DLL with the output of another DLL ? > > I need to multiply by 4. A DLL will only multiply by 2. > > Will the resultant 4X clock have poor characteristics if I do this? > (unstability/ bad jitter/ loss of lock ......) ? Yes. See Xilinx application note XAPP132 (page 12-13). > Also, I may want to use tw DLL to get multiply by 1.3333 ( 1st DLL 2X, 2nd > DLL /1.5) Dunno. Ths sounds iffy, though perhaps you might be able to multiply by 4 (see above) and divide by 3 in some fashion? ---- KeithArticle: 27659
That is no guarantee unless you are running a pretty slow clock. The delta between the propagation delays on the GSR net is quite substantial, and are longer than the clock periods you are likely to use on a Virtex part (>>10ns). Additionally, the sync reset is at the FF, so there is no guarantee of all the FF's seing the sync input go away on the same clock, regardless of how slow your clock is. Magnus Homann wrote: > > "Austin Franklin" <austin@darkroo98m.com> writes: > > > > > The recommendation to not use the global GSR is due to poor > > implementation > > > > (it's quite slow) of the dedicated metal in the Xilinx part. This > > timing > > > > issue is EASILY overcome in the design such that it will not cause any > > > > problems. > > > > > > Really? How? I never use it, I stick with sync reset. > > > > Be glad to tell you ;-) First, make sure ALL the registers in the design > > have a positive asynch set or reset. Second, instantiate the STARTUP > > block: > > Wait, this looks like Verilog! :--) > > [Code deleted] > > > Also, in your state machines, I would suggest an extra startup state before > > looking at any input signals. > > > > If you do all this, Synplicity will automatically use the global GSR. I > > may have missed something...if I did, please let me know. > > If I managed to read your Verilog, you use the GSR as a regular async > reset? I prefer to use sync reset, to assure that all FFs sees the > reset go away on the same clock pulse. > > Homann > -- > Magnus Homann, M.Sc. CS & E > d0asta@dtek.chalmers.se -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27660
By structured, if you mean structural instantiation, no. If you mean you've taken time to do a system architecture, then yes. Any good design has to be planned out at least a little in a top-down fashion, and hierarchy only helps. Magnus Homann wrote: > > Ray Andraka <ray@andraka.com> writes: > > > Use GSR to initialize all your FF's, but then have only one point in > > your design depend on when the GSR is released. For example, use a > > synchronized version of GSR to hold a master state machine in reset > > after GSR is released, then after GSR is safely gone away let the > > thing start going. > > Sounds like a resonable way of doing it. I'll remember that until next > time. > > Doesn't that mean you have to make a fairly structured design, though? > :-) > > Homann > -- > Magnus Homann, M.Sc. CS & E > d0asta@dtek.chalmers.se -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27661
Hi Is it me connecting from Europe or has Xilinx's web site been down for the last few days? -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 00 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 27662
I agree with Evan. GSR is free and it puts every flop in a known state as long as it is asserted. As long as you don't let things go off willy-nilly as soon as you release the reset you'll be OK. Usually this involves at most a sync reset tree that is MUCH smaller than the one you would need to reset every FF in the FPGA. Basically, all you need to hold reset after releasing GSR is stuff that governs operation of sequencers. Lots of times, it can be done just by holding off trigger inputs until a few clocks after GSR. eml@riverside-machines.com.NOSPAM wrote: > > On Fri, 01 Dec 2000 10:52:28 +0000, Rick Filipkiewicz > <rick@algor.co.uk> wrote: > > >The question is: If I > >instantiate the startup block, and connect the GSR pin to GND does this > >turn off the GSR function altogether ? or does it still get asserted > >during the configuration process ? > > It still gets asserted. I instantiate startup anyway, even if I've got > nothing to OR into GSR. That way I know exactly what the name of the > GSR net is, and I don't have to rely on the synth understanding my > intention. > > >If its not possible to turn it off altogether then I consider this > >dangerous esp if there's any prospect of an ASIC conversion. Even without > >that I consider that the chip start-up process should always be considered > >as part of the design and should not rely on features of the underlying > >technology. > > If you're doing an ASIC, then you can put in a global net for a > power-up reset without much impact on the design. I don't know that I > want to do this in an FPGA - routing is just too expensive. I'm still > in favour of using GSR, since it's free, but making sure that you get > out of reset in some synchronous way. > > Evan -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27663
See the app-notes on using DLLs. I think it is numbered up around #232. The 4x is described carefully in the Appnote and includes a VHDL example. Dan wrote: > > Hello, > > Is is possible to drive the input of a DLL with the output of another DLL ? > > I need to multiply by 4. A DLL will only multiply by 2. > > Will the resultant 4X clock have poor characteristics if I do this? > (unstability/ bad jitter/ loss of lock ......) ? > > Also, I may want to use tw DLL to get multiply by 1.3333 ( 1st DLL 2X, 2nd > DLL /1.5) > > Sincerely > Daniel DeConinck > High Res Technologies, Inc. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27664
Anyone knows what this error message means exactly? ----- FATAL_ERROR:Anno:ResolverImp.c:507:1.8 - Semantic check failed for physical block "pu24" (P6217). Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com ----- It does this everytime I try to back-annotate my NGD file... However, I can't find anything on support.xilinx.com. It can't even find a match for "semantic check" with their crappy answer database search engine. I'm using M3.1 and the design contains the PCI32 Virtex core. Any idea? Thanks! MartinArticle: 27665
"Magnus Homann" <d0asta@mis.dtek.chalmers.se> wrote in message news:ltsno88q8m.fsf@mis.dtek.chalmers.se... > If I managed to read your Verilog, you use the GSR as a regular async > reset? I prefer to use sync reset, to assure that all FFs sees the > reset go away on the same clock pulse. This is generally considered over-conservative design, but if it works for you without pushing you into bigger or faster chips, by all means go for it! :-) ---Joel KolstadArticle: 27666
Hello, I did not have any problems this week ! Olivier Regnault Avnet FranceArticle: 27667
Hi Martin, If possible, upgrade your 3.1i service pack to the latest (sp5 is now available) and rerun the design flow (starting at least with map). If not, then if you're running anno from the command line leave off the appending <filename>.ngm from the command line or uncheck the 'Correlate Simulation Data to Input Design' option in the GUI. Hope this helps, Tim "Guibert, Martin" wrote: > Anyone knows what this error message means exactly? > > ----- > FATAL_ERROR:Anno:ResolverImp.c:507:1.8 - Semantic check failed for > physical > block "pu24" (P6217). Process will terminate. To resolve this > error, please > consult the Answers Database and other online resources at > http://support.xilinx.com > ----- > > It does this everytime I try to back-annotate my NGD file... However, I > can't find anything on support.xilinx.com. It can't even find a match > for "semantic check" with their crappy answer database search engine. > I'm using M3.1 and the design contains the PCI32 Virtex core. > > Any idea? > > Thanks! > > MartinArticle: 27668
Take a look at solution http://support.xilinx.com/techdocs/5474.htm You probably didn't specify the glbl module to ncelab ncvlog -update $XILINX/verilog/src/glbl.v <testfixture>.v time_sim.v ncelab -messages -autosdf testfixture_name glbl ncsim -messages testfixture_name chsw wrote: > > Hello; > Now ,i am doing simulation with > NC-VERILOG,but ,during compiling and > simulation ,the question is occrued: > ncelab:*E,CUVHNF (./pos_bench.v,13|27):Hierarchical name component look up failed at 'test_convert', > wire GSR=glbl.GSR; > ncelab:*E,CUVHNF (./time_sim.v,7026|22):Hierarchical name component look up failed at 'glbl', > wire GTS=glbl.GTS; > ncelab:*E,CUVHNF(./time_sim.v,7027|22);Hierarchical name component look up failed at 'glbl', > what's meaning? how do i? > Thanks a lot -- / 7\'7 Paulo Dutra (paulo@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive (800) 255-7778 \_\/.\ San Jose, California 95124-3450 USAArticle: 27669
Hi there, My name is Ellen Ann Nichol and I am a recruiter...before you spam me..I am not hear to use this posting board to recruit FPGA people. Since I have a dire need for FPGA people, I only wanted to know if people could send me suggestions on how to recruit you guys. Call it a survey if you like. If you were looking for a job where would you look? Do you go to certain web sites? That sort of thing. Any tips would be greatly appreciated. ellen@ingeniusengineering.comArticle: 27670
Ray Andraka <ray@andraka.com> writes:
> That is no guarantee unless you are running a pretty slow clock. The delta
> between the propagation delays on the GSR net is quite substantial, and are
> longer than the clock periods you are likely to use on a Virtex part (>>10ns).
> Additionally, the sync reset is at the FF, so there is no guarantee of all the
> FF's seing the sync input go away on the same clock, regardless of how slow your
> clock is.
>
I've been thinking about this problem and decided to stick to a
solution discussed in a thread in this group some time ago when
Bob Perlman recommended to use both an async and a sync reset for
all the register in a design, or at least the critical ones.
I've seen the same technique by the way in EDN Jan 6, 2000 p. 128.
I use GSR as an async reset for all the register and I generate a
sync reset in this way:
-- Synchronous reset generators (EDN Jan 6, 2000 p. 128)
prr : process (mem_clock, GSR_NET)
begin
if (GSR_NET = '1') then
RESET_READ0 <= '1';
RESET_READ1 <= '1';
RESET_READ2 <= '1';
RESET_READ <= '1';
elsif (mem_clock'event and mem_clock = '1') then
RESET_READ0 <= GSR_NET;
RESET_READ1 <= RESET_READ0;
RESET_READ2 <= RESET_READ1;
RESET_READ <= RESET_READ2;
end if;
end process;
Then RESET_READ is then used as a sync reset as in
pp31 : process (mem_clock, GSR_NET)
begin
if (GSR_NET = '1') then
pix_B31 <= (others => '0');
elsif (mem_clock'event and mem_clock = '1') then
if (RESET_READ = '1') then
pix_B31 <= (others => '0');
elsif (pixel_valid_gg = '1') then
pix_B31 <= pix_G41;
end if;
end if;
end process;
Since RESET_READ is generated by a register if the design meets
timing the all the registers should be properly reset.
Any comments?
-Arrigo
--
Dr. Arrigo Benedetti e-mail: arrigo@vision.caltech.edu
Caltech, MS 136-93 phone: (626) 395-3129
Pasadena, CA 91125 fax: (626) 795-8649
Article: 27671"Joel Kolstad" <JoelKolstad@Earthlink.Net> writes: > "Magnus Homann" <d0asta@mis.dtek.chalmers.se> wrote in message > news:ltsno88q8m.fsf@mis.dtek.chalmers.se... > > If I managed to read your Verilog, you use the GSR as a regular async > > reset? I prefer to use sync reset, to assure that all FFs sees the > > reset go away on the same clock pulse. > > This is generally considered over-conservative design, but if it works for > you without pushing you into bigger or faster chips, by all means go for it! > :-) Well, wher I used to do designs we first chose the part, and then looked for tasks to do it in. We wanted speed, so we got the fastest, newest, part for sale. Not very cost sensitive, I admit... :-) Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 27672
Ray Andraka <ray@andraka.com> writes: > By structured, if you mean structural instantiation, no. If you mean you've > taken time to do a system architecture, then yes. Any good design has to be > planned out at least a little in a top-down fashion, and hierarchy only helps. I meant the later, and I agree with you. Not so good for rapid prototyping, though. :-) Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 27673
Bill Lenihan wrote: > > Question 1: > > How can I take a Xilinx Virtex FPGA design that contains instance-unique > ROM (ROM values unique to each module/unit manufactured) and keep my > core logic the same, but update the ROM for each SPROM/board > manufactured, preferably without having to re-synthesize, re-place & > route, re-verify, etc.,? Ideally, the designer would have a generic > logic bitstream (with anything in the ROM) and be able to > merge/append/over-write the ROM with the desired-ROM-contents file that > is unique to each board. Note: whether the ROM is truly ROM or really > RAM that can be further written over by the mission logic is irrelevent, > the key is that at power-on the memory is ROM and has the desired unique > values. I'm thinking specifically about building the ROM with BlockRAM, > but the problem may be equally relevent to ROM built with the > distributed, LUT-based RAM, too. You could use JBits to do this. On the main Xilinx web site, go to products -> System solutions -> Xilinx Online and there is a little description of JBits. Basically, JBits gives you read and write access to programmable resources at the bitstream level, so in your case, you would want write access to BlockRAM which is supported in the latest version. The basic operation is to read in a bitstream, do some modification (in Java) and write out a second bitstream, which is then used for download. Perhaps if you drop me a line, I can give you some more details. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 27674
What I have done in a Lucent (OR3T80) design is to disable the clock as long as the GSR is asserted (and a few cycles longer). This should also be possible in the virtex parts, but... -The BUFG primitive does not show the CE (Clock Enable) input of the elemet, that can be seen in the FPGAEditor -If one creates a macro that allows to access the CE signal, this only works when you do not use a DLL (This is because of a bug of the Alliance 3.2i software, that does not handel the XIL_MAP_ALLOW_ANY_DLL_INPUT variable as it should...and stops with an error) Patrick In article <3A27369A.BDF76883@andraka.com>, Ray Andraka <ray@andraka.com> wrote: > Use GSR to initialize all your FF's, but then have only one point in your design > depend on when the GSR is released. For example, use a synchronized version of > GSR to hold a master state machine in reset after GSR is released, then after > GSR is safely gone away let the thing start going. Sent via Deja.com http://www.deja.com/ Before you buy.
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