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In article <3A09118C.1671633A@asicentrum.cz>,
Michal Prokes <michal.prokes@asicentrum.cz> wrote:
>I performed many test with encoding and I need some literature to comparing
>my results to other. And the second reason is that I need some
>cross-references into my diploma thesis about this problem.
>
Hi MICHAL,
a must read:
\bibitem{knapp-onehot}
S.~K. Knapp, ``Accelerate {FPGA} macros with one-hot approach,''
{\em Electronic Design}, Sept. 1990.
Article: 27051WIRLESS PDA DEVELOPERS - San Jose ASIC, FPGA, Windows Device Drivers Pre-IPO firm in San Jose area needs several developers for new modules and components to be developed for use with wireless PDA devices. This is a new technology and a 'fresh paint' - clean canvas' opportunity for you! Hardware engineers should have 3 years design experience in FPGA and ASIC. Software engineers should have 2 years development experience - on Windows device drivers and be proficient in C. We want to hire you immediately! Our salary range is from $80K to $125K plus other financial opportunities - based upon the depth of your skills and the breadth of your experience. We are interested in persons living in the Bay Area only. We prefer to offer permanent employment but will consider contractors. U.S. citizenship or work permit required. We will sponsor visas of persons living in the Bay Area. Recruit EXpress, our search firm, will pay you a $3,000.00 bonus if you are hired - or if the persons you refer to them are also hired for our openings. We have six openings. Call or send your resume to Rex or Howard Frankel, at Recruit EXpress (713) 666-1001 .... or fax (713) 666-9993. Their email is: REX@RecruitEXpress.com or HOWARD@RecruitEXpress.comArticle: 27052
On Wed, 8 Nov 2000 15:57:00 +0100, "Roland Manders"
<roland.manders@philips.com> wrote:
I have not done Instantiattion a RAM for ACEX but I guess it is the
as for the APEX.
You must simply backbox the component by using attributes for the
synthesis with 3'th parthy synthesis (eg. Leonardo Sprectrum)
On the other hand when using simulation You MUST use generics in
order to do so you mus use the translate on/off to make generics
unvisible for the synthesis and visible for the simulation tool ( eg.
modelsim)
When using Renoir :_ make a VHDL (verilog block and nstantiate the
component in architecture)
This rule goes not only for Altera but also for Xilinx devices
I attach an example how to implement it
I hope it explains it
regards
Georg
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY fifodp IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (11
DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (11
DOWNTO 0);
wren : IN STD_LOGIC := '1';
inclock : IN STD_LOGIC ;
outclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END fifodp;
ARCHITECTURE SYN OF fifodp IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
signal clkx2:std_logic;
signal clkx1:std_logic;
signal clock_lock:std_logic;
COMPONENT altclklock
-- GENERIC (
-- inclock_period : NATURAL;
-- clock1_boost : NATURAL
-- );
PORT (
inclock : IN STD_LOGIC ;
clock1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT altdpram
PORT (
outclock : IN STD_LOGIC ;
wren : IN STD_LOGIC ;
inclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (11
DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (11
DOWNTO 0)
);
END COMPONENT;
attribute black_box: boolean;
attribute LPM_WIDTH: integer;
attribute LPM_WIDTHAD: integer;
attribute WIDTH: integer;
attribute WIDTHAD: integer;
attribute LPM_TYPE: string;
attribute LPM_INDATA : string ;
attribute LPM_OUTDATA : string ;
attribute LPM_RDADDRESS_CONTROL: string ;
attribute LPM_WRADDRESS_CONTROL: string ;
attribute LPM_FILE : string ;
attribute LPM_HINT : string ;
attribute INCLOCK_PERIOD:NATURAL;
attribute CLOCK0_BOOST : NATURAL;
attribute CLOCK1_BOOST : NATURAL;
-- Assign the appropriate attribute values here
attribute black_box of altdpram: component is true;
attribute LPM_WIDTH of altdpram: component is 16;
attribute LPM_WIDTHAD of altdpram: component is 12;
--attribute LPM_TYPE of altdpram: component is "LPM_RAM_DQ";
attribute LPM_INDATA of altdpram: component is "REGISTERED";
attribute LPM_OUTDATA of altdpram: component is "REGISTERED";
attribute LPM_RDADDRESS_CONTROL of altdpram: component is "INCLOCK";
attribute LPM_WRADDRESS_CONTROL of altdpram: component is "INCLOCK";
--attribute LPM_FILE of altdpram: component is "";
attribute LPM_HINT of altdpram: component is "USE_EAB=ON";
attribute WIDTH of altdpram: component is 16;
attribute WIDTHAD of altdpram: component is 12;
attribute CLOCK0_BOOST of altclklock:component is 1;
attribute CLOCK1_BOOST of altclklock:component is 2;
attribute INCLOCK_PERIOD of altclklock:component is 40000;
-- Here is where we specify that the LPM parameterized module we
-- want to use is: "LPM_RAM_DQ"
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altclklock_component : altclklock
--translate off
-- GENERIC MAP (
-- inclock_period => 40000,
-- clock0_boost => 1,
-- clock1_boost => 2
-- )
--translate off
PORT MAP (
inclock => inclock,
clock1 => clkx2,
locked => clock_lock
);
altdpram_component : altdpram
--translate off
-- GENERIC MAP (
-- width => 16,
-- widthad => 12,
-- indata_reg => "INCLOCK",
-- wraddress_reg => "INCLOCK",
-- wrcontrol_reg => "INCLOCK",
-- rdaddress_reg => "INCLOCK",
-- rdcontrol_reg => "INCLOCK",
-- outdata_reg => "OUTCLOCK",
-- indata_aclr => "OFF",
-- wraddress_aclr => "OFF",
-- wrcontrol_aclr => "OFF",
-- rdaddress_aclr => "OFF",
-- rdcontrol_aclr => "OFF",
-- outdata_aclr => "OFF",
-- lpm_hint => "USE_EAB=ON"
-- )
--translate on
PORT MAP (
outclock=>clkx2,
wren => wren,
inclock =>clkx2 ,
data => data,
rdaddress => rdaddress,
wraddress => wraddress,
q => sub_wire0
);
END SYN;
>Hi,
>
>Can anyone tell me how to instantiate dpram by using renoir as entry
>programs. I mean how can I infer
>the package for the Altera ACEX in renoir.
>
>Thanks.
>
>Roland
>
Article: 27053Erika, An excellent point. A PLL can do M/D fractional synthesis. The Virtex DLL can not. Thank you for pointing out my oversight, Austin erika_uk@my-deja.com wrote: > hi, > is it right than the PLL is able to deliver also any ratio...but the Dll > just integer or integer+0.5 > > --Erika > In article <3A09918E.246A77FF@xilinx.com>, > Austin Lesea <austin.lesea@xilinx.com> wrote: > > > > --------------20355C97D5FCEB4DF06F691F > > Content-Type: text/plain; charset=us-ascii > > Content-Transfer-Encoding: 7bit > > > > Anshuman, > > > > The DLL is not a PLL. A PLL is not the DLL. They both have their > > advantages and disadvantages. Thanks for the opportunity to respond > on this > > topic. > > > > Virtex Family DLL's > > > > The DLL's in Virtex is an all digital device with a state machine, and > > tapped delay line. The result of using it is always predictable, and > it > > will always be the same on any chip ever manufactured. > > > > It is unaffected by voltage, temperature, and process due to its > design. > > > > The jitter out of the CLK0 output is a fixed known amount +/- one tap > (~40 > > ps). DLL's do not filter out the input jitter, they pass it through. > > > > The jitter input tolerance is as stated in the data sheet, and if > exceeded, > > the device will not assert the LOCK signal, or it will lose LOCK if it > locks > > at all. > > > > All outputs (0, 90 degrees, 180 degrees, 270 degrees, 2X, CLKDV) > behave in > > this precise predictable digital fashion. > > > > The absolute phase error of the DLL is constrained to a tap, combined > with > > the error in matching the two inputs (in and feedback) to the DLL > (also very > > small because the of the physical layout). > > > > The DLL is designed to run as fast as the global clock buses, so speed > > inside the FPGA is not an issue (can't go any faster). The input > range of > > the DLL is much larger than that of a PLL. > > > > PLL's > > > > A phase locked loop is an analog device with a voltage or current > controlled > > oscillator (RC, LC, inverter ring, crystal, etc), a phase detector, > and a > > loop filter. Each one is unique, and there may be significant > variations in > > lot to lot, and part to part. It is not unusual to change components > to > > make PLL's work on the production floor. > > > > PLL's are directly affected by voltage, temperature, process (and some > claim > > phases of the moon). > > > > PLL's may have a lot, or no input jitter tolerance. You have to look > a Bode > > Plot of the loop response to see if it is stable, and perform a number > of > > jitter tolerance and transfer tests on a number of units over > temperature > > and voltage. You never really know if a PLL is locked (its analog!) > > > > The jitter out of a PLL can be extremely small (a few ps), or very > very > > gross (~90 ps). It depends entirely on the design, filter, oscillator > > chosen, and how much of the digital signals disturb the operation of > the > > PLL's loop. PLL's are able to filter out input jitter if designed > properly. > > > > PLL's have no outputs other than the oscillator output, which may be > running > > a twice the intended frequency to yield 180 degrees, or even higher if > more > > phases are required. > > > > The phase error of the PLL varies with voltage, temperature, and > process, > > and is difficult to contrain when trying to de-skew clock signals. It > is > > often unspecified due to the extreme difficulties in characterization > and > > test. > > > > PLL's can run at arbitraily high speeds (GHz), but offer narrow ranges > of > > operation. > > > > Which to use? > > > > If you are dealing with digital signals, in the digital domain, and > you are > > processing and modifying these signals, then the DLL is a natural > choice. > > > > If you need to filter jitter, then you may have to use the PLL. If > that is > > the case, an off-chip PLL, where you can use your own filter, and > oscillator > > may be the only way to go. > > > > PLL's that are co-located with other digital logic tend to add as much > > jitter as they are trying to remove. > > > > If you are in a communications system, with carrier frequencies, IF's, > up > > converters, and down converters, you will be using many PLL's, and be > > miserable for it....always waiting for that phone call: "line down, > PLL's > > not locking, again!" > > > > Austin Lesea > > Principal Engineer, FPGA Lab > > Xilinx > > > > Anshuman Sharma wrote: > > > > > I'm working on designing a low level packet filter on an FPGA. Since > it > > > needs run at very high speeds, which would be more advisable to use, > PLL > > > or a DLL? > > > > > > -- > > > Anshuman Sharma > > > Georgia Institute of Technology > > > > --------------20355C97D5FCEB4DF06F691F > > Content-Type: text/html; charset=us-ascii > > Content-Transfer-Encoding: 7bit > > > > <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> > > <html> > > Anshuman, > > <p>The DLL is not a PLL. A PLL is not the DLL. They both > have > > their advantages and disadvantages. Thanks for the opportunity > to > > respond on this topic. > > <p><b>Virtex Family DLL's</b> > > <p>The DLL's in Virtex is an all digital device with a state machine, > and > > tapped delay line. The result of using it is always predictable, > > and it will always be the same on any chip ever manufactured. > > <p>It is unaffected by voltage, temperature, and process due to its > design. > > <p>The jitter out of the CLK0 output is a fixed known amount +/- one > tap > > (~40 ps). DLL's do not filter out the input jitter, they pass it > > through. > > <p>The jitter input tolerance is as stated in the data sheet, and if > exceeded, > > the device will not assert the LOCK signal, or it will lose LOCK if it > > locks at all. > > <p>All outputs (0, 90 degrees, 180 degrees, 270 degrees, 2X, CLKDV) > behave > > in this precise predictable digital fashion. > > <p>The absolute phase error of the DLL is constrained to a tap, > combined > > with the error in matching the two inputs (in and feedback) to the DLL > > (also very small because the of the physical layout). > > <p>The DLL is designed to run as fast as the global clock buses, so > speed > > inside the FPGA is not an issue (can't go any faster). The input > > range of the DLL is much larger than that of a PLL. > > <p><b>PLL's</b> > > <p>A phase locked loop is an analog device with a voltage or current > controlled > > oscillator (RC, LC, inverter ring, crystal, etc), a phase detector, > and > > a loop filter. Each one is unique, and there may be significant > variations > > in lot to lot, and part to part. It is not unusual to change > components > > to make PLL's work on the production floor. > > <p>PLL's are directly affected by voltage, temperature, process (and > some > > claim phases of the moon). > > <p>PLL's may have a lot, or no input jitter tolerance. You have > to > > look a Bode Plot of the loop response to see if it is stable, and > perform > > a number of jitter tolerance and transfer tests on a number of units > over > > temperature and voltage. You never really know if a PLL is > locked > > (its analog!) > > <p>The jitter out of a PLL can be extremely small (a few ps), or very > very > > gross (~90 ps). It depends entirely on the design, filter, > oscillator > > chosen, and how much of the digital signals disturb the operation of > the > > PLL's loop. PLL's are able to filter out input jitter if > designed > > properly. > > <p>PLL's have no outputs other than the oscillator output, which may > be > > running a twice the intended frequency to yield 180 degrees, or even > higher > > if more phases are required. > > <p>The phase error of the PLL varies with voltage, temperature, and > process, > > and is difficult to contrain when trying to de-skew clock > signals. > > It is often unspecified due to the extreme difficulties in > characterization > > and test. > > <p>PLL's can run at arbitraily high speeds (GHz), but offer narrow > ranges > > of operation. > > <p><b>Which to use?</b><b></b> > > <p>If you are dealing with digital signals, in the digital domain, and > > you are processing and modifying these signals, then the DLL is a > natural > > choice. > > <p>If you need to filter jitter, then you may <i>have</i> to use the > PLL. > > If that is the case, an off-chip PLL, where you can use your own > filter, > > and oscillator may be the only way to go. > > <p>PLL's that are co-located with other digital logic tend to add as > much > > jitter as they are trying to remove. > > <p>If you are in a communications system, with carrier frequencies, > IF's, > > up converters, and down converters, you will be using many PLL's, and > be > > miserable for it....always waiting for that phone call: <b><i>"line > down, > > PLL's not locking, again!"</i></b> > > <p>Austin Lesea > > <br>Principal Engineer, FPGA Lab > > <br>Xilinx > > <p>Anshuman Sharma wrote: > > <blockquote TYPE=CITE>I'm working on designing a low level packet > filter > > on an FPGA. Since it > > <br>needs run at very high speeds, which would be more advisable to > use, > > PLL > > <br>or a DLL? > > <p>-- > > <br>Anshuman Sharma > > <br>Georgia Institute of Technology</blockquote> > > </html> > > > > --------------20355C97D5FCEB4DF06F691F-- > > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 27054
Is there a way to create a vhdl module & its test bench such that: 1) it has an instance of a primitive part say RAMB4_S8_S8, (I need dual clocks which XST does not handle.) 2) the vhdl module passes synthesis by clicking "Implement Design", 3) the test bench auto simulates by clicking "Simulate Functional VHDL model", 4) the test bench auto simulates by clicking "Simulate Post-Route VHDL model"? This involves switching between none, UNISIM, and PRIMSIM libraries. Any Ideas on how to set this up?Article: 27055
Anybody got some code I can scrounge? I'll bet others have done this already. I've got the schematics from the Xilinx web site and I've worked with peek/poke code to drive the printer port and I've written code to do the serial download over home-brew hardware so I'm pretty sure I can do it all. But why reinvent a wheel if I can scrounge it? -- These are my opinions, not necessarily my employers. I hate spam.Article: 27056
Thank you very much! Got it! <steve (Steve Rencontre)> wrote in message news:memo.20001108184559.1464E@steve.rsn-tech.co.uk... > In article <8uaap3$gao$1@news.doit.wisc.edu>, qianz@cae.wisc.edu (Qian > Zhang) wrote: > > > Here I have a signal-- REALCONTROL, > > it changes at the rising clock cycle, > > and if it changes, the next following clock cycle > > other signals need to be changed correspondingly > > so I use > > elsif REALCONTROL'event then > > CHANGEC:='1'; > > elsif REALPHASE'event then > > CHANGEP:='1'; > > end if; > > end process COUNTER_Gen; > > However sysopsis told me > > Checking... > > Error L139/C0 : #0 Error: The 'event or 'stable attribute ( on line > > 139 ) > > is supported only when the attribute is used in conformance with the > > style > > described in the Synopsys manual for the VHDL compiler. (VHDL-2160) > > 1 error(s) 0 warning(s) found > > Can anyone do me a favor to tell me how to fix it? > > Thank you very very much! > > Many features of VHDL are designed for simulation, and you are restricted > in a synthesis context. Synthesis can only use 'event to infer clocks, so > you need something like, > > signal last_control : std_logic; > > if CLK'event and CLK = '1' then -- infers a +ve clock > if REALCONTROL /= last_control then > CHANGEC <= '1'; > else > CHANGEC <= '0'; > end if; > > last_control <= REALCONTROL; -- infers a register > end if; > > -- > Steve Rencontre http://www.rsn-tech.co.uk > file://#include <disclaimer.h> >Article: 27057
hello: when i am doing timing simulator(using the reference design xapp205.zip :fifoctlr_ccmw1.v/fifoctlr_ccmw2.v) for a project,the follwoing message occures: "P1/U1/U11/BU0/INTERNAL_BLOCKRAM--READ Violation.Attempt to read from cell that is also being written to." the capacity of the dual block ram i mentioned is 16x1024--64x256,that is,when read_enable is active,write_enable must inactive.But when i replace it with 16x2048---64x512,it is right,and the phenomena of the warning is not . why?Article: 27058
I am looking for an old PDP-8 minicomputer like the PDP-8/E or PDP-8/M, etc... Also, any software, boards, manuals for a PDP-8. Please e-mail me at johnb@teachers.org if you have anything available. johnArticle: 27059
Thank you for this answer but I'm using neither both edges of the clock nor fpga-express. Andy Peters wrote: > prc wrote: > > > > I have a problem concerning the global buffers (BUFG) in a xc4062xla > > fpga from xilinx. I have 2 clocks signals using them in a design (the > > second clock is internal). I can see these buffers in the xnf netlist. > > During Place & Route the design manager gives me a warning saying that > > my internal clock is using non-dedicated resources. > > Are you using both edges of the clock? > > I found a bug with FPGA Express v3.4. If it sees that you are using > both edges of the clock, it stupidly infers an CLB inverter on the > clock, and runs that through a BUFGLS, whose output drives the flops > clocked on the opposite edge. Since at that point, the tools think the > clocks are unrelated, they complain about skew problems. The > non-dedicated resource is the inverter in the CLB. > > FPGA Express should use the polarity-select mux that's part of EVERY > flip-flop in the XLA part, but it doesn't. There's no work-around, > except maybe going back to a previous version, or buying a real > synthesis tool. V3.3 did not seem to have this problem. > > See > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10127 > for Xilinx' lame answer. > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u > > "It is better to be silent and thought a fool, > than to send an e-mail to the entire company > and remove all doubt."Article: 27060
In article <7UiO5.464529$1h3.12407989@news20.bellglobal.com>, "Simon Bilodeau" <simon.bilodeau@htrc.com> wrote: > Hi, I am developping an prototype board that is interfaced with PC- 104 bus. > It works well but after 5 minutes I begin to read 0xFFFF on my board and > bizarre caracters appear on my screen.. > > Some bizarre caracters display when the PC is booting (without my program > running) > > My board use 0x220 to 0x23F in I/O space with no interrupts. > > all my VCC and GND are connected with decoupling capacitors and unused pins > (TIE) are connected to GND. > > Any hint for me? > > Thanks in advance > > Simon Bilodeau > HTRC Paper Technologies. > > Your problem is not complety clear to me, but if it comes from the power supply or from glitches than sometimes it helps to configure the outputs for a slow rise time. -- Klaus Falser Durst Phototechnik AG I-39042 Brixen Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27061
--------------4F2F4F270F5DF0EADA343928 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi all, we have just bought the new ATMEL Demoboard with a FPSLIC SoC onboard. Has anybody expiriences with such a SoC or a application done on it ? Any comments are appreciated. with regards Georg Heinrich -- ## mail from: Georg Heinrich ### ##### # ### ###### ## mailto:georg@eas.iis.fhg.de ### # ### # ###### ## http://www.xgeorg.de ### ### # # # ~# ###### ###################################### # # # ### ###### --------------4F2F4F270F5DF0EADA343928 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Hi all, <p>we have just bought the new ATMEL Demoboard with a FPSLIC SoC onboard. <br>Has anybody expiriences with such a SoC or a application done on it ? <p>Any comments are appreciated. <br>with regards <br>Georg Heinrich <pre>-- ## mail from: Georg Heinrich ### ##### # ### ###### ## <A HREF="mailto:georg@eas.iis.fhg.de">mailto:georg@eas.iis.fhg.de</A> ### # ### # ###### ## <A HREF="http://www.xgeorg.de">http://www.xgeorg.de</A> ### ### # # # ~# ###### ###################################### # # # ### ######</pre> </html> --------------4F2F4F270F5DF0EADA343928--Article: 27062
I don't know of any such product. I would question whether such an
approach would be the best way to get your "feet wet" anyway. The code
produced by such a process would unlikely be clean and would therefore
offer little help as an educational tool. I can almost gaurantee it
won't do everything you want without tweaking which will ultimately
involve learning VHDL. Besides this, there's a good chance that only a
subset of C would be supported, perhaps a "synthesizable C". This
would involve a learning curve for the C-side also.
Perhaps a book on VHDL targetted to programmers would work best? I
haven't read any but I could probably at least find names.
Good luck with whatever you decide to do!
Tim
p.s. - If it helps, I went from a programming background to VHDL. It
requires a conceptual shift but the language is simple. It's similar
to going from C to object oriented C++. The syntax jump is easy but
the concepts are very different. I learned VHDL from VHDL tutorials.
They're all over the place.
In article
<D80554580569F2EE.743E0A7942AB9796.7CA462C6B0873E38@lp.airnews.net>,
"Peter Dennett" <pdennett@padsoft.com> wrote:
> Is there any GNU or like open source system for conversion of
> C to VHDL? Or for that matter any other higher level language.
>
> I'm a programmer interested in learning a bit about FPGAs
> and was thinking this might be a good way to get my feet
> wet. I don't need, nor could I afford a commercial product,
> unless its real affordable.
>
> As a starter project I am interested in creating a simple graphic
> LCD controller for quarter VGA devices. Nothing fancy, just
> handle screen refresh from a SRAM, simple dot, line drawing,
> and bit blit algorithms to SRAM, and a microcontroller interface.
> Initially monochrome, but room to grow to color.
>
> Likely I'll be using a "student" version for the FPGA tools. I
> have not as yet chosen a chip vendor of choice.
>
> Any constructive suggestions (I already know I'm a snot nosed
> programmer walking among the hardware gods) to either the
> converter, project, or appropriate chips are welcome.
>
> --
> Peter Dennett Email: pdennett@padsoft.com
> 61 Harbor Lane Web: www.padsoft.com
> Kemah, TX 77565 Web: www.boatbrains.com
> Voice: 281 334 3800 Cell: 713 899 6100 Fax: 281 521 1032
>
>
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 27063
Does anyone here know of sources for microprocessor Verilog or VHDL
behavioral models?
I am doing a board level simulation that involves FPGAs, memories,
peanut components, and a Mot ColdFire microprocessor. I checked with Mot
about providing a C behavioral model or an encrypted Verilog/VHDL behavioral
model, and they referred me to the Big S -- Synopsis. This means that it
will cost an ARM and a leg, and I'm not talking about an ARM processor!
Does anyone know of alternatives?
-Simon Ramirez, Consultant
Synchronous Design, Inc.
Article: 27064This is a multi-part message in MIME format. ------=_NextPart_000_004B_01C04A19.10E49EB0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable A message to the fpga-cpu list [www.egroups.com/group/fpga-cpu] this = morning announced a new mailing list, fpslic@egroups.com = [www.egroups.com/group/fpslic], for "Atmel FPLSIC, also AVR and Atmel = FPGA related topics." Jan Gray, Gray Research LLC ------=_NextPart_000_004B_01C04A19.10E49EB0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY bgColor=3D#ffffff> <DIV><FONT face=3D"Courier New" size=3D2>A message to the fpga-cpu list=20 [www.egroups.com/group/fpga-cpu] this morning announced a new = mailing list,=20 <A href=3D"mailto:fpslic@egroups.com">fpslic@egroups.com</A>=20 [www.egroups.com/group/fpslic], for "<FONT size=3D3>Atmel FPLSIC, also = AVR and=20 Atmel FPGA related topics."</FONT></FONT></DIV> <DIV><FONT face=3D"Courier New" size=3D2></FONT> </DIV> <DIV><FONT face=3D"Courier New" size=3D2>Jan Gray, Gray Research = LLC</FONT></DIV> <DIV><FONT face=3D"Courier New" size=3D2></FONT> </DIV> <DIV><FONT face=3D"Courier New" = size=3D2></FONT> </DIV></BODY></HTML> ------=_NextPart_000_004B_01C04A19.10E49EB0--Article: 27065
Hi, Has anyone done it? Is it possible? Target FPGA: Xilinx XC4005E-4 I remember reading a web page on using Atmel AT89C2051 to configure the FPGA, but can't find any using PIC. Regards, LC kanglc@agilis.st.com.sgArticle: 27066
"S. Ramirez" wrote: > > Does anyone here know of sources for microprocessor Verilog or VHDL > behavioral models? > I am doing a board level simulation that involves FPGAs, memories, > peanut components, and a Mot ColdFire microprocessor. I checked with Mot > about providing a C behavioral model or an encrypted Verilog/VHDL behavioral > model, and they referred me to the Big S -- Synopsis. This means that it > will cost an ARM and a leg, and I'm not talking about an ARM processor! > Does anyone know of alternatives? Ugh. I'm in the same boat. I started a ColdFire 5206e model a while ago -- just bus transactions -- and it's not ready for prime time (other things interfered). It would be nice if the chip vendors had some kind of USABLE model; then again, they usually don't even have IBIS models, so whom are we kidding? -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27067
Hi
I'm working on my first VHDL design.
I'm tring to interface the Xilinx PCI core with a MPC860 bus.
I have same problem with the map application.
It report this error (one of about 162!)
ERROR:OldMap:648 - BUFT symbol "PCI_CORE/PCI_LC/5/UPPER/T6" (output
signal=ADIO<22>, enable signal=PCI_CORE/PCI_LC/BAR1_T) on signal
"ADIO<22>"
has been reduced to a permanently-driving buffer. (The enable signal
was
probably either grounded or reduced to ground.) However, another
active
three-state BUFT symbol "USER_APP/BusSwitchC/C513" (output
signal=ADIO<22>,
enable signal=USER_APP/BusSwitchC/N430) is driving this signal;
therefore,
the signal is multiply sourced.
ModelSim simulation is OK!
I guess that the logic that manage the pci core is reduced to a costant
value.
Could someone be so kind as to suggest me a plausible cause?
Thank you in advance
Andrea
--
A.Sorio
R&D Electronic Engineer
Atenix E.E.
Via S.Dona' 106
30170 Mestre (VE)
ITALY
Tel. +39-041-2621035
email: andrea.sorio@atenix.it
Article: 27068Webpack and Foundation software only have primitives in HDL library. ADSU4 is a schematic macro and it cannot be instantiated in VHDL/Verilog. Only the primitive components like RAMB4_S8, CLKDLL etc. can be instantiated in HDL. Schematic macros must be only used in Schematic projects and not in HDL designs. Refer UNISIM library for a list of available HDL primitives. Hope this helps !!! Vikram Xilinx Applications Karl Olsen wrote: > Hello all, > > I am using the WebPACK 3.2 to do a Spartan2 design in VHDL. > Is the "Xilinx Unified Library" present in WebPACK 3.2i? > > I have been able to instantiate a RAMB4_S8 by manually having a component > declaration, probably because RAMB4_S8 is a primitive. But the compiler > won't recognize other design elements, such as the ADSU4 macro. Is there > any way of using the ADSU4 macro from VHDL? > > Regards, > Karl OlsenArticle: 27069
Hi,
I've some really weird results (design does not route) from PAR for a
Xilinx Virtex design, here is my experimental setup :
- My design is a 16 stage pipelined floating point
- M2.1 (latest SP) targeting Virtex xcv800
- It takes no more than 7% of the xcv800 slices...
I've tried various implementations with different compress factor (from
-c 1 to -c 0) results are the following :
Command Line : map -r -c 0 -cm speed -detail -o ret_fmul_16_c0
ret_fmul_16
Target Device : xv800
Target Package : bg432
Target Speed : -4
Mapper Version : virtex -- C.22
Design Summary
--------------
Number of errors: 0
Number of warnings: 4
Number of Slices: 724 out of 9,408 7%
Slice Flip Flops: 537
4 input LUTs: 629 (13 used as a route-thru)
Shift registers: 173
Number of Slices containing
unrelated logic: 0 out of 724 0%
Number of bonded IOBs: 97 out of 316 30%
Command Line : map -r -c 1 -cm speed -detail -o ret_fmul_16_c1
ret_fmul_8
Target Device : xv800
Target Package : bg432
Target Speed : -4
Mapper Version : virtex -- C.22
Design Summary
--------------
Number of errors: 0
Number of warnings: 3
Number of Slices: 450 out of 9,408 4%
Slice Flip Flops: 324
4 input LUTs: 629 (15 used as a route-thru)
Shift registers: 101
Number of Slices containing
unrelated logic: 118 out of 450 26%
Number of bonded IOBs: 97 out of 316 30%
In all cases with and without timing constraints, with multiple PAR
passes, the design always fail to route completely. Specifically GND and
Vcc signals (among others) do not route : below is an example of one of
the PAR report file which ask me to use a larger device while i uses at
most 7% of its slices ....
What I don't understand is that a relatively equivalent design in terms
of complexity (floating point adder) with much more pipelmine stage and
less regularity place an route successfully !!
Any Xilinx guru to shed the light on this :) ?
Steven Derrien
IRISA, France
Total REAL time: 17 mins 24 secs
Total CPU time: 17 mins 22 secs
End of route. 3897 routed (84.35%); 15 unrouted active,
708 unrouted PWR/GND.
No errors found.
The signal "mul/C3690_C85O" is not completely routed.
The signal "GLOBAL_LOGIC1" is not completely routed.
The signal "mul/retiming_reg_239Q" is not completely routed.
The signal "mul/retiming_reg_237Q" is not completely routed.
The signal "mul/C3690_C267/O" is not completely routed.
The signal "mul/C3690_C631O" is not completely routed.
The signal "GLOBAL_LOGIC0" is not completely routed.
The signal "mul/C3690_C1008/O" is not completely routed.
The signal "mul/C3690_C1003O" is not completely routed.
The signal "mul/retiming_reg_38Q" is not completely routed.
The signal "mul/C3690_C1420O" is not completely routed.
The signal "mul/retiming_reg_91Q" is not completely routed.
The signal "mul/C3690_C1440O" is not completely routed.
The signal "mul/retiming_reg_97Q" is not completely routed.
The signal "mul/retiming_reg_115Q" is not completely routed.
The signal "mul/C3690_C1493/O" is not completely routed.
The signal "mul/C3690_C1492O" is not completely routed.
This design was not fully routed. To help fully route the design, you
may try
the following:
* Retarget the design to the next larger device in this family.
--> I only use 7% of the chip ressource !!!!!
Total REAL time to Router completion: 17 mins 28 secs
Total CPU time to Router completion: 17 mins 26 secs
The Number of signals not completely routed for this design is: 17
The Average Connection Delay for this design is: 2.890 ns
The Maximum Pin Delay is: 10.541 ns
The Average Connection Delay on the 10 Worst Nets is: 7.578 ns
Listing Pin Delays by value: (ns)
d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 11.00 d >= 11.00
--------- --------- --------- --------- --------- ---------
1987 1065 228 246 371 0
Article: 27070In article <IIdO5.7216$Fi.29641@NewsReader>, gary2@nexsan.com (Gary Watson) wrote: > > Bitgen has an option to load a 8 character hexidecimal number into the > "User > ID Register" whatever the heck that is. I've been looking through the > Xilinx docs and can't find an answer. It might be a JTAG thing, and not > something inside the Virtex/Spartan which I can read once the device is > programmed. Correct, although there's nothing to stop you implementing a JTAG interface to read it :-) -- Steve Rencontre http://www.rsn-tech.co.uk //#include <disclaimer.h>Article: 27071
Andy,
A "leading" design verification "expert" told me that I could get this
model from the vendor,i.e., Motorola, very easily. "Just ask them," he
said. I have learned from experience that in our business, anyone who has a
quick, fast answer to a complicated problem is just blurting out BS. Of
course this has to be verified.
And so I did. I found the IBIS and BDSL files at the Mot site, but I
couldn't find any behavioral models. So I registered and posted my request
to their technical support team. I got back a response directing me to the
IBIS and BDSL files! A second post telling them that there is a HUGE
difference between these files and what I wanted got me a response back with
a link to the Synopsis site. I have a message in to the local Synopsis rep
asking him for the cost of this model, but I am bracing myself for sticker
shock (and a long wait for the response). This is why I posted the original
message.
At least I know that there are others looking for similar things. I
will post the results when I get them. Hmm, this is what ABC, NBC and CBS
said on the night of the election, and they still don't know!
Thanks.
Simon Ramirez, Consultant
Synchronous Design, Inc.
"Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message
news:8uelp5$rqp$3@noao.edu...
> "S. Ramirez" wrote:
> >
> > Does anyone here know of sources for microprocessor Verilog or VHDL
> > behavioral models?
> > I am doing a board level simulation that involves FPGAs, memories,
> > peanut components, and a Mot ColdFire microprocessor. I checked with
Mot
> > about providing a C behavioral model or an encrypted Verilog/VHDL
behavioral
> > model, and they referred me to the Big S -- Synopsis. This means that
it
> > will cost an ARM and a leg, and I'm not talking about an ARM processor!
> > Does anyone know of alternatives?
>
> Ugh. I'm in the same boat. I started a ColdFire 5206e model a while
> ago -- just bus transactions -- and it's not ready for prime time (other
> things interfered). It would be nice if the chip vendors had some kind
> of USABLE model; then again, they usually don't even have IBIS models,
> so whom are we kidding?
>
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u
>
> "It is better to be silent and thought a fool,
> than to send an e-mail to the entire company
> and remove all doubt."
>
Article: 27072Andrea Sorio wrote: > However, another active > three-state BUFT symbol "USER_APP/BusSwitchC/C513" (output > signal=ADIO<22>, > enable signal=USER_APP/BusSwitchC/N430) is driving this signal; > therefore,the signal is multiply sourced. > > ModelSim simulation is OK! Does your simulation wiggle ADIO<22>? > I guess that the logic that manage the pci > core is reduced to a costant value. That's not necessarily a problem. The problem is that you shorted two outputs together. -- mike.treseler at flukenetworks dot comArticle: 27073
Ha! I knew it! Thank you Steven for validating this for me. I have *exactly* the same problem. I'm using a Virtex-E 2000, FG1156-7. I only use up between 27-50% of the CLBs, but my design does not fully route either!! OK, what I've learned so far: 1) Forget the VCC and GND not routing. PAR tries to route your active signals, and when it can't, it gives up before even doing power and ground, even though they might be values (like reset) in your design. If it can't route all the active signals, it gives up. 2) Try and find the offending module in your design. I see from your report that it could be the 'mul' block. Even though it breaks the functionality, see if you can take it out, and have the thing P&R without it. I tried this with mine, and was able to find the offending module. I have a workaround to this module, which you might be able to do to your module. 3) Don't bother trying area constraints to fix supposed congestion within your design. You can do it if you're bored, but I tried single area constraints, columns, routing channels, and very thin and wide are constraints. Nothing works. I have a call into Xilinx now. My offending module was over 1000 FFs, and I wonder if PAR pukes on that. I don't know. Thank you again for validating my position on this Steven. I thought I was crazy... Cheers, WallyArticle: 27074
I'm thinking about requesting the Xilinx ChipScope software & cores for purchase, despite having 16 Virtex I/O pins plus clock for LA hookup. At $495, it seems like (relatively) cheap insurance. Looks like we'd have to rent an Agilent 16700 LA to fully use it. Anyone have any experience with using ChipScope (i.e. would you recommend it)? A colleague has admonished me to check it out first before buying it because of his experience with Intel's early generation ICEs. much TIA. Lawrence Peregrim lperegrim@ksa1.nospam.com
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