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I have available for sale one of the following: YOKOGAWA ADVICE In Circuit Emulator #AD200B/EM/COV Power Supply AC100V Interface AE001C/ETH PH014 H8/510 Probe "pod" New cost >$25,000 This is a current production unit, used to develop, debug & evaluate hardware & software, from 4bit to 32bit & possibly 64bit architectures For more info go to: www.ydcusa.com (hit ADVICE, then hit UNIVERSAL ARCHITECTURE) www.ashling.com/prydc.html If interested E-mail or call (323)851-8844Article: 27801
Olivier REGNAULT wrote: > AVNET Europe is selling Xilinx Design Kit which includes > Foundation ISE (Xilinx Development tool) + demo board (Spartan2 100K gates) + Download cable. > > Refer to your local sales office. > > Olivier REGNAULT > Avnet france Aha! Now we know where all the SpartanII's are going. Expect a rush of orders for the board followed by an equally large rush of returned units complaining of the poor solder quality after the FPGA ``just sorta fell off''.Article: 27802
> My name is Ellen Ann Nichol and I am a recruiter...before you spam me..I am > not hear to use this posting board to recruit FPGA people. Since I have a > dire need for FPGA people, I only wanted to know if people could send me > suggestions on how to recruit you guys. Call it a survey if you like. If > you were looking for a job where would you look? Do you go to certain web > sites? That sort of thing. Any tips would be greatly appreciated. I hope you understand that recruiters have a really bad reputation on usenet - almost as bad as porn/scam spammers. Anybody who hasn't seen it should read Russ Allbery's "rant". http://www.eyrie.org/~eagle/writing/rant.html If I was in charge, I'd say no job ads in this newsgroup and probably most others. To me, they are just clutter. Usenet is a place for people to share. People posting jobs rarely contribute anything useful. For example, you might have offered to post a summary of your survey. That would be giving something to the group. The standard way to advertise on usenet is to put a few lines in a signature at the end of your posting. (4 lines is the normal limit. Bogus posts just to get your ad posted again don't count.) I don't have any good suggestions for how to find people, but here is my list of things not to do: Spam me directly via email. I got one from Lucent today. Sigh. Said he found my name via Deja.com. How many others did he hit? Post a big pile of crap here. I'm thinking of a collection of jobs where the word "FPGA" is burried deep inside one job description. Post the same thing here again a week or two later. If I was looking for a job, I'd ask my friends. -- These are my opinions, not necessarily my employers. I hate spam.Article: 27803
> > > I am working on a new design , using XCV400-BG560. > > > How can I find out (except looking at the Pin-out symbol diagram) > > > which > > > I/O pin belongs to each of the banks ? > > The data sheet for the part will tell you. > > No it doesn't (as far as I could see); > The only way to extract which I/O pin belongs to each of the banks from > the data sheet is to observe its relative location in the BG560 PIN > Function Diagram. I'm confused. I'm looking at a copy of the VirtexE data sheet. Is the non-E version different? More than half of mine is page after page just listing the internal name, the pin number, and which bank it's in. -- These are my opinions, not necessarily my employers. I hate spam.Article: 27804
> x 3res at the TX end is a bit of a pain - yes, I know the > sheet says there is a combo bourns part but would expect > 26wk lead and long term supply headaches. Actually, you may have the other problem. They probably want you to buy a whole reel - 5000 pieces. They sure are dense though. > No, I think its 350mV for LVDS and 850mV on PECL, at least Thanks. I just did the arithmetic. I get 373 mV and 809 mV. That's using spec values for the resistors and 2.5 and 3.3 for the power supply and assuming the outputs switch rail-to-rail. -- These are my opinions, not necessarily my employers. I hate spam.Article: 27805
> I am trying to use an XCV300e-8ES part to transmit and receive 16bit by > 622MHz sonet frames but I think I may be having problems with the DLL's at > that frequency. Did you track it down yet? I'm assuming you are using the LVDS or LVPECL clock inputs. I've got a test board where I'm seeing DLL problems when using a LVPECL clock input. I'm using an XCV50E-6 at well below its max speed. Similar logic with a LVTTL clock input works OK. I also used the blinking LEDs trick. I can usually get it to work by fiddling around a bit. I haven't tried to track it down. Once I get it going it will run for a long time. -- These are my opinions, not necessarily my employers. I hate spam.Article: 27806
Anybody had success or troubles with the National LP3965? I've got a setup that goes Wall brick to make 5 V LP3965 to make 3.3 from 5 LP3965 to make 1.8 from 3.3 The 1.8 supply is for an XCV50E. It looks like the 1.8 regulator is shutting down. The output ramps down to about 1.4 V over 250 uSec. If I calculate the current it works out to roughly what I expect. Then it recovers and the picture starts over again. I've got a board where we added 1000 uF caps on the input and output of the 3.3V regulator. That pattern is different. After the recovery, the 1.8 supply is OK for 500 uSec while the 3.3 V supply is dropping. National's AN-1148 gives a lot of background on linear regulators. The data sheet just says it needs 10uF on the output side with no details on the ESR required for stability. I've got 33 uF tantilum right next to the regulator chip and another one on the other side of the board. This only happens when I adjust the test setup so that there is a lot of noise on the 3.3 V supply - 100 mV p-p. The digital logic works OK with that much noise. The board is running at ~80 MHz and it's all random data from LFSRs. This board is a test/debug board. I've got a scope on an error signal. It is working fine until the 1.8 V supply drops below 1.5. I think I just need to "fix" the output caps so the feedback path is stable. But I'd be a lot happier if I was doing some science and engineering rather than trial and error. Anybody know if two regulators in series like this get into more stability troubles? URLs? -- These are my opinions, not necessarily my employers. I hate spam.Article: 27807
We are looking for consultant to program Xilinx Spartan2. Preferably in the Bay Area (SJ). Please email to me at nguyentule@aol.com.Article: 27808
I am looking to buy 500 to 1000 of the Xilinx Spartan XCS30 or XCS40. Anyone has excess inventory of these items? Please email to me at snguyen43@juno.com ThanksArticle: 27809
With the time constants you have, I would at least wonder if this is some type of thermal shutdown of the regulator. On 9 Dec 2000 11:28:20 GMT, murray@pa.dec.com (Hal Murray) wrote: > >Anybody had success or troubles with the National LP3965? > >I've got a setup that goes > > Wall brick to make 5 V > LP3965 to make 3.3 from 5 > LP3965 to make 1.8 from 3.3 > >The 1.8 supply is for an XCV50E. > >It looks like the 1.8 regulator is shutting down. The output >ramps down to about 1.4 V over 250 uSec. If I calculate the >current it works out to roughly what I expect. Then it >recovers and the picture starts over again. > >I've got a board where we added 1000 uF caps on the input >and output of the 3.3V regulator. That pattern is different. >After the recovery, the 1.8 supply is OK for 500 uSec while >the 3.3 V supply is dropping. > >National's AN-1148 gives a lot of background on linear regulators. >The data sheet just says it needs 10uF on the output side with no >details on the ESR required for stability. I've got 33 uF tantilum >right next to the regulator chip and another one on the other side >of the board. > >This only happens when I adjust the test setup so that there is >a lot of noise on the 3.3 V supply - 100 mV p-p. The digital logic >works OK with that much noise. The board is running at ~80 MHz >and it's all random data from LFSRs. > >This board is a test/debug board. I've got a scope on an error >signal. It is working fine until the 1.8 V supply drops below 1.5. > >I think I just need to "fix" the output caps so the feedback >path is stable. But I'd be a lot happier if I was doing some science >and engineering rather than trial and error. > >Anybody know if two regulators in series like this get into >more stability troubles? URLs? Philip Freidin FliptronicsArticle: 27810
Hal, Another customer had the same setup with the same LDO parts, and we made it work by placing resistors on the outputs to make the minimum load something other than none, and we used lo esr aluminum electrolytics, I think it was 470 uf. My recommendation was not to put two such super fast regulators in series. They told us to keep the two boards they sent us, and re-layed it out for two regulators dropping from the 5 Vdc to the 3.3 and 1.8. A lot of regulators are not stable with 0 load, or wildly changing load, so the resistor helps that issue, as well as damping the oscillations, but it looked like with different patterns, you might need different caps and R's! Austin Hal Murray wrote: > Anybody had success or troubles with the National LP3965? > > I've got a setup that goes > > Wall brick to make 5 V > LP3965 to make 3.3 from 5 > LP3965 to make 1.8 from 3.3 > > The 1.8 supply is for an XCV50E. > > It looks like the 1.8 regulator is shutting down. The output > ramps down to about 1.4 V over 250 uSec. If I calculate the > current it works out to roughly what I expect. Then it > recovers and the picture starts over again. > > I've got a board where we added 1000 uF caps on the input > and output of the 3.3V regulator. That pattern is different. > After the recovery, the 1.8 supply is OK for 500 uSec while > the 3.3 V supply is dropping. > > National's AN-1148 gives a lot of background on linear regulators. > The data sheet just says it needs 10uF on the output side with no > details on the ESR required for stability. I've got 33 uF tantilum > right next to the regulator chip and another one on the other side > of the board. > > This only happens when I adjust the test setup so that there is > a lot of noise on the 3.3 V supply - 100 mV p-p. The digital logic > works OK with that much noise. The board is running at ~80 MHz > and it's all random data from LFSRs. > > This board is a test/debug board. I've got a scope on an error > signal. It is working fine until the 1.8 V supply drops below 1.5. > > I think I just need to "fix" the output caps so the feedback > path is stable. But I'd be a lot happier if I was doing some science > and engineering rather than trial and error. > > Anybody know if two regulators in series like this get into > more stability troubles? URLs? > > -- > These are my opinions, not necessarily my employers. I hate spam.Article: 27811
The ESB RAM in the Altera 20K is not a true dual port RAM. It has a read port and a write port. In order to make it look like a dual port RAM, you need to clock it at 2x your data clock to do 2 accesses per clock. Depending on your system clock, you may not be able to do that with one ESB. You can also double the number of ESBs so that you read or write two words for one virtual port on even clocks and 2 words for the other virtual port on odd clocks. Xilinx Virtex's block RAM is a true dual port RAM, so you have independent read/write access to both ports, even if the clocks are different. Jerry Pongstaporn wrote: > > has anyone tried to implement a true dual port ram in an altera 20k > device. by true dual port, i mean you can write and read both ports. > the only lpm they offer is lpm_ram_dp. but that only allows you to > write one port and read the other. i also tried the csdpram function > they offer, but i cannot get that to work. that is a cycle-shared dual > port ram. xilinx has a true dual port in their libraries, but i would > rather not switch from altera at this point. has anyone else run into > this before? btw, i am synthesizing vhdl with synplicity, and using > quartus for place and route. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27812
Thanks. > With the time constants you have, I would at least wonder if > this is some type of thermal shutdown of the regulator. The LP3962 has an error pin. I may have to get one of them to verify that it really is shutting down. (The LP3965 has a sense pin instead.) The data sheet lists 3 reasons for shutdown: too hot, low input voltage, and overcurrent. It's not overheating, not even warm. The input voltage is fine - maybe noisy, but plenty of headroom. I can't measure the current. The regulator is rated at 1.5 amps. The average is well under that. The ramp down slope matches what I expect. There are no big spikes on the 1.8 V supply indicating something is drawing a lot of current. I tried something suggested by National's support group. I bypassed the first regulator by connecting up a lab supply. That setup runs for a while before going through the shutdown cycle. The time between shutdown cycles seems random. > A lot of regulators are not stable with 0 load, or wildly changing load, > so the resistor helps that issue, as well as damping the oscillations, > but it looked like with different patterns, you might need different caps > and R's! Humm. Thanks. There is one graph in AN-1148 that shows the ESR of the cap for the stable region. There is both an upper limit and a lower limit. It gets better (wider range is stable) at low current. Note that too good (low ESR) of a cap is unstable too. Nothing in the data sheet though. On the other hand, it's easy to try adding some dummy load. I wonder what we have in the junk box. -- These are my opinions, not necessarily my employers. I hate spam.Article: 27813
I would use the second LP3965 to make 1.8 from 5 V. That avoids cascading two "amplifiers", which is always a tricky proposition. You lose nothing by running the two linear regulators in parallel, but you gain stability and peace of mind. Peter Alfke, Xilinx Applications. ======================================= Hal Murray wrote: > Anybody had success or troubles with the National LP3965? > > I've got a setup that goes > > Wall brick to make 5 V > LP3965 to make 3.3 from 5 > LP3965 to make 1.8 from 3.3 > > The 1.8 supply is for an XCV50E. > > It looks like the 1.8 regulator is shutting down. The output > ramps down to about 1.4 V over 250 uSec. If I calculate the > current it works out to roughly what I expect. Then it > recovers and the picture starts over again. > > I've got a board where we added 1000 uF caps on the input > and output of the 3.3V regulator. That pattern is different. > After the recovery, the 1.8 supply is OK for 500 uSec while > the 3.3 V supply is dropping. > > National's AN-1148 gives a lot of background on linear regulators. > The data sheet just says it needs 10uF on the output side with no > details on the ESR required for stability. I've got 33 uF tantilum > right next to the regulator chip and another one on the other side > of the board. > > This only happens when I adjust the test setup so that there is > a lot of noise on the 3.3 V supply - 100 mV p-p. The digital logic > works OK with that much noise. The board is running at ~80 MHz > and it's all random data from LFSRs. > > This board is a test/debug board. I've got a scope on an error > signal. It is working fine until the 1.8 V supply drops below 1.5. > > I think I just need to "fix" the output caps so the feedback > path is stable. But I'd be a lot happier if I was doing some science > and engineering rather than trial and error. > > Anybody know if two regulators in series like this get into > more stability troubles? URLs? > > -- > These are my opinions, not necessarily my employers. I hate spam.Article: 27814
I would use the second LP3965 to make 1.8 from 5 V. That avoids cascading two "amplifiers", which is always a tricky proposition. You lose nothing by running the two linear regulators in parallel, but you gain stability and peace of mind. Peter Alfke, Xilinx Applications. ======================================= Hal Murray wrote: > Anybody had success or troubles with the National LP3965? > > I've got a setup that goes > > Wall brick to make 5 V > LP3965 to make 3.3 from 5 > LP3965 to make 1.8 from 3.3 > > The 1.8 supply is for an XCV50E. > > It looks like the 1.8 regulator is shutting down. The output > ramps down to about 1.4 V over 250 uSec. If I calculate the > current it works out to roughly what I expect. Then it > recovers and the picture starts over again. > > I've got a board where we added 1000 uF caps on the input > and output of the 3.3V regulator. That pattern is different. > After the recovery, the 1.8 supply is OK for 500 uSec while > the 3.3 V supply is dropping. > > National's AN-1148 gives a lot of background on linear regulators. > The data sheet just says it needs 10uF on the output side with no > details on the ESR required for stability. I've got 33 uF tantilum > right next to the regulator chip and another one on the other side > of the board. > > This only happens when I adjust the test setup so that there is > a lot of noise on the 3.3 V supply - 100 mV p-p. The digital logic > works OK with that much noise. The board is running at ~80 MHz > and it's all random data from LFSRs. > > This board is a test/debug board. I've got a scope on an error > signal. It is working fine until the 1.8 V supply drops below 1.5. > > I think I just need to "fix" the output caps so the feedback > path is stable. But I'd be a lot happier if I was doing some science > and engineering rather than trial and error. > > Anybody know if two regulators in series like this get into > more stability troubles? URLs? > > -- > These are my opinions, not necessarily my employers. I hate spam.Article: 27815
I would use the second LP3965 to make 1.8 from 5 V. That avoids cascading two "amplifiers", which is always a tricky proposition. You lose nothing by running the two linear regulators in parallel, but you gain stability and peace of mind. Peter Alfke, Xilinx Applications. ======================================= Hal Murray wrote: > Anybody had success or troubles with the National LP3965? > > I've got a setup that goes > > Wall brick to make 5 V > LP3965 to make 3.3 from 5 > LP3965 to make 1.8 from 3.3 > > The 1.8 supply is for an XCV50E. > > It looks like the 1.8 regulator is shutting down. The output > ramps down to about 1.4 V over 250 uSec. If I calculate the > current it works out to roughly what I expect. Then it > recovers and the picture starts over again. > > I've got a board where we added 1000 uF caps on the input > and output of the 3.3V regulator. That pattern is different. > After the recovery, the 1.8 supply is OK for 500 uSec while > the 3.3 V supply is dropping. > > National's AN-1148 gives a lot of background on linear regulators. > The data sheet just says it needs 10uF on the output side with no > details on the ESR required for stability. I've got 33 uF tantilum > right next to the regulator chip and another one on the other side > of the board. > > This only happens when I adjust the test setup so that there is > a lot of noise on the 3.3 V supply - 100 mV p-p. The digital logic > works OK with that much noise. The board is running at ~80 MHz > and it's all random data from LFSRs. > > This board is a test/debug board. I've got a scope on an error > signal. It is working fine until the 1.8 V supply drops below 1.5. > > I think I just need to "fix" the output caps so the feedback > path is stable. But I'd be a lot happier if I was doing some science > and engineering rather than trial and error. > > Anybody know if two regulators in series like this get into > more stability troubles? URLs? > > -- > These are my opinions, not necessarily my employers. I hate spam.Article: 27816
Hal Murray wrote: > Anybody had success or troubles with the National LP3965? > I've got a setup that goes > Wall brick to make 5 V > LP3965 to make 3.3 from 5 > LP3965 to make 1.8 from 3.3 > The 1.8 supply is for an XCV50E. Peter Alfke <peter.alfke@xilinx.com> writes: > I would use the second LP3965 to make 1.8 from 5 V. That avoids > cascading two "amplifiers", which is always a tricky proposition. > You lose nothing by running the two linear regulators in parallel, but > you gain stability and peace of mind. If the XCV50E draws 400 mA [*], using the two regulators in series means that they only have to dissipate 0.68W and 0.60W, whereas if you use a single regulator it has to dissipate the whole 1.28W. Depending on how you heat-sink the devices, the ambient temperature, and the airflow, this may make a big difference. Eric [*] Arbitrarily chosen as twice the max rated quiescent current spec; I suspect that a typical application will consume more, but I don't have experience with the part.Article: 27817
This is a multi-part message in MIME format. --------------582047F9A301ECAFC7FE8913 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit THank U very much Mr.Phil, I have been using JBits. :)) Cheers Anup Phil James-Roxby wrote: > anup wrote: > > > > Hello, Can someone give me starters on implementing designs that needs > > to be partially reconfigured in the Xilinx Virtex FPGAs. > > I am usign the Xilinx Foundation 3.1 series tools. > > Thanks and regards > > Anup > > The other option to XAPP151 etc is JBits. We have a full toolkit which > allows you to either manipulate designs made with standard tools, or to > construct Virtex bitstreams from scratch using our library of > parameterised cores. Partial configuration is naturally supported. > Drop a line to jbits@xilinx.com to get the latest version > Phil > -- > --------------------------------------------------------------------- > __ > / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 > \ \ Staff Software Engineer Fax: Unreliable use email :-) > / / Loki/DARPA Email: phil.james-roxby@xilinx.com > \_\/\ Xilinx Boulder > --------------------------------------------------------------------- --------------582047F9A301ECAFC7FE8913 Content-Type: text/x-vcard; charset=us-ascii; name="anup.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for anup Content-Disposition: attachment; filename="anup.vcf" begin:vcard n:Anup Kumar;Raghavan tel;home:+61-7-38761962 tel;work:+61-7-33658849 x-mozilla-html:TRUE url:www.elec.uq.edu.au/~anup org:University of Queensland;Computer Science & Electrical Engineering version:2.1 email;internet:anup@elec.uq.edu.au adr;quoted-printable:;;47/401, Dept. of CSEE, UQ, =0D=0A=0D=0A;St.Lucia, Brisbane ;Queensland;4072;Australia fn:Anup end:vcard --------------582047F9A301ECAFC7FE8913--Article: 27818
Hello Hal, I have had some improvement in my 311MHz DLL situations. In my design I'm using two DLL's running at 311MHz. In the beginning neither would lock reliably but in one case I was not using enough amplitude on the differential lvds inputs. By adjusting the amplitude up I got that DLL to lock all the time. The other DLL's input had poor signal integrity and poor frequency stability. The chip driving it was a divide by two PECL chip, mc100lvel32 I think. It was occasionally skipping a beat which I imagine is very bad for DLL's. Also the 311MHz input to DLL was poorly terminated with the termination some distance from the lvds inputs and one side of the differential line more than an inch longer than the other. There was a nasty reflection on one side. I was able to improve the termination somewhat by cutting and patching the board and I stabilized the lvel32 by properly biasing its inputs. I also went to the LVPECL setting on the DLL's input and adjusted the lvel32's output biasing resistors to put out lvpecl levels. All this was sufficient to get the second DLL to lock. My original posting received a response from a Xilinx technical guy that warned that DLL's are sensitive to double clocking due to reflections. He recommended that I bring out the DLL lock signal to an LED and that is very helpful to see if the DLL thinks it is locked. In every case when my counter stopped running the lock signal was off. He also decoded the part number on my chips to tell me that they were not really -8 speed grade but rather were early Engineering Sample(ES) parts that probably have only -6 speed. I don't have his email here with me but I will try to forward it to you from my day job. It seems that when properly driven these VirtexE DLL's really work. Good luck, -- Pete Dudley Arroyo Grande Systems "Hal Murray" <murray@pa.dec.com> wrote in message news:90t2s5$cs2@src-news.pa.dec.com... > > > I am trying to use an XCV300e-8ES part to transmit and receive 16bit by > > 622MHz sonet frames but I think I may be having problems with the DLL's at > > that frequency. > > Did you track it down yet? > > I'm assuming you are using the LVDS or LVPECL clock inputs. > > > I've got a test board where I'm seeing DLL problems when using > a LVPECL clock input. I'm using an XCV50E-6 at well below > its max speed. Similar logic with a LVTTL clock input works OK. > > I also used the blinking LEDs trick. > > I can usually get it to work by fiddling around a bit. I haven't > tried to track it down. Once I get it going it will run for > a long time. > > -- > These are my opinions, not necessarily my employers. I hate spam.Article: 27819
In article <3A32EA0F.AB3B1A17@xilinx.com>, Peter Alfke <peter.alfke@xilinx.com> writes: > I would use the second LP3965 to make 1.8 from 5 V. That avoids > cascading two "amplifiers", which is always a tricky proposition. > You lose nothing by running the two linear regulators in parallel, but > you gain stability and peace of mind. Thanks. In hindsight, that seems like a good suggestion. (In my case, the heat distribution is better that way too.) But I didn't find any mention of this in either the Xilinx data sheet or app note on Virtex power or the National data sheet or their app note on linear regulators. I can't be the first one to wire up two regulators this way. If this is such an obvious problem why haven't the manufacturers mentioned it yet? I wired them this way because of some old memory about power sequencing. I don't remember where that came from and there isn't anything in the data sheet about it so I assume (now) that it doesn't matter. I'm assuming/guessing that this particular problem is noise related. The board fails between 38-42 MHz. It works below 38 or above 42. The 40 MHz range is where the transmit and receive clocks line up and the noise gets a lot worse. I didn't see any mention of noise in the National app note. Their data sheets don't even have any good stability data, just things like "at least 10 uF". (Remindes me of trying to get metastability data.) This feels like a bogus shutdown rather than an instability problem. What sort of scope pictures should I expect if it is unstable? Low frequency flapping or high frequency ringing? Would things be different if I were using a switching regulator? I hacked in some extra load. That helps. With an external supply making 3V and the extra load it actually works - or rather I haven't provoked the problem on the bench. I haven't tried temp/power ranges. -- These are my opinions, not necessarily my employers. I hate spam.Article: 27820
Hal, The board I saw had the power supplies oscillating in the 100's of KHz range to the MHz range. They are very fast regulators, so when they are unstable they burst into song at a pretty high frequency. The resistor stabilized the board we had, too. Austin Hal Murray wrote: > In article <3A32EA0F.AB3B1A17@xilinx.com>, > Peter Alfke <peter.alfke@xilinx.com> writes: > > I would use the second LP3965 to make 1.8 from 5 V. That avoids > > cascading two "amplifiers", which is always a tricky proposition. > > You lose nothing by running the two linear regulators in parallel, but > > you gain stability and peace of mind. > > Thanks. > > In hindsight, that seems like a good suggestion. (In my case, > the heat distribution is better that way too.) > > But I didn't find any mention of this in either the Xilinx data > sheet or app note on Virtex power or the National data sheet or > their app note on linear regulators. I can't be the first one to > wire up two regulators this way. If this is such an obvious problem > why haven't the manufacturers mentioned it yet? > > I wired them this way because of some old memory about power > sequencing. I don't remember where that came from and there > isn't anything in the data sheet about it so I assume (now) > that it doesn't matter. > > I'm assuming/guessing that this particular problem is noise related. > The board fails between 38-42 MHz. It works below 38 or above 42. > The 40 MHz range is where the transmit and receive clocks line up > and the noise gets a lot worse. I didn't see any mention of noise > in the National app note. Their data sheets don't even have any > good stability data, just things like "at least 10 uF". (Remindes > me of trying to get metastability data.) > > This feels like a bogus shutdown rather than an instability problem. > What sort of scope pictures should I expect if it is unstable? Low > frequency flapping or high frequency ringing? > > Would things be different if I were using a switching regulator? > > I hacked in some extra load. That helps. With an external supply > making 3V and the extra load it actually works - or rather I haven't > provoked the problem on the bench. I haven't tried temp/power ranges. > > -- > These are my opinions, not necessarily my employers. I hate spam.Article: 27821
Hal, Oh, I forgot: the fluctuations trigger the POR circuit and the part shuts down (the voltage goes below the POR trip point). Then it starts all over again. Austin Hal Murray wrote: > In article <3A32EA0F.AB3B1A17@xilinx.com>, > Peter Alfke <peter.alfke@xilinx.com> writes: > > I would use the second LP3965 to make 1.8 from 5 V. That avoids > > cascading two "amplifiers", which is always a tricky proposition. > > You lose nothing by running the two linear regulators in parallel, but > > you gain stability and peace of mind. > > Thanks. > > In hindsight, that seems like a good suggestion. (In my case, > the heat distribution is better that way too.) > > But I didn't find any mention of this in either the Xilinx data > sheet or app note on Virtex power or the National data sheet or > their app note on linear regulators. I can't be the first one to > wire up two regulators this way. If this is such an obvious problem > why haven't the manufacturers mentioned it yet? > > I wired them this way because of some old memory about power > sequencing. I don't remember where that came from and there > isn't anything in the data sheet about it so I assume (now) > that it doesn't matter. > > I'm assuming/guessing that this particular problem is noise related. > The board fails between 38-42 MHz. It works below 38 or above 42. > The 40 MHz range is where the transmit and receive clocks line up > and the noise gets a lot worse. I didn't see any mention of noise > in the National app note. Their data sheets don't even have any > good stability data, just things like "at least 10 uF". (Remindes > me of trying to get metastability data.) > > This feels like a bogus shutdown rather than an instability problem. > What sort of scope pictures should I expect if it is unstable? Low > frequency flapping or high frequency ringing? > > Would things be different if I were using a switching regulator? > > I hacked in some extra load. That helps. With an external supply > making 3V and the extra load it actually works - or rather I haven't > provoked the problem on the bench. I haven't tried temp/power ranges. > > -- > These are my opinions, not necessarily my employers. I hate spam.Article: 27822
On page 78 of EETimes, October 16 in the letters from readers (crosstalk) section, a letter describes an interesting problem. (this section is not on- line, so you need the print copy). He writes to warn about replacing tantalum caps with ceramics, pointing out that they have a lower ESR. I only mention this because of the example he gives: Paraphrasing: LDO regs use com. emitter stage with high gain for LDO, and need the zero in the transfer function afforded by tantalums ESR to add stability. Without the zero, it is unstable, and oscillates. His failure case was replacing a 10uF tant with a 10uF ceramic that was associated with a LP2951 LDO. He got 1V P-P sine wave. On 11 Dec 2000 01:44:28 GMT, murray@pa.dec.com (Hal Murray) wrote: > power supply that sings. Philip Freidin FliptronicsArticle: 27823
Philip Freidin wrote: > On page 78 of EETimes, October 16 in the letters from readers (crosstalk) > section, a letter describes an interesting problem. (this section is not on- > line, so you need the print copy). > > He writes to warn about replacing tantalum caps with ceramics, pointing > out that they have a lower ESR. > > I only mention this because of the example he gives: > > Paraphrasing: > > LDO regs use com. emitter stage with high gain for LDO, and need > the zero in the transfer function afforded by tantalums ESR to add > stability. Without the zero, it is unstable, and oscillates. > > His failure case was replacing a 10uF tant with a 10uF ceramic > that was associated with a LP2951 LDO. He got 1V P-P sine wave. > > On 11 Dec 2000 01:44:28 GMT, murray@pa.dec.com (Hal Murray) wrote: > > > power supply that sings. > Philip Freidin > Fliptronics Is there any indication in the article that this has been seen with regulators from other manufacturers e.g. Maxim, Linear, Micrel, Unitrode etc ?Article: 27824
"Olivier R" <olivier.regnault@avnet.com> wrote in message news:ee6ef70.1@WebX.sUN8CHnE... > Rick, > > Xilinx has also a free development tool (WEBpack ISE) based on Foundation ISE. It supports XC9500 family, CoolRunner Family, Spartan 2 Family and Virtex 300E. Note that Modelsim XE starter is also free from Xilinx Website. It is not a size design limited tool. However, it is slower than the Modelsim XE which is not slower than the Altera Modelsim. There is also no time limitation, means that tools will work even after 1 year use. > <end orig> My license file for Modelsim XE starter has a 30day limit. If you are sure this is not time limited then please advise & I'll chase a correction. Anyone else? Dave
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