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Ramanathan <ramank@lucent.com> wrote: >Hi, > >what is meant by a Test Bench? > >Regards, >Ramanathan K. In the old days when people designed their systems with transistors and 74xx gates, they used to build prototypes on things called bread-boards. When a prototype was done, they took it to a bench where testing equipment stood (oscilloscopes, voltage sources, signal generators, etc.) and tested the prototype using these equipments. That bench was called test-bench. These days we write pieces of code which do exactly the same thing. One designs a chip and to test it one writes a test-bench which effectively supplies all the necessary input to the design, exercises different features of the design and observes the output (and maybe some/all of the internal states) to decide whether the design functions correctly wrt the specification. Hope this helps, Muzaffer FPGA DSP Consulting http://www.dspia.comArticle: 27776
This is possibly a stupid question, but I'll ask anyway... If I have an internal FF (say a counter to reduce the incoming GCK frequency), and then clock a lot of internal FF's from an output of this counter, will this "slow clock" be carried internally over low-skew interconnects? Or is this not recommended to drive FF clocks with anything other than global clock inputs??? Thanks, PaulArticle: 27777
Neil Franklin <neil@franklin.ch.remove> writes: > Mail to the address given on the page (JBits@xilinx.com). They then I wrote: > Too bad they don't answer their email. I guess they don't need any > new customers. I spoke too soon. I finally received a reply. I guess I've gotten too accustomed to automated systems for this sort of thing, and didn't expect to have to wait six days for a reply from a real person. Anyhow, now I have the info on where to get JBits. :-)Article: 27778
Eric Smith <eric-no-spam-for-me@brouhaha.com> writes: > I wrote: > > It says "JBits will be available over the web in 1Q99." > > But I can't seem to actually find it. Any hints? > > Neil Franklin <neil@franklin.ch.remove> writes: > > Mail to the address given on the page (JBits@xilinx.com). They then > > send you an URL (actually 3 URLs, Windows NT, Solaris, Linux) plus > > password. Then download (9MByte), install and have fun. > > Too bad they don't answer their email. I guess they don't need any > new customers. Funny. They answered my mail from Sun, 12 Nov 2000 19:35:06 +0100 on Mon, 13 Nov 2000 11:02:55 -0800 Having a bad week? JBits handler off on vacation/conference/sick? -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, MysticArticle: 27779
Paul Taylor wrote: > This is possibly a stupid question, but I'll ask anyway... > > If I have an internal FF (say a counter to reduce the incoming GCK > frequency), and then clock a lot of internal FF's from an output of > this counter, will this "slow clock" be carried internally over low-skew > interconnects? > > Or is this not recommended to drive FF clocks with anything > other than global clock inputs??? > > Thanks, > Paul I've just tried this out with Verilog/Synplify & it appears not. In fact Synplify assumes that this is possible and puts a BUFG on the internally generated clock which causes NGDBUILD to error out! Looking at the Lib guide it says that for the 95K series a BUFG is *always* implemented in the IOB. Unless I'm missing something you have 2 options: o Take the slow clock off chip and then back on via a global clock pin. o Use the slow clock as a clock enable - easy with the XL series since the macrocell FFs have CE inputs.Article: 27780
"Paul Taylor" <p.taylor@ukonline.co.uk> wrote in message
news:d2SX5.15908$bp4.228253@monolith.news.easynet.net...
> This is possibly a stupid question, but I'll ask anyway...
>
> If I have an internal FF (say a counter to reduce the incoming GCK
> frequency), and then clock a lot of internal FF's from an output of
> this counter, will this "slow clock" be carried internally over low-skew
> interconnects?
>
> Or is this not recommended to drive FF clocks with anything
> other than global clock inputs???
>
> Thanks,
> Paul
I just placed and routed another guy's design using a Spartan chip, and
he did exactly what you are doing. One of the internal counter output bits
is used as a clock to toggle other flip flops.
For several reasons, I am changing his design. Instead of using this
internal clock, I am going to generate a clock enable signal that will tell
the subsequent flip flops to toggle. Those flip flops will use the same
clock as the internal counter.
This has several benefits such as keeping all flip flops on the same
clock domain, minimizing skew of the final signals (since they are generated
off the same clock), not worrying about whether the new internal clock will
meet timing, not worrying about how this new internal clock is routed, etc.,
etc.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Article: 27781This is a multi-part message in MIME format. ------=_NextPart_000_0066_01C06111.559A7CA0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi, Burch Electronic Designs has a range of low cost, easy-to-use FPGA proto kits. We support Atmel, Xilinx, Altera, Lucent and Actel. For picutres and specs see www.BurchED.com.au Prices start at US$60. In a few days time we will be releasing a 200K gate Xilinx kit which will have an introductory price of US$120!!! Regards Tony Burch www.BurchED.com.au "The lowest cost, easiest-to-use FPGA prototyping kits." "Bassem" <bassem.abdel-aziz@alcatel.com> wrote in message = news:90lo36$n3r$1@kannews.ca.newbridge.com... Hi, I am looking for an FPGA starter kit. Atmel's ATSTK40 looks like a = perfect candidate, but it looks like they don't make it anymore (I may be = wrong about that). Any suggestions on alternative kits or about how to buy = the Atmel one? Thanks Bassem ------=_NextPart_000_0066_01C06111.559A7CA0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 5.50.4522.1800" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY bgColor=3D#ffffff> <DIV><FONT size=3D2>Hi,</FONT></DIV> <DIV><FONT size=3D2></FONT> </DIV> <DIV><FONT size=3D2>Burch Electronic Designs has a range of low = cost,</FONT></DIV> <DIV><FONT size=3D2>easy-to-use FPGA proto kits. We = support</FONT></DIV> <DIV><FONT size=3D2>Atmel, Xilinx, Altera, Lucent and = Actel.</FONT></DIV> <DIV><FONT size=3D2>For picutres and specs see <A=20 href=3D"http://www.BurchED.com.au">www.BurchED.com.au</A></FONT></DIV> <DIV><FONT size=3D2></FONT> </DIV> <DIV><FONT size=3D2>Prices start at US$60.</FONT></DIV> <DIV><FONT size=3D2></FONT> </DIV> <DIV><FONT size=3D2>In a few days time we will be releasing a 200K=20 gate</FONT></DIV> <DIV><FONT size=3D2>Xilinx kit which will have an introductory price of=20 US$120!!!</FONT></DIV> <DIV><FONT size=3D2></FONT> </DIV> <DIV><FONT size=3D2>Regards</FONT></DIV> <DIV><FONT size=3D2></FONT> </DIV> <DIV><FONT size=3D2>Tony Burch</FONT></DIV> <DIV><FONT size=3D2><A=20 href=3D"http://www.BurchED.com.au">www.BurchED.com.au</A></FONT></DIV> <DIV><FONT size=3D2>"The lowest cost, easiest-to-use FPGA</FONT></DIV> <DIV><FONT size=3D2>prototyping kits."</FONT></DIV> <DIV><FONT size=3D2></FONT> </DIV> <BLOCKQUOTE=20 style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; = BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px"> <DIV>"Bassem" <<A=20 = href=3D"mailto:bassem.abdel-aziz@alcatel.com">bassem.abdel-aziz@alcatel.c= om</A>>=20 wrote in message <A=20 = href=3D"news:90lo36$n3r$1@kannews.ca.newbridge.com">news:90lo36$n3r$1@kan= news.ca.newbridge.com</A>...</DIV>Hi,<BR><BR>I=20 am looking for an FPGA starter kit. Atmel's ATSTK40 looks like a=20 perfect<BR>candidate, but it looks like they don't make it anymore (I = may be=20 wrong<BR>about that). Any suggestions on alternative kits or about how = to buy=20 the<BR>Atmel=20 one?<BR><BR>Thanks<BR>Bassem<BR><BR><BR><BR></BLOCKQUOTE></BODY></HTML> ------=_NextPart_000_0066_01C06111.559A7CA0--Article: 27782
> This has several benefits such as keeping all flip flops on the same > clock domain, minimizing skew of the final signals (since they are generated > off the same clock), not worrying about whether the new internal clock will > meet timing, not worrying about how this new internal clock is routed, etc., > etc. You didn't mention the really big advantage. That's the style that the tools are expecting you to use. They will work much better if you cooperate. And that's the way the FEs and people on this newsgroup will expect your design to work so you will get more/better help from them. -- These are my opinions, not necessarily my employers. I hate spam.Article: 27783
Hi, Anyone out there happen to know if there is available IP for de-interleaver with matrix size of 47 row * 128 column used in ATM AAL1 re-assembly process. The Altera IP only provide up to 40 row. SherdynArticle: 27784
Just did that... The slow clock doesn't need to go off the chip and back in... it just needs to go to an IOB and back in. There Xilinx web site has plenty of info on how to do it. Bob. Rick Filipkiewicz wrote: > > Paul Taylor wrote: > > > This is possibly a stupid question, but I'll ask anyway... > > > > If I have an internal FF (say a counter to reduce the incoming GCK > > frequency), and then clock a lot of internal FF's from an output of > > this counter, will this "slow clock" be carried internally over low-skew > > interconnects? > > > > Or is this not recommended to drive FF clocks with anything > > other than global clock inputs??? > > > > Thanks, > > Paul > > I've just tried this out with Verilog/Synplify & it appears not. In fact > Synplify assumes that this is possible and puts a BUFG on the internally > generated clock which causes NGDBUILD to error out! > > Looking at the Lib guide it says that for the 95K series a BUFG is *always* > implemented in the IOB. Unless I'm missing something you have 2 options: > > o Take the slow clock off chip and then back on via a global clock pin. > > o Use the slow clock as a clock enable - easy with the XL series since the > macrocell FFs have CE inputs.Article: 27785
This is a multi-part message in MIME format. --------------CAB3582310F7B3FDAEA7D647 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Thank you very much Mr.John Regards Anup John Ayer wrote: > Hi Anup, > > There are a couple of APP notes you may find useful. One is XAPP 138 > "Virtex Configuration and Readback" located at: > http://support.xilinx.com/xapp/xapp138.pdf . Another is XAPP 151"Virtex > Series Configuration Architecture User Guide" located at: > http://support.xilinx.com/xapp/xapp151.pdf . > XAPP 151 goes in to much more detail on performing readback than 138, so > if this is your first attempt I would suggest reading 138 first to get a > feel for what is going on before looking at 151. > > Other Virtex APP notes can be found at: > http://support.xilinx.com/apps/virtexapp.htm. > > Hope this helps, > Regards, > John > > anup wrote: > > > Hello, Can someone give me starters on implementing designs that needs > > to be partially reconfigured in the Xilinx Virtex FPGAs. > > I am usign the Xilinx Foundation 3.1 series tools. > > Thanks and regards > > Anup --------------CAB3582310F7B3FDAEA7D647 Content-Type: text/x-vcard; charset=us-ascii; name="anup.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for anup Content-Disposition: attachment; filename="anup.vcf" begin:vcard n:Anup Kumar;Raghavan tel;home:+61-7-38761962 tel;work:+61-7-33658849 x-mozilla-html:TRUE url:www.elec.uq.edu.au/~anup org:University of Queensland;Computer Science & Electrical Engineering version:2.1 email;internet:anup@elec.uq.edu.au adr;quoted-printable:;;47/401, Dept. of CSEE, UQ, =0D=0A=0D=0A;St.Lucia, Brisbane ;Queensland;4072;Australia fn:Anup end:vcard --------------CAB3582310F7B3FDAEA7D647--Article: 27786
Opps. I was trying to email this to family. Maybe they got my Xilinx question. Sorry about posting here. -- Sincerely Daniel DeConinck High Res Technologies, Inc.Article: 27787
Can somebody (great if you are in Australia) tell me where can I buy a PLCC package adapter for some of the Xilinx FPGA/CPLD. I'm trying to build the circuit as shown in the "Design Lab book?" of the Xilinx F1.5 xilinx package. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27788
I found that Altera has a free version of the Max+ development tools on their web site. They also provide free versions of LeonardoSpectrum and Synopsys FPGA Express synthesis tools. But I am sure that the synthesis tools have some limitations. Does anyone know what they are? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX URL http://www.arius.comArticle: 27789
Hi, all. I was under the impression that Xilinx was making sure that the Spartan-II devices were completely pin-compatable with the Vertex devices. I'm using a FGA456 package, with no problem. But when I look at the datasheets for the Spartan-II family and the small end of the Vertex family the TQFP144 package does *not* seem to be pin compatable. Am I reading the data sheet wrong or something? If I could hear (read?) another voice say "You're right", or "You're wrong", I'd feel better. Thanks! -KentArticle: 27790
In article <90psu3$qjl$1@nnrp1.deja.com>, nhduong@my-deja.com wrote: > Can somebody (great if you are in Australia) tell me where can I buy a > PLCC package adapter for some of the Xilinx FPGA/CPLD. I'm trying to > build the circuit as shown in the "Design Lab book?" of the Xilinx F1.5 > xilinx package. I've found it quite easy to just put a PLCC socket onto a prototyping board - no adaptor required. Leon -- Leon Heller, G1HSM Tel: (Mobile) 079 9098 1221 (Work) +44 1327 357824 Email: leon_heller@hotmail.com Web: http://www.geocities.com/SiliconValley/Code/1835 Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27791
I installed maxplus2 10.0 and had still the same errors. I then replaced some of the includes by their full path what made most of the errors dissapear. Summa sumarum...I've decided to use CSFIFO instead and to externally synchronize. Thanks for all the input! JonasArticle: 27792
We had a postgrad student project a few years ago that investigated the internal interconnections of a Xilinx device. The old Xilinx 2064 device was chosen as being the simplest. He mananged to develop a method of discovering the interconnect positions purely experimentally. This was done by changing a single bit in the programming code file and then observing the difference in Xilinx's "World View" graphics package option. Phrases like "needles in haystacks" springs to mind. I think the project demonstrated that the major FPGA companies even then, "built in" randomness into their internal configuration schemes to make reverse engineering more difficult. He found that a certain configuration bit in one device would be totally different to another device, even within the same family. Hence the project finished with those conclusions. ___________________________________________ H A R V E Y T W Y M A N Department of Electronics, University of Kent. Canterbury. U.K. ABOUT ME: http://www.Twyman.org.uk/CV.htm EMAIL ME: H.E.Twyman@ukc.ac.uk ___________________________________________ Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27793
We ONLY use Altera Maxplus II for teaching. We also use their VHDL compiler but mainly projects use Altera's MegaFunctions to define VERY SIMPLE functional structures at the schematic level. The name MegaFunctions is a bit vague, they are similar to Xilinx's X- BLOX which is a much better name. You define your circuit using functional blocks (BLOX in Xilinx speak) in a similar way to a "Block Diagram". The blocks however are fully programmable i.e. A MegaFunction COUNTER can be configured to: - count up or down - start counting at a certain number ( reset to that number) - finish counting at a certain number ( the MODULUS ) - count up to very large numbers ( the limit would be the physical propeties of the device used) All in a simple BOX on the schematic. We find that this is MUCH easier for students to come to terms with than defining circuits at the gate level. ___________________________________________ H A R V E Y T W Y M A N Department of Electronics, University of Kent. Canterbury. U.K. ABOUT ME: http://www.Twyman.org.uk/CV.htm EMAIL ME: H.E.Twyman@ukc.ac.uk ___________________________________________ In article <memo.20001127184529.1372G@steve.rsn-tech.co.uk>, steve@rsn-tech.co.uk wrote: > In article <4DuR5.40671$Ze6.8222612@typhoon.tampabay.rr.com>, > sramirez@deleet.cfl.rr.com (S. Ramirez) wrote: > > > Rex, > > Perhaps your students will learn a valuable real world lesson from > > Mark -- after all of the arguments are heard about how great a certain > > vendor's tools are, most of the time the decision boils down to cost! > > But Altera have a free package too! > > > -Simon Ramirez, Consultant > > Synchronous Design, Inc. > > > > > > ******************************************************************** > > "Mark Harvey" <mark.harvey@iol.it> wrote in message > > news:8bqR5.81326$BF.2913634@news.infostrada.it... > > > Why not use the Xilinx Webpack? -it will allow your students to use > > > both > > > CPLDs and Spartan-II and Virtex 300E FPGAs - and it's free! > > -- > Steve Rencontre http://www.rsn-tech.co.uk > //#include <disclaimer.h> > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27794
You may wish to consider using a low cost FPGA proto kit. See http://www.burched.com.au/bedxilinxbase.html A kit like this saves alot of time, and gets you up-and-running quickly. It comes with the download pod cable also. Burch Electronic Designs is in Australia. Regards Tony Burch www.BurchED.com.au <nhduong@my-deja.com> wrote in message news:90psu3$qjl$1@nnrp1.deja.com... > Can somebody (great if you are in Australia) tell me where can I buy a > PLCC package adapter for some of the Xilinx FPGA/CPLD. I'm trying to > build the circuit as shown in the "Design Lab book?" of the Xilinx F1.5 > xilinx package. > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 27795
AVNET Europe is selling Xilinx Design Kit which includes Foundation ISE (Xilinx Development tool) + demo board (Spartan2 100K gates) + Download cable. Refer to your local sales office. Olivier REGNAULT Avnet franceArticle: 27796
Rick Collins wrote: > > I found that Altera has a free version of the Max+ development tools on > their web site. They also provide free versions of LeonardoSpectrum and > Synopsys FPGA Express synthesis tools. But I am sure that the synthesis > tools have some limitations. Does anyone know what they are? Rick, I think they're just limited to Synthesising designs targeted at the Altera devices covered in the free version of Maxlus2. From their web site (OEM tools info link from the download page) > OEM Version Information > > FPGA Express-Altera version 3.5 is tailored for Altera devices. The feature > set is identical to standard FPGA Express software: > > Altera-specific architecture optimizations > Static timing analysis > Constraint management > Schematic viewer to view the register transfer level (RTL) code as a > schematic and inspect the design for inferred operators > Integrated FPGA Scripting Tool which supports a Tcl based command-line > language > > The full range of FPGA Express synthesis flows are supported: > > Push-button > Constraint-based > Hierarchical > Script-based synthesis > > Integration with Altera's Quartus[tm] tools is also provided, allowing the > ability to launch Quartus from within FPGA Express. I've downloaded this, but I've never used FPGA Express before so it's hard to say if it looks like the 'full' version or not. Note that the Altera tool set is only $2K and for that you get a version of Modelsim which isn't limited to any size of design (and is 50% quicker than Modelsim XE) and FPGA Express or Exemplar Spectrum with Quartus and Maxplus2 which between them allow any Altera device to be targeted. It also _isn't_ time base licensed, after a year you don't get any more free tool updates or suport but all tools (including third party) will continue to work and new designs can be started. There was some discussion about the stability of Quartus when it first came out but as that was over 18 months ago I would have expected it to be sorted by now. With this in mind an Altera tool licence seems a lot better value than the Xilinx tools. Nial. Nial.Article: 27797
anup wrote: > > Hello, Can someone give me starters on implementing designs that needs > to be partially reconfigured in the Xilinx Virtex FPGAs. > I am usign the Xilinx Foundation 3.1 series tools. > Thanks and regards > Anup The other option to XAPP151 etc is JBits. We have a full toolkit which allows you to either manipulate designs made with standard tools, or to construct Virtex bitstreams from scratch using our library of parameterised cores. Partial configuration is naturally supported. Drop a line to jbits@xilinx.com to get the latest version Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 27798
Rick, Xilinx has also a free development tool (WEBpack ISE) based on Foundation ISE. It supports XC9500 family, CoolRunner Family, Spartan 2 Family and Virtex 300E. Note that Modelsim XE starter is also free from Xilinx Website. It is not a size design limited tool. However, it is slower than the Modelsim XE which is not slower than the Altera Modelsim. There is also no time limitation, means that tools will work even after 1 year use. Note also that the quality of result and the ease of use allows Xilinx to give the best tool. Regards Olivier RArticle: 27799
Harvey, As a professor who taught EECS 150 (Introduction to Digital Logic) at UC Berkeley, I would have been in heaven if a program like this had been in place 23 years ago: http://university.xilinx.com/univ/index.htm I would hope that the usefulness of having Virtex FPGA knowledge is a consideration, (best selling FPGA for two generations now, soon to be a third...) We agressively support schools through the University program. Parts, software ... check it out. Austin harveytwyman@my-deja.com wrote: > We ONLY use Altera Maxplus II for teaching. We also use their VHDL > compiler but mainly projects use Altera's MegaFunctions to define VERY > SIMPLE functional structures at the schematic level. > > The name MegaFunctions is a bit vague, they are similar to Xilinx's X- > BLOX which is a much better name. > > You define your circuit using functional blocks (BLOX in Xilinx speak) > in a similar way to a "Block Diagram". > > The blocks however are fully programmable i.e. > > A MegaFunction COUNTER can be configured to: > > - count up or down > > - start counting at a certain number ( reset to that number) > > - finish counting at a certain number ( the MODULUS ) > > - count up to very large numbers ( the limit would be the physical > propeties of the device used) > > All in a simple BOX on the schematic. > > We find that this is MUCH easier for students to come to terms with > than defining circuits at the gate level. > > ___________________________________________ > > H A R V E Y T W Y M A N > > Department of Electronics, > University of Kent. > Canterbury. U.K. > > ABOUT ME: http://www.Twyman.org.uk/CV.htm > EMAIL ME: H.E.Twyman@ukc.ac.uk > ___________________________________________ > > In article <memo.20001127184529.1372G@steve.rsn-tech.co.uk>, > steve@rsn-tech.co.uk wrote: > > In article <4DuR5.40671$Ze6.8222612@typhoon.tampabay.rr.com>, > > sramirez@deleet.cfl.rr.com (S. Ramirez) wrote: > > > > > Rex, > > > Perhaps your students will learn a valuable real world lesson > from > > > Mark -- after all of the arguments are heard about how great a > certain > > > vendor's tools are, most of the time the decision boils down to > cost! > > > > But Altera have a free package too! > > > > > -Simon Ramirez, Consultant > > > Synchronous Design, Inc. > > > > > > > > > ******************************************************************** > > > "Mark Harvey" <mark.harvey@iol.it> wrote in message > > > news:8bqR5.81326$BF.2913634@news.infostrada.it... > > > > Why not use the Xilinx Webpack? -it will allow your students to > use > > > > both > > > > CPLDs and Spartan-II and Virtex 300E FPGAs - and it's free! > > > > -- > > Steve Rencontre http://www.rsn-tech.co.uk > > //#include <disclaimer.h> > > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy.
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