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Rick Filipkiewicz wrote: > > Does anybody have any info/datasheet on these parts ? It seems a strange > situation that I can go all the way from synthesis through to > place&route but I don't know what's actually in these devices ?!. I'm > sort of assuming that they relate to Virtex in the same kind of way that > Spartan1 related to the smaller XC4K series parts. I remember a short discussion with a Xilinx FAE a few months ago. The devices do not exist yet but the whole sotware is already ready for them. They are, exactly as you suppose, "cheap" versions of the Virtex, as Spartan are "cheap" versions of the XC40xx. Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel 00 33 1 46 67 51 11 92400 COURBEVOIE Fax 00 33 1 46 67 51 01 FRANCEArticle: 19726
Hi, Thanks for all the responses... I have got hold of the few RS codec programs, still playing ard with them... How does the actual encoding and decoding process vary with the shortened RS code, say RS (26,24)? Can I just feed in the data byte(m=8) into the encoder (shift registers) as per normal? ie. shift in 24 data bytes ( and shift another 2 empty bytes??) and the register content is the 2 parity bytes? I have a few sets of sample answer but I can never get to the answer no matter how i shift... btw, how do u shorten the normal RS(31,27) (double error correcting??) to RS(26,24) ? Thanks for all helps/advice :-) MKYap <jhirbawi@yahoo.com> wrote in message news:85b91j$2tn$1@nnrp1.deja.com... > In article <84savt$bo2$1@violet.singnet.com.sg>, > "MK Yap" <mkyap@ieee.org> wrote: > > Hi, > > > > I'm writing a prog (VHDL or C) to enable block encoding and decoding > of CD > > sectors. In the ECC (error correction coding) field, RSPC(Reed > Solomon > > Product Code) is used. The RSPC is a product code over GF(2^8) > producing P > > and Q parity bytes. The GF(2^8) field is generated by the primitive > > polynomial > > P(x) = x^8 + x^4 + x^3 + x^2 + 1 > > The P parities are (26,24) RS codeword over GF(2^8) and the Q parities > are > > (45,43) RS codeword over GF(2^8). > > > > My question is: How can I write the encoding and decoding algorithm > for the > > ECC field?? The RS used are non standard RS codes (n,k) in which n is > > usually n=2^m -1 which m=8 in this case... > > I tried to look for more info from books but it is really limited... I > came > > across some books saying that conventional RS decoding can be used.. > that is > > the berlekamp, Peterson and Weldon algorithm. But I see no connection > > between them coz the derivation is based on a fundamental which is > > different. > > > > Pls enlighten... by providing some books, paper, web site or perhaps > > explanation of theory behind them... Thank you very much!! > > You're dealing with shortened Reed-Solomon codes; you may not find much > that specifically describes their encoding and decoding beacause it is > almost the same as the non-shortened version. For the encoder, encode as > a generic cyclic code over GF(2^8). For the decoding the Euclidean > Algoithm decoder will work for the shortened codes the same way it would > for the non-shortened ones with n=your codeword length instead of 2^m-1. > I'm sure the Berlekamp-Massey algorithm will also work with only minor > modifications. > > Jacob Hirbawi. > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 19727
This email is the first email in the PCI/USB project by opencores group You are welcomed to join us ======================================================== Hi, Before we start the work in the cores design we have to define few things. We should get information about PCI and USB standards and design tips ( I posted few links the last time and I still looking for more) I hope once we proved that we are able to develop a good system may be we can get some support from the PCI or USB groups and I'll try to contact them so as to get the specs or test suits. Documentation: text files is the most portable format or latex can be used to write our design documentation instead of the MS stuff that are not portable. The project should be divided into small subprojects for example we could have : the main controller, the optional blocks, the arbiter and test suite. Development platform: we need to make our platform as much as possible generic and platform independent and it will be excellent if we port it to many platforms. Project schedule: 1. defining the spec and the subprojects. 2. defining the functionality of the main blocks. 3. defining the blocks interfaces. 4. defining the archs, the states and timing of the blocks 5. selecting some tools and platforms 6. design implementation. 7. verification 8. testing on real system could you please comment on the schedule as a first step we have to understand the diff between the available bus standards (e.g. PCI64/66MHz, PCI-X, CompactPCI- USB v1 & USB v2) and all optional and required features of the busses. Thanks Jamil Khatib OpenIP Organization http://www.openip.org OpenIPCore Project http://www.openip.org/oc OpenCores Project http://www.opencores.orgArticle: 19728
thanks for your hint with the dll. i now use one dll and 2 global buffer to distribute the clock in my design. this seems to be the best way. but one question i still have. I placed the dll and the clock buffers in VHDL, but how do i assign properties like CLKDV_DIVIDE or STARTUP_WAIT in the VHDL code ? Are they generics or attributes ? Bye, Kai. -- ------------------------------------------ Dipl. Ing. Kai Troester IMMS - Institut fuer Mikroelektronik- und Mechatronik-Systeme gGmbH Langewiesener Strasse 22 98693 Ilmenau Germany Tel: +49(3677)6783-42 Fax: +49(3677)6783-38 E-mail: kai.troester@imms.de -------------------------------------------Article: 19729
Christoph Cronimund <christoph.cronimund@active.ch> wrote in message news:855e0r$ark$1@dino.active.ch... > At Siemens Switzerland's R&D department, I have developed and implemented an > adaptive digital filter based on the computational efficient Lapped Is source code available? regards, DamjanArticle: 19730
Hi everybody, does anyone know how fast (in terms of clock speed or/and in terms of performance) and how big is the fastest 32 bit RISC in FPGA (not restricted to any particular FPGA vendor). Processor can be commercial or open source. It would be best if it is with caches and MMU. Thanks. regards, DamjanArticle: 19731
Hi,
I had a few seconds and looked up the security features in the Gatefield device
(marketed by Actel) and this is what their www site says:
4.What security features does ProASIC provide?
Its non-volatility eliminates the need of a boot
PROM, thus eliminating the pirating of bit-streams
at start-up. A read back security bit prevents
programming content from being read from the device.
IP vendors will be able to license their IP to
specific ProASIC devices.
----------------------------------------------------------------------
rk The world of space holds vast promise
stellar engineering, ltd. for the service of man, and it is a
stellare@erols.com.NOSPAM world we have only begun to explore.
Hi-Rel Digital Systems Design -- James E. Webb, 1968
rk wrote:
> Hi,
>
> I'm not intimately familiar with the Gatefield products and their security
> provisions, but perhaps they will fit your needs, as they do store their
> configuration in EEPROM.
>
> Have a good evening,
>
> rk
>
> =================================
>
> Richard Erlacher wrote:
>
> > The whole problem of theft risk would go away if the FPGA makers would
> > put the config EEROM inside the FPGA. That wold save space,
> > uncomplicate the board layout process, and let more of us sleep at
> > night.
> >
> > Everything the FPGA vendors do, however, is to benefit them. THEY
> > sell more devices when there is competition from counterfeiters, at
> > list in the first quarter . . . and, like most businesses, they don't
> > care about the second quarter.
> >
> > If the FPGA vendors, e.g. XILINX ever do offer a device with an
> > internal, not externally visible config device, I'd look for its pins
> > to contain the information they currently get from outside the device
> > since they still want to reatin the ability to read YOUR IP if it's of
> > any value. They also profit from the counterfeiting, even though
> > everyone else loses.
Article: 19732Has anyone used these or even know how they work? thx m Matt Billenstein http://w3.one.net/~mbillens/ mbillens@one.netArticle: 19733
Kresten Nørgaard wrote in message <857h4h$96j$1@news.inet.tele.dk>... >Hi group! >I'm looking into a new design, consisting of 4 pcs. of 32-bit 100 MHz >asynchronous counters. When stopped, the counters are emptied into a FIFO >(common to all counters - 32 kbyte size total). The FIFO's will be read >through an ordinary 8 MHz CPU interface. Question: why an async counter? Especially at 100 MHz? you'd better off with a synchronous counter and some logic that generates count enables. -- a ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu Spelling Counts! You don't loose your money - you lose it.Article: 19734
George wrote in message <856cle$a99$1@news.qub.ac.uk>... >Hi folks, > >Is Xilinx 4000 configuration bitstream structure open to public. No. > In other words, is it possible for us to edit bitstream. No. >If the structure of the >circuit is known in advance (placement and routing), why should people go >through the lengthy process of Xilinx tools (A lot of DSP aarchitectures are >quiet regular). Are you saying that you've floorplanned your design, and all that's left is to convert it to the bitstream? >How about Virtex? no. -- a ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu Spelling Counts! You don't loose your money - you lose it.Article: 19735
If you are doing a structural construction (not a bad idea for lots of DSP applications), you might look at JHDL developed by BYU. It gives you much better control over placement and implementation than you get with VHDL. I think the output still goes through the xilinx tools, so that you don't have to specify the pips, switch connections etc. Andy Peters wrote: > George wrote in message <856cle$a99$1@news.qub.ac.uk>... > >Hi folks, > > > >Is Xilinx 4000 configuration bitstream structure open to public. > > No. > > In other words, is it possible for us to edit bitstream. > > No. > > >If the structure of the > >circuit is known in advance (placement and routing), why should people go > >through the lengthy process of Xilinx tools (A lot of DSP aarchitectures > are > >quiet regular). > > Are you saying that you've floorplanned your design, and all that's left is > to convert it to the bitstream? > > >How about Virtex? > > no. > > -- a > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) noao \dot\ edu > > Spelling Counts! You don't loose your money - you lose it. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 19736
Haven't used them. They work based on the stong temperature dependence of the junction voltage. Matt Billenstein wrote: > Has anyone used these or even know how they work? > > thx > > m > > Matt Billenstein > http://w3.one.net/~mbillens/ > mbillens@one.net -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 19737
In article <85d9p9$18g4$1@noao.edu>, Andy Peters <apeters.Nospam@nospam.noao.edu.nospam> wrote: >George wrote in message <856cle$a99$1@news.qub.ac.uk>... >>Hi folks, >> >>Is Xilinx 4000 configuration bitstream structure open to public. > >No. >> In other words, is it possible for us to edit bitstream. > >No. Doesn't jbits support XC4000? Jbits gives you a means to edit the bitfiles in an abstract manner. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 19738
Hi,
If you are talking about the timing violations from the sequential
elements in your
design during simulation (like setup, hold etc.) I would suggest you to
look at the on-line
documentation of your simulator. For instance couple of months back I was
involved
in SDF Back annotated simulation with Verilog-XL and I found the on-line
manual
quite handy.
Hope this helps.
Regards,
Srini
<elynum@my-deja.com> wrote in message news:84u5lg$sa8$1@nnrp1.deja.com...
> Does anyone know where I can get a good book or article on timing
> diagrams? I haven't had a lot of experience when it comes to stuff like
> timing violations as far as I need something that will explain how to
> understand clock to output times, setup and hold times and their
> importance in simulation.
>
> Thanks
>
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
Article: 19739Robert Larkin wrote: > Regarding the on chip clock on Xilinx 4005 FPGAs. Are any any external RC > components needed? I couldn't seem to find an application note dealing with > this question. Also does any one have any real idea of its reliability? > > See the Xilinx data book page 6-27/28 for a description, and page 14-27 for an explanation of frequency tolerances. This is a totally on-chip oscillator; no external components are needed or possible. This oscillator is also used as configuration clock, so it obviously must be reliable. Every Xilinx device uses this oscillator for every configuration. There are no reliability concerns. Wide frequency tolerances are the only drawback. Peter Alfke, Xilinx ApplicationsArticle: 19740
> > stay in one level of logic. The bottom line here is if you are doing > clock enables, accumulators with load or synch clear, adder/subtractors > or any other 3 > or more input arithmetic you'll end up using 2 LE's > per bit per function. Most of the design uses enable signals to effectively reduce the sampling rate, while keeping a fully synchronous design .. We tried hard wiring the main enable signals to '1' to check the impact on resource usage [the design is not functional]. The results is not encouraging: Synplify estimates 92% device usage (before was 95%) NOTE that this is only about 2/3 of the design. The registers was reduced from 863 to 839, probably because the block generating the enable signals got optimized away. The registers with enable went from 728 downto 496. What is your experience with accuracy of Synplify's resource usage estimates for Altera Flex devices? If I'm interested in getting resource usage estimates for a specific, or for all, subblocks (or entities) how should I proceed? I failed to find detailed information in Synplify's output/log files. Is there a menu or command option that I missed? Will I get a good estimate by comparing resource usage estimates generated before and after deleting (blackboxing) the specific block? > > I wasn't sure if you had filters in there or not. How are they implemented? > FIR or IIR? how many coefficients? If you haven't already, you should look > at the distributed arithmetic algorithm. > The filter is an IIR with two internal taps, each 12 bit wide. The coefficients are fixed and have been optimized to contain a total of only about 7 or 8 single '1' bits (all coefficients together). Six such filters are used.Article: 19741
Intel pioneered this in Pentium. Peter Alfke Ray Andraka wrote: > Haven't used them. They work based on the stong temperature dependence > of the junction voltage. > > Matt Billenstein wrote: > > > Has anyone used these or even know how they work? > >Article: 19742
Matt, I assume that you're trying to figure out how to use it... It measure the voltage drop of a diode or transistor junction. Several suppliers make chips that can convert this voltage to a digital temperature - see Analog Devices web site for devices. One url is listed below: <http://products.analog.com/products/info.asp?product=ADM1020> Bob Matt Billenstein wrote: > > Has anyone used these or even know how they work? > > thx > > m > > Matt Billenstein > http://w3.one.net/~mbillens/ > mbillens@one.netArticle: 19743
Do you have the RTL analyzer for synplicity? If you do, you can look to see what the synthesis produced. I'm guessing that you've got alot of adders with more than just the two addend inputs. If an input is gated, or you have a synchronous clear, or an add-subtract control, any of those will push the adder implementation to two levels of logic. If that is the case, then deactivating the CE won't collapse those adders to a single level. Another issue related to having lots of parallel adders in the design is the fact that you wind up with alot of parallel or bus-wide connections on the row. The number of row wires in each row is only 3/4 of the number of LE's in the row, so unless you have some LE's that only connect within the LAB, then you are stuck with a maximum row utilization of 75%, and only if the fan-in is equivalent to the fan-out. Realistically, you will get an even lower utilization for circuits that have all the LAB connections to/from outside of the LAB because any given LE in a row can only connect to a rather limited subset of the other LE's in the row without having to use two row route segments and an LE to connect them. You can cut down on the enables in a filter if the adder tree is a tree with equal delays rather than a chain by using a data-valid signal. The delay register has to have enables to keep the samples stationary when input data is not valid, but the enables there a essentially free anyway, since you are probably not using the LUT in front of the register. If the delay queue is held stationary, the data from the last valid sample will ripple through the coefficient multiplies or tables and through the adder tree. The output of the adder tree will also need an enable (data valid signal) delayed to match the latency through the filter. By doing it that way, you eliminate the enables from the adder tree, which can help. In your case, where you probably have multiple levels of logic at each adder, it would help if you can push the gating or inversion back into a previous level to allow the logic using carry chains to stay at two inputs. Berni Joss wrote: > > > > stay in one level of logic. The bottom line here is if you are doing > > clock enables, accumulators with load or synch clear, adder/subtractors > > or any other 3 > or more input arithmetic you'll end up using 2 LE's > > per bit per function. > > Most of the design uses enable signals to effectively reduce the sampling > rate, while keeping a fully synchronous design .. > > We tried hard wiring the main enable signals to '1' to check the impact on > resource usage [the design is not functional]. The results is not > encouraging: > > Synplify estimates 92% device usage (before was 95%) NOTE that this is only > about 2/3 of the design. > The registers was reduced from 863 to 839, probably because the block > generating the enable signals got optimized away. > The registers with enable went from 728 downto 496. > > What is your experience with accuracy of Synplify's resource usage estimates > for Altera Flex devices? > > If I'm interested in getting resource usage estimates for a specific, or for > all, subblocks (or entities) how should I proceed? > I failed to find detailed information in Synplify's output/log files. Is > there a menu or command option that I missed? > Will I get a good estimate by comparing resource usage estimates generated > before and after deleting (blackboxing) the specific block? > > > > > I wasn't sure if you had filters in there or not. How are they > implemented? > > FIR or IIR? how many coefficients? If you haven't already, you should > look > > at the distributed arithmetic algorithm. > > > > The filter is an IIR with two internal taps, each 12 bit wide. > The coefficients are fixed and have been optimized to contain a total of > only about 7 or 8 single '1' bits (all coefficients together). > Six such filters are used. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 19744
I believe there is an appnote on the Xilinx website that addresses this in much more detail than I could here. IIRC, these are attributes you need to put on the instance, which if you are using Synplicity can be done with user attributes. Alternatively, you can define them in the constraints file. Kai Troester wrote: > thanks for your hint with the dll. i now use one dll and 2 global buffer > to distribute the clock in my design. this seems to be the best way. but > one question i still have. I placed the dll and the clock buffers in > VHDL, but how do i assign properties like CLKDV_DIVIDE or STARTUP_WAIT > in the VHDL code ? Are they generics or attributes ? > > Bye, Kai. > -- > ------------------------------------------ > Dipl. Ing. Kai Troester > > IMMS - Institut fuer Mikroelektronik- > und Mechatronik-Systeme gGmbH > > Langewiesener Strasse 22 > 98693 Ilmenau > Germany > Tel: +49(3677)6783-42 > Fax: +49(3677)6783-38 > E-mail: kai.troester@imms.de > ------------------------------------------- -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 19745
Hi, In the last few years the hardware resources for ASIC, FPGA, and CPLD designers was improved in the manner of hw size, speed and fabrication delay. SW programmers now also have high speed processors, large memories advanced compilers and visual tools. although all these resources are available for programmers, but -as I see- they do not improve their sw _in_the_same_ratio_as_the improvements_of_the_resources. For example all new sw versions need larger memories and faster processors without the increase of the functionality of the new version. This is because they always think that they will have larger memory and faster processors and they do not have time to optimize their code nor to calculate how much resources they need as they did in the past. Since the hardware technology becomes to offer to HW designers more than what they need I think they will start doing the same as what SW programmers doing now. Do you think like me? Do you know how can we prevent this? I think this can be prevented by following the Open Source and open Hardware design concepts in the design. You can read more about this idea in OpenIPCore Project at http://www.openip.org/oc Thanks Jamil Khatib OpenIP Organization http://www.openip.org OpenIPCore Project http://www.openip.org/oc OpenCores Porject http://www.opencores.orgArticle: 19746
On Mon, 10 Jan 2000 10:40:47 -0500, Matt Billenstein <mbillens@one.net> wrote: >Virtex Temperature Sensing diode pins DXP, DXN >Has anyone used these or even know how they work? Matt, Look at the datasheet for the LM84 (NS) or MAX1617 (etc) (Maxim) or ADM1021 (Analog Devices). Other manufacturers have them, but I can't remember the part numbers off hand. These parts are designed to measure processor temperature for commodity motherboards, so they have an SMB (like I2C) interface. http://www.national.com/pf/LM/LM84.html http://dbserv.maxim-ic.com/pl_list.cfm?filter=ts http://products.analog.com/products/info.asp?product=ADM1021 The trick is to measure the diode drop at two different current densities (typ 10:1 ratio). The difference in forward voltage can be used to calculate the temperature without depending on the diode characteristics too much. You can expect a few degrees error over a 50 degree range *without calibration*. There is another method that uses 3 different currents, and can calibrate out the effects of series resistance, but the chips mentioned above don't do that. For more details, see the following thread: http://www.deja.com/=dnc/[ST_rn=ps]/viewthread.xp?search=thread&recnum=%3c37131c68.28537681@newshost%3e%231/1&AN=465835970&svcclass=dnserver&frpage=getdoc.xp You might have to manually paste that URL... sorry. You need to read the whole thread, particularly the post about measuring die temperature by stuffing the part into a chicken and measuring how long the chicken takes to cook. If that URL doesn't work, try this one: http://www.deja.com/=dnc/[ST_rn=ps]/getdoc.xp?AN=466619186 See also US patents # 3,812,717 and # 5,195,827 Regards, Allan.Article: 19747
Hi, What, do you think, is the best FPGA for SDRAM controller ? Say, up to PC100 ? TIA, simonArticle: 19748
Hi to all, I am not shure this is the right newsgroup for my problem, but maybe someone can give me a hint or the name of a better fitting newsgroup. We are designing PCI-Framegrabber cards using standard PC-platforms and Windows98 The problem is that the Video Data DMA Burst via PCI-Bus sometimes stopps for about 30 microsec. While that time alle PCI Data-Transfers are aborted with a RETRY termination. As a consequence our Video Fifos get a Data Overflow! Maybe this is a problem with the cache controller an the motherboard. Is anybody dealing with a similar problem? thanks peterArticle: 19749
Hello,
As far as I can see (and you can call me a cynic if you like),
the increase in requirements of SW is driven by profit (of course). When
people see software that they (think) they need and it tells them tell
need to double their memory, or by a graphics accelerator, then they go
out and do it. This feeds the hardware industry by giving it challenges
to design new gizmos for the software people to develop with. Basically
it's a vicious circle. What it means also is when SW designers (and
hardware) come across a problem, they don't try to sort it out, they
just increase the resources available to themselves, and everything gets
bigger and more expensive !
PAT.
In article <387AD481.58C40A0C@ieee.org>, Jamil Khaib <Khatib@ieee.org>
writes
>
>Hi,
>In the last few years the hardware resources for ASIC, FPGA, and CPLD
>designers was improved in the manner of hw size, speed and fabrication
>delay.
>
>SW programmers now also have high speed processors, large memories
>advanced compilers and visual tools. although all these resources are
>available for programmers, but -as I see- they do not improve their sw
>_in_the_same_ratio_as_the improvements_of_the_resources. For example all
>new sw versions need larger memories and faster processors without the
>increase of the functionality of the new version. This is because they
>always think that they will have larger memory and faster processors and
>they do not have time to optimize their code nor to calculate how much
>resources they need as they did in the past.
>
>Since the hardware technology becomes to offer to HW designers more than
>what they need I think they will start doing the same as what SW
>programmers doing now.
>
>Do you think like me? Do you know how can we prevent this?
>I think this can be prevented by following the Open Source and open
>Hardware design concepts in the design. You can read more about this
>idea in OpenIPCore Project at http://www.openip.org/oc
>
>Thanks
>Jamil Khatib
>OpenIP Organization http://www.openip.org
>OpenIPCore Project http://www.openip.org/oc
>OpenCores Porject http://www.opencores.org
>
>
--
Pat
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