Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 83300

Article: 83300
Subject: Re: *RANT* Ridiculous EDA software "user license agreements"?
From: Ziggy <Ziggy@TheCentre.com>
Date: Wed, 27 Apr 2005 13:49:43 GMT
Links: << >>  << T >>  << A >>
David wrote:
> On Wed, 27 Apr 2005 11:42:58 +0000, Uwe Bonnes wrote:
> 
> 
>>In comp.arch.fpga license_rant_master <none@nowhere.net> wrote:
>>: I am an ASIC engineer who frequently 'takes work home' with me.
>>: Recently, I began using ssh to remotely login to our company's
>>: servers to run some Verilog/VHDL simulations.  Launching
>>: sims (from the UNIX command line) is fairly easy and painless,
>>: but any kind of interactive (GUI) operations are pitifully
>>: slow over an WAN/internet connection.  In the past, I
>>: haven't needed to do much more than check on running jobs,
>>: restart them, then logout.  Now, I find the need to do some
>>: interactive debugging work (waveform viewing, code editing,
>>: etc.)
>>
>>Look at NX. It what LBX (Low Bandwidth X ) promised, but NX
>>delivers. Probably not to easy to set yet, but worth a try. 
>>
> 
> 
> It's easy enough to set up the server (either look at the commercial
> version from www.nomachine.com, or google for "freenx" or "nxserver") on
> linux, and clients are even easier (download free from nomachine).  It is
> said to be usable over a modem connection - I have certainly found it
> works well over ADSL for most work.  It's definitely faster than tightVnc
> (which is also okay for many things - and works well for pretending you
> are sitting at your office windows desktop).
> 
> 
> 
>>Bye
> 
> 
> 
> 
Too bad its not easy to setup a server in FreeBSD ( i know, totaly OT )

Like others will most likely point out, something like TightVNC would 
support compression, and is even easier to setup then NX..

Article: 83301
Subject: Synplify warning CL209
From: "Mohammed A Khader" <am.imak@gmail.com>
Date: 27 Apr 2005 07:08:39 -0700
Links: << >>  << T >>  << A >>
Hello,

  When synthezing the design with Synplify Pro 8.0  it gave the
follwoing Warning.

  CL209   Input port bit <4> of spi_addrs(4 downto 0) is unsed.
  CL209   Input port bit <3> of spi_addrs(4 downto 0) is unsed.
  CL209   Input port bit <2> of spi_addrs(4 downto 0) is unsed.
  CL209   Input port bit <1> of spi_addrs(4 downto 0) is unsed.


  I am sure that I am using the slice  (4 downto 1)  as an input to the
mux.

 I tried by assigning this slice to an intermediate wire (signal)  and
then  to the mux input . But again it is giving the same error.

 Following is the relevant piece of code....
 ntity Ctrl_Ram is
	port(
	    Ctrl_Data_In : in  WORD;
		Ctrl_Addrs   : in  unsigned(3 downto 0);
		Spi_Addrs    : in  unsigned(4 downto 0);
		Ctrl_Wr      : in  std_logic;

		Intl_Rst     : in  std_logic;
		Clk          : in  std_logic;

		Reset        : in  std_logic;

		Data32_Out   : out DWORD;
		Data16_Out   : out WORD
		);
end entity Ctrl_Ram;

Architecture arch of Ctrl_Ram is
begin
 spi_addrs_intl <= Spi_Addrs(4 downto 1);
Addrs_Mux:process(Ctrl_Addrs,spi_addrs_intl,Intl_Rst)
	begin
		case Intl_Rst is
			when '0' => Addrs_In <= spi_addrs_intl;
			when '1' => Addrs_In <=  Ctrl_Addrs;

			when others => Addrs_In <= (others =>'X');
		end case;
	end process Addrs_Mux;   


 Thank you.

-- Mohammed A Khader.


Article: 83302
Subject: Virtex slow clock multiply options?
From: kevin@firebolt.com
Date: 27 Apr 2005 07:24:28 -0700
Links: << >>  << T >>  << A >>
Hello,

Please forgive me if this is a rather elementary problem.  My situation
is this:  I'm using a Virtex Device (XVC800) I believe that has is
being clocked with a 40 MHz and 10 MHz signal.  Main goal: the FPGA
creates two output 'clock' signals with varying frequency ('user'
selected freq, 50% duty), one between 500 kHz and 700 kHz and the other
exactly 16 times the frequency of the first.  Also, of course, provide
the 'user' with as much selection of frequencies between 500 and 700
kHz as possible (i.e. small granularity).

Thinking about it, I can only think of one way to do this.  Feed the 40
MHz clock through two DLL's to provide a 160MHz signal.  Have the
'user' provide a count of the # of 160 MHz clock cycles requested to
create the 16x freq signal and then slow down the signal (multiply the
count by 16) to create the 500 to 700 kHz signal.  Doing this, the
'user' is only able to select 6 different frequencies that will match
the range between 500 and 700.

I would of course love to just create the 500 to 700 kHz signal off of
the 40 MHz clock (providing 23 different freq. selections) then somehow
use the DLLs or other to multiply by 16, but the DLLs have a min input
freq. of 25 MHz.

Anyone have any ideas?  Everyone thoroughly confused as to what I'm
trying to do?  Anyone still reading this far?  

Thanks a bunch,

Kevin


Article: 83303
Subject: Re: Virtex slow clock multiply options?
From: "Gabor" <gabor@alacron.com>
Date: 27 Apr 2005 07:31:13 -0700
Links: << >>  << T >>  << A >>

k...@firebolt.com wrote:
> Hello,
>
> Please forgive me if this is a rather elementary problem.  My
situation
> is this:  I'm using a Virtex Device (XVC800) I believe that has is
> being clocked with a 40 MHz and 10 MHz signal.  Main goal: the FPGA
> creates two output 'clock' signals with varying frequency ('user'
> selected freq, 50% duty), one between 500 kHz and 700 kHz and the
other
> exactly 16 times the frequency of the first.  Also, of course,
provide
> the 'user' with as much selection of frequencies between 500 and 700
> kHz as possible (i.e. small granularity).
>
> Thinking about it, I can only think of one way to do this.  Feed the
40
> MHz clock through two DLL's to provide a 160MHz signal.  Have the
> 'user' provide a count of the # of 160 MHz clock cycles requested to
> create the 16x freq signal and then slow down the signal (multiply
the
> count by 16) to create the 500 to 700 kHz signal.  Doing this, the
> 'user' is only able to select 6 different frequencies that will match
> the range between 500 and 700.
>
> I would of course love to just create the 500 to 700 kHz signal off
of
> the 40 MHz clock (providing 23 different freq. selections) then
somehow
> use the DLLs or other to multiply by 16, but the DLLs have a min
input
> freq. of 25 MHz.
>
> Anyone have any ideas?  Everyone thoroughly confused as to what I'm
> trying to do?  Anyone still reading this far?
>
> Thanks a bunch,
>
> Kevin


This is simple and nothing new.  Google for "DDS" or Direct Digital
Synthesis.
There are a few threads in this group on the subject.


Article: 83304
Subject: Re: Virtex slow clock multiply options?
From: kevin@firebolt.com
Date: 27 Apr 2005 08:23:52 -0700
Links: << >>  << T >>  << A >>
Please correct me if I'm wrong (probable), but aren't DSS's used just
to create the numeric representation of a requested wave-shape.  Sorry
I didn't clarify in my original post, I only need to output a square
wave (0/1) over the standard FPGA I/O.  As I would still be clocking
the DSS at 40 MHz, I wouldn't be able to get better
resolution/granularity for frequencies between 500 to 700 kHz that
would be able to be multiplied by 16 based on a 40 MHz clock  Is there
a way to make the DSS asynchronous?  Sorry if I'm missing something
obvious.

Kevin


Article: 83305
Subject: Re: Synplify warning CL209
From: Bert Cuzeau <_no_spa_m_info_no_underscore_@alse-fr___.com>
Date: Wed, 27 Apr 2005 17:30:54 +0200
Links: << >>  << T >>  << A >>
Mohammed A Khader wrote:
> Hello,
> 
>   When synthezing the design with Synplify Pro 8.0  it gave the
> follwoing Warning.
> 
>   CL209   Input port bit <4> of spi_addrs(4 downto 0) is unsed.
>   CL209   Input port bit <3> of spi_addrs(4 downto 0) is unsed.
>   CL209   Input port bit <2> of spi_addrs(4 downto 0) is unsed.
>   CL209   Input port bit <1> of spi_addrs(4 downto 0) is unsed.
> 
> 
>   I am sure that I am using the slice  (4 downto 1)  as an input to the
> mux.
> 
>  I tried by assigning this slice to an intermediate wire (signal)  and
> then  to the mux input . But again it is giving the same error.
> 
>  Following is the relevant piece of code....
>  ntity Ctrl_Ram is
> 	port(
> 	    Ctrl_Data_In : in  WORD;
> 		Ctrl_Addrs   : in  unsigned(3 downto 0);
> 		Spi_Addrs    : in  unsigned(4 downto 0);
> 		Ctrl_Wr      : in  std_logic;
> 
> 		Intl_Rst     : in  std_logic;
> 		Clk          : in  std_logic;
> 
> 		Reset        : in  std_logic;
> 
> 		Data32_Out   : out DWORD;
> 		Data16_Out   : out WORD
> 		);
> end entity Ctrl_Ram;
> 
> Architecture arch of Ctrl_Ram is
> begin
>  spi_addrs_intl <= Spi_Addrs(4 downto 1);
> Addrs_Mux:process(Ctrl_Addrs,spi_addrs_intl,Intl_Rst)
> 	begin
> 		case Intl_Rst is
> 			when '0' => Addrs_In <= spi_addrs_intl;
> 			when '1' => Addrs_In <=  Ctrl_Addrs;
> 
> 			when others => Addrs_In <= (others =>'X');
> 		end case;
> 	end process Addrs_Mux;   
> 
> 
>  Thank you.
> 
> -- Mohammed A Khader.
> 

1. Why this complex code and not simply :

Addrs_In <= Spi_Addrs(4 downto 1) when Intl_Rst='0' else Ctrl_Addrs;

2. I don't think we see enough of the code to tell you where
exactly you got it wrong.
Maybe Addrs_In is not used when Intl_Rst='0' ?

Have you checked with simulation that somehow Spi_Addrs is
effectively used ?


Bert Cuzeau


Article: 83306
Subject: Re: Sync + FIFO
From: Duane Clark <dclark@junkmail.com>
Date: Wed, 27 Apr 2005 15:31:16 GMT
Links: << >>  << T >>  << A >>
ALuPin wrote:
> Duane Clark wrote:
> 
>>It makes no sense to say that you are going to "synchronize the data bus 
>>with some register stages". What will invariably happen when you try to 
>>do that is that some of the portions of the data bus will occasionally 
>>exit the last stage on different clocks. Each individual bit of the bus 
>>may be synchronized correctly, but the bus as a whole will not, without 
>>taking additional measures.
> 
> 
> Thank you for your answers.
> The external data stream I am talking about comes form an USB transceiver
> which sends the data synchronous to 60MHz clk which I can use in my FPGA
> as FIFO write clock. Under this assumption of synchronous data stream
> the portions of the data bus will NOT occasionally exit the last stage
> on different clocks, will they ?

That should work fine (assuming of course the FIFOs are designed right). 
In this case, the FIFOs are doing the synchronizing, not the registers.

Article: 83307
Subject: XC9500 - creating RS485 Mux
From: dima2882 <vadimv@ieee.org>
Date: Wed, 27 Apr 2005 08:38:31 -0700
Links: << >>  << T >>  << A >>
Hi all,

If anyone can think of why this idea may NOT work, please let me know - I want to try to build this. I need to make a serial signal breakout box, and I can't afford the card... so I want to take RS-422/485 signals, convert them to TTL with a converter chip, and use a CPLD as a Mux for the several TTL signals connected to it. The TTL signal that passes based on Mux setting is converted to RS-232 with a MAX232 chip, and goes to the PC. Can a XC9500 CPLD be made fast enough to keep up, for baud rate of 115kbs?

Thanks for all your suggestions.

Article: 83308
Subject: Re: Another Altera FPGA Development Board
From: "Alex Gibson" <news@alxx.net>
Date: Thu, 28 Apr 2005 01:41:32 +1000
Links: << >>  << T >>  << A >>

"Ziggy" <Ziggy@TheCentre.com> wrote in message 
news:wZwbe.22752$r53.15336@attbi_s21...
> Paolo wrote:
>> Hi,
>> This board:
>> http://www.altera.com/corporate/cust_successes/customer_showcase/csh-seventech_lp.html
>> has similar characteristics, besides is available a Software Dev Kit to 
>> immediately develop your program in C++.
>> My company, buy this board to develop gambling machine. Our company 
>> doesn't have an inside structure to develop hardware, but only software. 
>> Before we developed our software on PC platform. But the PC platform 
>> it's not good for an embedded use.  Now with this board we succeed in 
>> realizing excellent products.
>> On the web page of Seventech, you can also see a sample C++  code to 
>> realize a graphic animation with this board.
>> With this board it is possible to realize graphic animations with very 
>> good performance and the cost, also for the companies, it is <300$, for 
>> an only piece.
>>
>> Paolo
>>
>>
>>
>
> That does look interesting, too bad the FPGA doesnt have the dual PowerPC 
> cores included..
>
> What sort of free tools are available for the altera chips and are they 
> any good?

Altera Quartus
http://www.altera.com/products/software/products/quartus2web/sof-quarwebmain.html
http://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp
annoyance is having to re-request a license every so often.
Usually happens when you don't have net access
and sometimes can take a few days to get a new one.

Tools quite good.
If you started with xilinx can take bit to get used to.
Maybe a bit less buggy than xilinx tools in my experiance.
(don't crash as often on my machine or ones I have to help support)

Altera have a fpga with an arm core.
http://www.altera.com/products/devices/arm/arm-index.html

Alex 



Article: 83309
Subject: Re: webpack for os x or freebsd ?
From: "Alex Gibson" <news@alxx.net>
Date: Thu, 28 Apr 2005 01:53:34 +1000
Links: << >>  << T >>  << A >>

"Ziggy" <Ziggy@TheCentre.com> wrote in message 
news:qwxbe.23136$NU4.3286@attbi_s22...
> Alex Gibson wrote:
>> Has any one tried running 7.1 for linux on OS X or darwin or freebsd ?
>>
>> Even just commandline tools ?
>>
>> Trying to avoid having yet another computer(or dual boot)
>>
>> Alex
>
> Not sure how it could work if the linux they support is ix86.. OSX is PPC 
> remember...

darwin  the base of  OS X  has both ppc and x86 versions
and can be downloaded from

http://developer.apple.com/darwin/

http://www.opendarwin.org/

http://www.gnu-darwin.org/

It doesn't have any of the apple libraries that run on top of darwin
from OS X but can run X11 , kde , gnome etc  all the usuall bsd / linux 
programs.

Guess I need to get another x86 box then and vmware to run windows and 
linux.
need something for ise + edk and for building uclinux for microblaze

Alex 



Article: 83310
Subject: Re: Virtex slow clock multiply options?
From: Kolja Sulimma <news@sulimma.de>
Date: Wed, 27 Apr 2005 18:11:04 +0200
Links: << >>  << T >>  << A >>
You take your reference clock and multiply it with the DCM to somthing
like 100MHz, or a little more.
From there you can do digital synthesis that results in 10ns jitter at
the output. You have two options to reduce that jitter:
1. Instead of a square wave use an DAC to generate a sine wave and
filter it with a low pass filer.
2. Use an external PLL to remove the jitter.

If I rember correctly Peter Alfke told me that the DCM succeeds to
reduce the jitter down to about 100ps so you could get rid of the
external PLL and instead synthesize a clock that is an integer multiple
of the target clock but is fast enough to be fed into a DCM and than
devide the result down to the target frequency.

Square wave synthesis is done with Bresenhams line drawing algorithm (X
counts with the input frequency and the output square wave is the lowest
bit of Y)
Sine wave synthesis is only marginally more complex but requires more
resources.

Kolja Sulimma

kevin@firebolt.com wrote:
> Please correct me if I'm wrong (probable), but aren't DSS's used just
> to create the numeric representation of a requested wave-shape.  Sorry
> I didn't clarify in my original post, I only need to output a square
> wave (0/1) over the standard FPGA I/O.  As I would still be clocking
> the DSS at 40 MHz, I wouldn't be able to get better
> resolution/granularity for frequencies between 500 to 700 kHz that
> would be able to be multiplied by 16 based on a 40 MHz clock  Is there
> a way to make the DSS asynchronous?  Sorry if I'm missing something
> obvious.
> 
> Kevin
> 

Article: 83311
Subject: Re: MAX II UFM data specification and programming
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Wed, 27 Apr 2005 18:19:03 +0200
Links: << >>  << T >>  << A >>
Bert Cuzeau <_no_spa_m_info_no_underscore_@alse-fr___.com> writes:

> Petter Gustad wrote:
>
>> Is there an easy way to convert a plain ascii file of hex numbers etc.
>> into a SOF format or similar in order to program the UFM of the MAX
>> II?
>> Petter
>>
>
> I think plain hex-ascii to MIF format is so obvious that you
> don't need anything more that a few seconds of your text editor...

Thank you for your reply. I've used MIF files for simulation
previously, but I would like to program the UFM seperately. It seems
like the Quartus II programmer accepts SOF files only. How can I load
the MIF file into the UFM?

Further is there a way I can generate a SVF file to program the UFM?
I would like to program serial numbers etc. into the UFM during
production and testing of some boards containing a MAX II among other
devices. 

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 83312
Subject: x on ml300?
From: Jason Zheng <xin.zheng@jpl.nasa.gov>
Date: Wed, 27 Apr 2005 10:02:08 -0700
Links: << >>  << T >>  << A >>
Hi,

I'm trying to write a graphics demo program on an ML-300 board with 
embedded PowerPC CPU and 128MB of RAM, no graphics acceleration chip. I 
got the linux kernel running, and have been advised that regular X11 
will not run because it takes too much memory and I need to run some 
other memory-extensive tasks on the background.

Does anyone know of a good widget toolkit that can solve my problem? 
Thanks in advance.

-jz

Article: 83313
Subject: Re: MAX II UFM data specification and programming
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 27 Apr 2005 19:19:32 +0200
Links: << >>  << T >>  << A >>
Hi Petter,

my first attempt to look into the problem caused following exception in
quartus :)

Internal Error: Sub-system: PGME, File: pgme_tsunami_algorithm.cpp, Line:
1640
data_ptr != NULL
Quartus II Version 4.2 Build 156 11/29/2004 SJ Web Edition

and Quartus self closed itself silently...
hm...next attempt:

Error: JEDEC STAPL Format Files, Jam STAPL Byte Code 2.0 Files, Serial
Vector Format Files, and In System Configuration Files do not support
EPM1270 device


ok your choices

1) to reverse engineer the JTAG commands to program the UFM and write your
own JAM or SVF and play that using JAM or SVF player
2) fight with Altera to provide some solution
3) if you can live that you need to program the UFM before the main then you
can use simple JTAG-BSCAN indirect approuch
4) if you can allocate some 10 to 12 LE you can add the ability to reprogram
the UFM while the MAX2 is programmed (and possible operation)
5) you can hire me todo [1]
6) you can hire me todo [3] or [4]

http://gforge.openchip.org/frs/shownotes.php?release_id=47

there is simple boilerplate that connect the JTAG BSCAN to the UFM for
read/write - its only an starter boilerplate need to add some flip flops and
muxes to get it useable, but it shows a little how the idea would work

Antti










"Petter Gustad" <newsmailcomp6@gustad.com> schrieb im Newsbeitrag
news:87fyxc6vm0.fsf@filestore.home.gustad.com...
> Bert Cuzeau <_no_spa_m_info_no_underscore_@alse-fr___.com> writes:
>
> > Petter Gustad wrote:
> >
> >> Is there an easy way to convert a plain ascii file of hex numbers etc.
> >> into a SOF format or similar in order to program the UFM of the MAX
> >> II?
> >> Petter
> >>
> >
> > I think plain hex-ascii to MIF format is so obvious that you
> > don't need anything more that a few seconds of your text editor...
>
> Thank you for your reply. I've used MIF files for simulation
> previously, but I would like to program the UFM seperately. It seems
> like the Quartus II programmer accepts SOF files only. How can I load
> the MIF file into the UFM?
>
> Further is there a way I can generate a SVF file to program the UFM?
> I would like to program serial numbers etc. into the UFM during
> production and testing of some boards containing a MAX II among other
> devices.
>
> Petter
> -- 
> A: Because it messes up the order in which people normally read text.
> Q: Why is top-posting such a bad thing?
> A: Top-posting.
> Q: What is the most annoying thing on usenet and in e-mail?




Article: 83314
Subject: obufds attribute problem
From: =?ISO-8859-15?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Wed, 27 Apr 2005 19:24:08 +0200
Links: << >>  << T >>  << A >>
Hi,

I want to feed data from a piso into a obufds. I have my code attached. 
When I try to synthesize it, I get this error:

ERROR:HDLParsers:850 - "D:/Daten/xilinx/led_test/led_test/led_test.vhd" 
Line 183. Formal port IOSTANDARD does not exist in Component 'OBUFDS'.

I have the component declared like this:

component OBUFDS is
port (I : in STD_LOGIC;
O : out STD_LOGIC;
OB : out STD_LOGIC);
end component;

I can not find the error.

Another question: Can I connect a normal net to a obufds? Or should I 
put a buf manually in front of it?

regards,
Benjamin

My code:

-- generates serial data for one lvds-pair
process (lvds_tick)
begin
    if load_lvds= '1' then
       reg <= lvds_channel_1;
    elsif rising_edge(lvds_clk) then
       reg <= reg((7-2) downto 0) & '0';
    end if;
    lvds_1_in <= reg(7 - 1);
end process;

lvds_1_obufds : OBUFDS
generic map (
	IOSTANDARD => "LVDS_25")
port map (
       O => lvds_1_out_p,     -- Diff_p output (connect directly to 
top-level port)
       OB => lvds_1_out_n,   -- Diff_n output (connect directly to 
top-level port)
       I => lvds_1_in      -- Buffer input
);

Article: 83315
Subject: Re: Sync + FIFO
From: "Berty" <wooster.berty@gmail.com>
Date: 27 Apr 2005 10:40:39 -0700
Links: << >>  << T >>  << A >>
Peter,
While I understand your point I'm afraid this is why you see so many
Eng that know just about nothing except copy paste of IP module.
Of course Async FIFO is not as simple as shift register. And of course
it involve some thinking and I would strongly recommend anyone who want
to design such thing or for that matter any new design to have DR of
more experience Eng to see how he did what he did and see how to
improve or fix the wrong.
I'm fully aware of the Empty Full having designed several FIFO of all
type and flavor.
Except for the obvious of the advantage of knowing what you do and
example as for why you should know to design by yourself can be that
Some FIFO depend on the implementation when they have one last entry
will toggle the empty while other will not.
Sometime this toggle can be more useful however if you know Zilch about
how the FIFO was design you can do nothing and have to adapt yourself
to what ever the core give even if this is not the best for the design
you do.
And talking about synconizers and Gray counter etc while to use them
correctly is important this is not rocket science, Sure to give
complete and full explanation of what Metastable is and the effect of
it in clear way and not just using "wave hand" explanation can be
challenging but the actual implementation once you understand the
meaning of it is not so difficult that one have to pass it aside and
use other proven code.
I guess it all boil down to are you an Eng who want to be a copy/paste
one or are you an Eng who want to know how to do thing and yes ONCE you
know use other if they make sense, but even for this to tell if it make
sense you need to understand and not just be another copy/paste-Eng as
more and more I for one encounter.

And all those who might give example on how they saved money, time etc
by using other FIFO and not learning how to do it the right way are
just an example as why you SHOULD learn and not just be copy paste one
and use this as example to why to use other code.

Back to Math using your own logic is equivalent to say to Eng you
should learn how to do 1+1 however to do integral of X^2 from 0 to 2 is
to complex so use calculator, I do hope university will not go with
this logic and those that do well maybe from there we get all the
copy-paste Eng's.

Remember that any minute you "Waste" today for learn how to do it
will pay thousands time in your future, when you have design which are
not simple and there is no IP and you need to draw from your own
experience, which if it involve only/mainly copy-paste without the
knowledge mean you will never become ASIC leader or Architect of new
complex designs and you will stay basic simple Designer, as no
knowledge mean poor  capability.


Article: 83316
Subject: Re: PCI plug n play and Graphics card implementation
From: "DerekSimmons@FrontierNet.net" <DerekSimmons@FrontierNet.net>
Date: 27 Apr 2005 12:01:35 -0700
Links: << >>  << T >>  << A >>
In the next couple of weeks I'm putting the finishing touches on a
triangle rasterization library. My development platform is a Stratix II
EDK/SDK. I'll also be posting it to the NIOS II forum website when
finished. I was wondering if you were interested and if there was any
other interest.

Thanks,
Derek


Article: 83317
Subject: Re: XC4k parts obsolete ?
From: "Antti Lukats" <antti@openchip.org>
Date: Wed, 27 Apr 2005 21:18:48 +0200
Links: << >>  << T >>  << A >>
"Bert Cuzeau" <_no_spa_m_info_no_underscore_@alse-fr___.com> schrieb im
Newsbeitrag news:426f3007$0$20473$626a14ce@news.free.fr...
> austin wrote:
> > http://www.xilinx.com/bvdocs/notifications/pdn2004-21.pdf
> >
> > Is the discontinue notice for somw parts that had extremely low volumes.
>
>
> Thanks Austin.
> The "port" won't be too difficult anyway :-)
>
> Bert
>

BTW, Atmel AT40K are claimed to be pin-compatible to xilinx XC4K,
but if you can redesign to recent lowcost FPGA then thats possible
preferable.

antti



Article: 83318
Subject: Re: obufds attribute problem
From: =?ISO-8859-15?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Wed, 27 Apr 2005 21:42:52 +0200
Links: << >>  << T >>  << A >>
Hi,

I found an answer to my question about the attribute here: 
http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=12506

regards,
Benjamin

Article: 83319
Subject: Re: what is microblaze ?
From: manmeetbhangu@gmail.com (mb)
Date: 27 Apr 2005 12:45:00 -0700
Links: << >>  << T >>  << A >>
Hi thanks a lot guys :))

i think ur response was indeed helpful :)

cheers

Article: 83320
Subject: Re: x on ml300?
From: Peter Ryser <peter.ryser@xilinx.com>
Date: Wed, 27 Apr 2005 13:16:29 -0700
Links: << >>  << T >>  << A >>
The Linux demo shipping with the ML300 runs X11 just fine.

- Peter


Jason Zheng wrote:
> Hi,
> 
> I'm trying to write a graphics demo program on an ML-300 board with 
> embedded PowerPC CPU and 128MB of RAM, no graphics acceleration chip. I 
> got the linux kernel running, and have been advised that regular X11 
> will not run because it takes too much memory and I need to run some 
> other memory-extensive tasks on the background.
> 
> Does anyone know of a good widget toolkit that can solve my problem? 
> Thanks in advance.
> 
> -jz


Article: 83321
Subject: RocketIO decoupling
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Wed, 27 Apr 2005 20:17:22 GMT
Links: << >>  << T >>  << A >>
The RIO User Guide (UG024) stipulates that the RIO supply pins need to be 
filtered using a Ferrite bead and a capacitor. It's very specific about the 
bead being either of 2 Murata parts and the capacitor being a 0.22uF 0603 
device.

The ML300 board however doesn't adhere to the capacitor recommendations and 
uses a larger device. How important is it to stick rigidly to the User's 
Guide, does anyone have any relevant information on this?

I'm having problems finding a supplier of the ferrite beads. Similar 
question: is it really so important that I use either of the 2 parts stated 
in the UG?

TIA.

Rog. 



Article: 83322
Subject: Re: MAX II UFM data specification and programming
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Wed, 27 Apr 2005 22:21:44 +0200
Links: << >>  << T >>  << A >>
"Antti Lukats" <antti@openchip.org> writes:

> Hi Petter,
>
> my first attempt to look into the problem caused following exception in
> quartus :)
>
> Internal Error: Sub-system: PGME, File: pgme_tsunami_algorithm.cpp, Line:
> 1640
> data_ptr != NULL
> Quartus II Version 4.2 Build 156 11/29/2004 SJ Web Edition

Urg!

You can generate SVF in 4.2SP1:

Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Full Version

I have
set_global_assignment -name GENERATE_SVF_FILE ON
set_global_assignment -name GENERATE_JAM_FILE ON

in my Tcl script. But I would like to generate SVF files for the UFM
part only. I don't want to run full synthesis, place and route, etc
for each production device.

> 1) to reverse engineer the JTAG commands to program the UFM and
> write your own JAM or SVF and play that using JAM or SVF player

My plan was to write some code to merge in my own data in order to
program the UFM from serial numbers read from a barcode reader.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 83323
Subject: Re: x on ml300?
From: larwe@larwe.com
Date: 27 Apr 2005 13:41:28 -0700
Links: << >>  << T >>  << A >>

> I'm trying to write a graphics demo program on an ML-300 board with
> embedded PowerPC CPU and 128MB of RAM, no graphics acceleration chip.
I
> got the linux kernel running, and have been advised that regular X11
> will not run because it takes too much memory and I need to run some
> other memory-extensive tasks on the background.

Crazy talk. X11 runs fine in 128Mb of RAM on PowerPC. I'm building a
demo embedded application around a PPC-Linux box (603e) with 64Mb of
RAM (external video RAM), running X11.

Do you have a swap partition on something as well?


Article: 83324
Subject: Re: x on ml300?
From: Jason Zheng <xin.zheng@jpl.nasa.gov>
Date: Wed, 27 Apr 2005 14:00:05 -0700
Links: << >>  << T >>  << A >>
larwe@larwe.com wrote:
>>I'm trying to write a graphics demo program on an ML-300 board with
>>embedded PowerPC CPU and 128MB of RAM, no graphics acceleration chip.
> 
> I
> 
>>got the linux kernel running, and have been advised that regular X11
>>will not run because it takes too much memory and I need to run some
>>other memory-extensive tasks on the background.
> 
> 
> Crazy talk. X11 runs fine in 128Mb of RAM on PowerPC. I'm building a
> demo embedded application around a PPC-Linux box (603e) with 64Mb of
> RAM (external video RAM), running X11.
> 
> Do you have a swap partition on something as well?
> 

 >>and I need to run some
 >>other memory-extensive tasks on the background.

and swap is very limited.

-jz



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search