Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Problem solved! > But this doesn't solve my issue concerning the Phase of the DCM. If I > change the phase, nothing changes in the setup-time. Only the > "datasheet"-section in the timingreport reflects the phasechange > correct. As the friendly guy from the websupport told me, the OFFSET-IN- Constraint does not reflect the phase of the DCM, if you use the keyword "HIGH" or "LOW". Example: Connection like mentioned before, adc_DCLK_P goes into the DCM, is renamed to CLK and clocks the FFs, where ADC_DATEN is registered. First the grouping-constraint: NET "adc_DATA_P<*>" TNM = "ADC_DATEN"; Then the OFFSET-IN: TIMEGRP "ADC_DATEN" OFFSET = IN 0.97 ns BEFORE "adc_DCLK_P" HIGH; This does not reflect any phase changes you made in the DCM. Instead use: TIMEGRP "ADC_DATEN" OFFSET = IN 0.97 ns BEFORE "adc_DCLK_P"; -- don't use the HIGH-Keyword. It's so simple :( regards, ChristianArticle: 115251
reciver may or may not update credits for malformed packet. Anyways error messsege will be sent so reciver buffer problem will be taken care of by transmitter .On Feb 2, 10:13 pm, "Colin Hankins" <Colin.Hank...@touit.com> wrote: > If the receiver can not determine which FC information to update then it > must not update the FC information. Otherwise updating of the FC information > is optional when a receiver receives a malformed TLP. So depending on what > the receiving device does, or how malformed the packet is, your scenario > could certainly play out. > > But the receiving device will send an ERR_FATAL message to the root complex > > Colin > > "Fred" <f...@n0spam.com> wrote in message > > news:1170332691.17553.0@iris.uk.clara.net... > > >I know there is a PCI-Express newsgroup but there are very few posts of any > >relevance to PCI Express itself. > > > Is there another newsgroup more dedicated to the workings of PCI Express? > > > I have the following question: What happens when a mal formed packet is > > received? The transmitter CC will be incremented but the CL (which is the > > CA received from the receiver) will not be incremented such that the > > apparent size of the available space in the receive buffer will decrease > > with no mechanism to correct itself. Am I correct?Article: 115252
The V4 can generate clk_90 and clk_270 from the DCM in high speed mode. Your FAE was wrong - only previous generation devices had this limitation. To see this is simulation use the DCM_BASE or DCM_ADV primitive instead of DCM. On Jan 16, 4:31 am, "skyworld" <chenyong20...@gmail.com> wrote: > Hi, > I need to generate four clocks with DCM in VIRTEX4. The frequency is > 312MHz. I can't get any output from clk_90 and clk_270. I contacted > Xilinx's FAE and they told me there is no output from 90/270 phase > shift when DCM works at high speed mode. Does anybody know how to > generate these four clocks with equal phase shift in VIRTEX 4? thanks > very much.Article: 115253
On 30 Jan 2007, you wrote in comp.arch.fpga:
> Sebastian Schüppel wrote:
>
>> I have a source code which is compiled by the Design Compiler from
>> Synopsys. I also mapped my technology library to that, so it will
>> generate a VHDL netlist.
>>
>> My problem is that there are Components declarations and
>> instantiations in the netlist with no architecture.
>
> Can you give one or two examples of such components? It may be that
> these are Altera primitives which are known to the Quartus software.
>
> Best regards,
>
>
> Ben
>
I solved one of my problems. Because I'm new to this whole topic I did't
know that I have to use a .lmf file. So now I almost mapped all of the
components like ABTL ... and so on. But still there is on which I do not
get mapped. It's a component called DFFS. I don't know why this one doesn't
get mapped. Because in the .lmf file it says
FUNCTION "DFFS" ("D","CLK","VDD" ,"VDD")
RETURNS ("Q")
END
BEGIN
FUNCTION dffe (D,CLK,CLRN,PRN,ENA)
RETURNS (Q)
so it should work.
because the used component has the following port map structure
D: IN std_logic;
CLK: IN std_logic;
Q: OUT std_logic;
I could create a D Flip-Flop by my one with the help of Quartus
Megafunction to make it work, but thats not the way it should go.
Could you please help me?
Sebastian
Article: 115254Hi I'm starting to use the gnu mb-gcc compiler but I get this error message: mb-gcc test1.c /cygdrive/d/xilinx/gnu/microblaze/nt/bin/../lib/gcc/microblaze/ 3.4.1/../../../../microblaze/bin/ld: can't open input file: /cygdrive/ d/xilinx/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../ microblaze/bin/ld collect2: ld returned 1 exit status I don't know why this problem appears. The file ld is in such directory. May be some issues with cygwin? Thanks ManuelArticle: 115255
>It would be interesting to hear how many people that would be >interested in this? >Count me in! I'm just a newbie but it would be great to see what >others could do! >Another very interesing subject would be FPGA-MAME! Somebody had the >same thoughs? Already there are versions with PacMan, Space Invaders, >Donkey Kong, Pengo and others. just think of the possiblities with >Partial Reconfiguration of that was more every-mans business. Today >it seem very resource-expensive and hard to do. But maybe the recent >updates in ISE 9.1 with Partitions could be used to make Partial >Reconfiguration more "open". >Or maybe a FPGA-MESS would be even more interesing! Well what do >think? There are already lot's of projects in this area. It's been thought of :) I know there's specific projects for Atari-ST, Amiga, C64, Amstrad etc.. (thoe Amiga is proberbly the more challenging one) Search for C-one etc.Article: 115256
Hi
I am trying to compile a file with custom initialization routines. Mainly
to write my own assembler interrupt routines. I am using ISE/EDK 8.2 and
the compiler that comes with the edk.
I followed the description as pointed out in:
http://www.xilinx.com/ise/embedded/edk82i_docs/est_rm.pdf (pages 128,129).
I copied cpu_init.S, boot.S and xil-crt0.s and modified the latter as
described in the URL above. Currently i am using no interrupts and have
no interrupt vector table. Finally i am linking my small c programm which
does nothing but blinking some leds with the following makefile:
CC=powerpc-eabi-gcc
simple.elf: simple.o boot.o xil-crt0.o cpu_init.o
$(CC) -o simple.elf -nostartfiles xil-crt0.o simple.o cpu_init.o -Wl,-defsym -Wl,_START_ADDR=0xffff0000
boot seems to be linked although -nostartfiles is given. objdump of the
elf file looks good to me.
Thanks for your suggestions
ST
Article: 115257On Feb 5, 11:10 am, pbF...@ludd.invalid wrote: > >It would be interesting to hear how many people that would be > >interested in this? > >Count me in! I'm just a newbie but it would be great to see what > >others could do! > >Another very interesing subject would be FPGA-MAME! Somebody had the > >same thoughs? Already there are versions with PacMan, Space Invaders, > >Donkey Kong, Pengo and others. just think of the possiblities with > >Partial Reconfiguration of that was more every-mans business. Today > >it seem very resource-expensive and hard to do. But maybe the recent > >updates in ISE 9.1 with Partitions could be used to make Partial > >Reconfiguration more "open". > >Or maybe a FPGA-MESS would be even more interesing! Well what do > >think? > > There are already lot's of projects in this area. It's been thought of :) > I know there's specific projects for Atari-ST, Amiga, C64, Amstrad etc.. > (thoe Amiga is proberbly the more challenging one) > > Search for C-one etc. Yep, thanks for the tip but I've already read and had some talks with both the SUSKA-implementor, the Minimig implementor, read about the nice C64DTV-project and underlying C-one with its Amstrad and others- implementation. I talked some with the original implementor of the new C64-core for C-one before he teamed up with (or jumped over too) C- one. There are also a great Apple2-project guy who I had alot of disscussion with and who's project works great. A TRS-80 project what works great, the great System09 There are complete ZX Spectrum's out there ready for donwload into your nearest FPGA-card. These projects are for complete and static platforms. So with lots of the above project's source code available there are a goldmine for the persons whom have the time to pursue a future multi- platform-project. The above persons work is of course a well needed starting-point!Article: 115258
Someone wrote:
"[..]
And for some reason my output seems to be stuck somewhere..it hangs
and i have to manually kill the terminal by force closing it.
Heres the description of the problem:
[..]
[..] When I build the file and then run
the executable, the whole terminal hangs and shows nothing ...
Heres the code:
[.. Over two hundred lines of C++ edited. That is a lot of code to
bother reading if we have not even narrowed down the possible
problems, which might not even be in your C++ code.]
int sc_main(int argc, char **argv)
{
srand(time(NULL));
// create instances of sensor generator modules for each
direction
Generator gen_NS("Generator_NS");
Generator gen_SN("Generator_SN");
Generator gen_WE("Generator_WE");
Generator gen_EW("Generator_EW");
// create intances of controller modules
Controller c_NS("Controller_NS"); //name and pointer to
sensor_values
Controller c_SN("Controller_SN");
Controller c_WE("Controller_WE");
Controller c_EW("Controller_EW");
main_controller M("main_controller");
// create channels between the controller instances and main
controller
sc_signal<bool> NS_main;
sc_signal<bool> SN_main;
sc_signal<bool> WE_main;
sc_signal<bool> EW_main;
sc_signal<bool> main_NS;
sc_signal<bool> main_SN;
sc_signal<bool> main_EW;
sc_signal<bool> main_WE;
// create channels between the sensor generator modules and the
corresponding controllers
sc_signal<bool> sen_NS;
sc_signal<bool> sen_SN;
sc_signal<bool> sen_WE;
sc_signal<bool> sen_EW;
// connect channels to ports of the modules instances
gen_NS(sen_NS);
gen_SN(sen_SN);
gen_WE(sen_WE);
gen_EW(sen_EW);
c_NS(sen_NS, main_NS, NS_main);
c_SN(sen_SN, main_SN, SN_main);
c_WE(sen_WE, main_WE, WE_main);
c_EW(sen_EW, main_EW, EW_main);
M(NS_main,WE_main,SN_main,EW_main,main_NS,main_WE,main_SN,main_EW);
// start simulation
sc_start(50, SC_SEC); //simulation time?
return 0;
}
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------
Heres the make file which i use:
[..]
OPT = -O3
DEBUGFLAG = #-g
#OTHER = -Wall
[..]
OTHER = -Wno-deprecated
[..]
# List all directories from where you include .h-files
INCDIR= -I. -I.. -I$(SYSTEMC)/include
[..]
## Variable that points to SystemC installation path
## version 2.1
SYSTEMC = /usr/include
[..]
Would be glad if anyone would point out something in the system which
will atleast make it run..[..] or maybe theres a problem with the make file
i dont really know.
I used the same make file which is used in our school lab where we
work with sun ray machines and modified it to reflect the x86 machine
im working with.
May be i didnt do it correctly in the make file.
Any help wud be sincerely appreciated."
You have written code which calls many functions and constructors but
you do not know whether main() or sc_main() or any other part of the
program is ever reached. I suggest a debugging technique which may or
may not help you in your current situation but which is occassionally
very useful with almost any language: add debugging print statements
in your code to trace the control flow. I would start by e.g. adding
std::cerr << "\nReached debugging print statement1\n";
between the opening { of sc_main() and the call to srand(). If that is
not printed, then you can deduce that you have a problem before
sc_main(). If the print statement is executed, you can try adding
another: e.g. half way or 25% through sc_main() you could add
std::cerr << "\nReached debugging print statement2\n";
and if that is printed, add another statement later in sc_main(),
otherwise another print statement earlier in sc_main(), eventually
working liking this you could reduce the amount of lines to inspect.
However, I shall also make some remarks on your makefile. You use
SYSTEMC before the quoted assignment "SYSTEMC = /usr/include" but
maybe you also set it during invocation of make on the command line.
For debugging a program compiled by G++, it would be better to have
OPT = -O0 #Hyphen then upper case letter Oh then numeral zero.
DEBUGFLAG = -g
Also, -Wall should not be disabled (though it does not actually
activate all warnings).
None of this advice has been SystemC(R)-specific so far, but
you should try it. If you still can not even get one print statement
to work, start a new SystemC(R) C++ program and write only the
following C++ code:
#include<iostream>
#include"systemc"
int sc_main(int argc, char **argv)
{
std::cerr << "\nThis program checks whether I can even access the\
SystemC(R) installation because if I can not, a more advanced\
program such as a SystemC(R) traffic light simulation is also not\
going to work.\n";
return 0;
}
If this does not work, perhaps you should try a different type of
makefile or do it all on the command line. Unfortunately at least one
of the examples from SystemC.org does not work, but maybe you will
find one which is suitable for you.
After you make some more progress, if you still have difficulties, you
could ask for help on news:comp.arch.fpga again or you might try the
email list
HTTPS://WWW.SystemC.org/mailman/listinfo/systemc-forum
or the HTTP-based help forum hosted on SystemC.org .
Good luck,
Colin Paul Gloster
Article: 115259No major differences here between, ISE 8.2i and 9.1i Well got ChipScopPro 9.1 runnig on my Win2k3 Server. Which was not possible with ISE 8.2i Bye Helmut On 2 Feb., 15:50, "Francesco" <francesco_poder...@yahoo.com> wrote: > Hi, I'm just wondering how many people here are using ISE 9.1. > Could you post your experience here? > Antii what do you think? > Is really 6 time faster? > > I tryed unsuccesfully to use ISE 9.1 SP1...unfortunately in my case > the tool crashed with the message error: "Runtime error" > I tryed a few time unsuccesfully.... Now I'm back on ISE 8.2 > > Thanks eveybody, > Francesco > > PS: please post here even if you are using Webpack 9.1Article: 115260
hi,
i tried to implement or1K processor on spartan 400K chip, but it
sysnthesizes to 4834 slices, but the chip has only 3584 slices. hrere
is the full sysnthesis report for the main processor core.
Number of Slices: 4834 out of 3584 134% (*)
Number of Slice Flip Flops: 3104 out of 7168 43%
Number of 4 input LUTs: 17219 out of 7168 240% (*)
Number used as logic: 9027
Number used as RAMs: 8192
Number of bonded IOBs: 369 out of 173 213% (*)
IOB Flip Flops: 71
Number of MULT18X18s: 4 out of 16 25%
Number of GCLKs: 3 out of 8 37%
are these figures correct? i though a spartan3 could handle this
processor without much of a problem. in addition to the processor, i
got some image processing units as well to put in to it.
how does or1k compares with microblace footprint, as i've seen many
tutorials of implementation of microblaze on spartan 3.
are there any other free processor cores available which would fit in
to spartan 3, 400K version with GNU toolchain support?
any responce is much appreciated.
Thank you
Article: 115261
On 2007-02-05, CMOS <manusha@millenniumit.com> wrote:
> hi,
> i tried to implement or1K processor on spartan 400K chip, but it
> sysnthesizes to 4834 slices, but the chip has only 3584 slices. hrere
> is the full sysnthesis report for the main processor core.
>
> Number of Slices: 4834 out of 3584 134% (*)
> Number of Slice Flip Flops: 3104 out of 7168 43%
> Number of 4 input LUTs: 17219 out of 7168 240% (*)
> Number used as logic: 9027
> Number used as RAMs: 8192
^^^^^^^^^^
> Number of bonded IOBs: 369 out of 173 213% (*)
> IOB Flip Flops: 71
> Number of MULT18X18s: 4 out of 16 25%
> Number of GCLKs: 3 out of 8 37%
You are truly using an obscene amount of LUTs as RAM in this design if
I my say so. My guess is that you are implementing the caches in
distram instead of blockrams. As a comparison, here is a breakdown of
an OR1200 design that we are using:
+-----------------------------+--------+--------+--------+-----------+--------+--------+
| Module | LUTS | FF | RAMB16 | MULT18x18 | IOB | DCM |
+-----------------------------+--------+--------+--------+-----------+--------+--------+
| cpu | 1 | | | | | |
| cpu/dwb_biu | 12 | 72 | | | | |
| cpu/iwb_biu | 66 | 74 | | | | |
| cpu/or1200_cpu | 3824 | 837 | 2 | 4 | | |
| cpu/or1200_dc_top | 235 | 40 | 5 | | | |
| cpu/or1200_ic_top | 186 | 38 | 5 | | | |
| cpu/or1200_immu_top | 11 | 33 | | | | |
| cpu/or1200_pic | 27 | 38 | | | | |
| cpu/or1200_sb | 309 | 352 | | | | |
| cpu/or1200_tt | 170 | 96 | | | | |
... lots of other modules not part of the or1200 ...
+-----------------------------+--------+--------+--------+-----------+--------+--------+
| Total | 9499 | 4402 | 28 | 4 | 115 | 2 |
+-----------------------------+--------+--------+--------+-----------+--------+--------+
This is targetted at a Virtex 2-4000 but the LUT/FF count should be
similar when targetted to another FPGA with 4 input LUTs and
blockrams. For the curious, the opencores ethernet controller is
responsible for most of the rest of the LUT/FF usage.
/Andreas
Article: 115262I was trying to installing Xilinx ISE 9.1i full version on RHEL 4 AS 64-bit and I got following errors: error while loading shared libraries: libstdc++.so.5: cannot open shared object file: No such file or directory The Xilinx Webpage says RHEL 4 WS 64-bit is supported. Does this mean only WS not AS is supported? Any one succeed on installing 9.1i on AS/ES ? ThanksArticle: 115263
On 2007-02-05, Andreas Ehliar <ehliar@lysator.liu.se> wrote: > On 2007-02-05, CMOS <manusha@millenniumit.com> wrote: >> hi, >> i tried to implement or1K processor on spartan 400K chip, but it >> sysnthesizes to 4834 slices, but the chip has only 3584 slices. hrere >> is the full sysnthesis report for the main processor core. >> >> Number of Slices: 4834 out of 3584 134% (*) >> Number of Slice Flip Flops: 3104 out of 7168 43% >> Number of 4 input LUTs: 17219 out of 7168 240% (*) >> Number used as logic: 9027 >> Number used as RAMs: 8192 > ^^^^^^^^^^ >> Number of bonded IOBs: 369 out of 173 213% (*) >> IOB Flip Flops: 71 >> Number of MULT18X18s: 4 out of 16 25% >> Number of GCLKs: 3 out of 8 37% > > You are truly using an obscene amount of LUTs as RAM in this design if > I my say so. My guess is that you are implementing the caches in > distram instead of blockrams. As a comparison, here is a breakdown of > an OR1200 design that we are using: I just realized that this answer might not have been extremely helpful. Take a look at the or1200_defines.v file if you haven't already done so. Specifically, search for XILINX and you should be able to configure the memory type you are using. /AndreasArticle: 115264
Thanks to everybody.... So seems that I'm not the only person having some sort of problem. I'm not the only person that has switched back to 8.x Thanks everibody.... ane please continue to write your comment here... We may help sombodyelse ! FrancescoArticle: 115265
"Andreas Ehliar" <ehliar@lysator.liu.se> wrote in message > > I just realized that this answer might not have been extremely helpful. > Take a look at the or1200_defines.v file if you haven't already done so. > Specifically, search for XILINX and you should be able to configure > the memory type you are using. > > /Andreas I thought it explained things pretty well. The synthesis tools normally do a good job of inferring BlockRAM. However, if you code so that, for example, there's an asynchronous read, the tool has no choice but to use distram. HTH, Syms.Article: 115266
Hi, what is the best way of moving data from a faster clock domain (100 mhz ) to slower one(75 Mhz)? thanksArticle: 115267
Hi Thanks for listening, i found the error. I had checked all memory regions... and they where located in brams but alas i haven't checked if the data segments where lying in the data brams. So everything works right now. S.T.Article: 115268
On 5 Feb., 15:25, "CMOS" <manu...@millenniumit.com> wrote: CMOS, Hi, > are there any other free processor cores available which would fit in > to spartan 3, 400K version with GNU toolchain support? I'm currently fooling with LatticeMico32 [1] on the Spartan3E Starter Kit (Spartan3E-500, ~10 kLUTs). LM32 takes < 1500 LUTs, is under GPL and there is a GCC port. Even though I don't have much experience with that CPU, it looks quite good. Before that I used LEON3 [2] -- It takes ~5000 LUTs on that chip (without caches), reaches only 50MHz but is fully SPARC v8 compatible. j. [1] http://www.latticesemi.com/products/intellectualproperty/ipcores/ mico32/index.cfm [2] http://www.gaisler.com/Article: 115269
There are two issues: How do you throttle the faster data stream, so that it does not overwhelm the slower receiver? How do you interface between two inherently asynchronous clock domains? A FIFO is a popular device, but it may be an overkill, depending on your answer to my first question. Peter Alfke, Xilinx On Feb 5, 8:39 am, "vlsi_learner" <baj...@gmail.com> wrote: > Hi, > > what is the best way of moving data from a faster clock domain (100 > mhz ) to slower one(75 Mhz)? > > thanksArticle: 115270
I checked with the Xilinx Applications group, and here is their answer: "The free memory interface designs developed by the Xilinx memory applications team have one primary goal: to prove that the FPGA device can interface with given external memory devices at the specified performance, using the IO standard specified by the memory vendor (JEDEC). We therefore focus on the physical layer that comprises the read data capture logic, and the write data transmit logic. The memory controller that we provide with the interface design is very basic, handling memory initialization, auto refresh commands, and other user requested commands like reads and writes. Such a basic controller can be efficient (high data throughput) for streaming video applications with consecutive reads and writes to the same row and bank. But such a controller is very inefficient in applications requiring random accesses to different rows and banks. Therefore, in the Virtex-5 DDR/DDR2 SDRAM memory controller, we now provide multiple-bank support to increase the efficiency of data throughput. Multiple-bank support may still not be the solution for certain applications, and our customers usually replace just the Xilinx-provided controller with one that they designed to specifically handle their system's traffic pattern. With our free Virtex-5 applications the memory interface designs are modular and provide a clean partition between the optimized physical layer and the controller, making it easy to replace the controller while retaining the physical layer design." Hope this explanation helps. Peter Alfke, Xilinx On Feb 1, 5:55 pm, Ray Andraka <r...@andraka.com> wrote: > I think what Nico was trying to say is you get what you pay for. In my > experience, the free DDR designs are generally not worth much. Either > they only support basic operation, or they won't work at full speed, or > they are so littered with bugs that you are better off starting from > scratch. Yes, there are "free" cores out there, but you'll likely put > as much effort into getting them to work in your design as you would > starting with a clean sheet.Article: 115271
Francesco wrote: > Hi, I'm just wondering how many people here are using ISE 9.1. > Could you post your experience here? > Antii what do you think? > Is really 6 time faster? > > I tryed unsuccesfully to use ISE 9.1 SP1...unfortunately in my case > the tool crashed with the message error: "Runtime error" > I tryed a few time unsuccesfully.... Now I'm back on ISE 8.2 > > > Thanks eveybody, > Francesco > > PS: please post here even if you are using Webpack 9.1 > for now i tried a V4SX55 and a 3S500E design and see some improvements on synthesis and par (both work quite well with the smartguide) ... still see those warnings about corrupt files and sometimes i have to close and re-open ISE because for some strange reason the editor stops accepting any input and by restarting it, i get back some response? it also seems impossible to add xco files that are in the working directory to the GUI, from the moment they are in a sub-directory or other directory you can add them? the GUI seems a bit more stable and responsive...Article: 115272
yttrium wrote: > it also seems impossible to add xco files that are in the working > directory to the GUI, from the moment they are in a sub-directory or > other directory you can add them? I keep all the verilog source and xco files in the same Verilog subdirectory. In all previous versions, I could choose 'Add Source", then select all the files in the Verilog subdirectory. In 9.1i, the xco files can only be added using 'Add Copy of Source'. Apparently 'Add Source' is no longer good enough for xcos. --- Joe SamsonArticle: 115273
On Jan 30, 8:04 am, "Sebastian Sch=FCppel" <sch...@hrz.tu-chemnitz.de> wrote: > I have a source code which is compiled by the Design Compiler from > Synopsys. I also mapped my technology library to that, so it will generate > a VHDL netlist. > > My problem is that there are Components declarations and instantiations in > the netlist with no architecture. > > And I'd like to use this netlist as a component of my design in Altera's > Quartus software. > > Can someone tell me how I get this fixed. > > Thanks Is there some reason you don't want to synthesize the original source code in quartus, instead of importing the netlist? Quartus will undoubtedly do a better job of synthesizing to the altera fpga architecture than design compiler will. AndyArticle: 115274
If speed isn't an issue (i.e. one/non-frequent transfers), you need to do two things: 1) synchronize you clock from one domain to the other (there are well- known techniques for this) 2) you can borrow a 2/4-phase protocol from the asynchronous world and implement it in each clock domain. As evindent, this is substantially slower than the async FIFO option. However, depending on the application, it might be more convenient e.g. non-streaming applications. Cheers, -Manny
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z