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Weng Tianxiang wrote: > On Jan 29, 2:10 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > wrote: > > On 28 Jan 2007 15:39:20 -0800, "Weng Tianxiang" > > > > <wtx...@gmail.com> wrote: > > >I want a global error signal to indicate the situation and I am not > > >interested in complex design and all FIFO will be called using one > > >simple module. > > > > >The global error signal applies not only to FIFOs, but also to any > > >module if there is an error situation happening and it will indicate: > > >Hi, it is error here in this clock !!! Using this signal will greatly > > >reduce error debugging time also.Weng, > > > > If this is for simulation only, then you can use global signals. > > > > We have, in the past, suggested using an array of global > > signals, one for each instance that you are debugging. You can > > then attach a generic to each instance, and use it to determine > > which signal is driven by that instance: > > > > package DEBUG_SUPPORT is > > signal s: std_logic_vector(1 to 100); > > end package DEBUG_SUPPORT; > > > > use work.DEBUG_SUPPORT; > > entity DEBUG_ME is > > generic (DEBUG_ID: natural := 0); > > port (....); > > end; > > architecture TRACEABLE of DEBUG_ME is > > -- Internal signal that reflects the error condition > > signal HIGH_WHEN_ERROR: std_logic; > > begin > > ... > > ... all your other stuff > > ... > > DEBUG_TRACING: if DEBUG_ID > 0 generate > > DEBUG_SUPPORT.s(DEBUG_ID) <= > > '1' when HIGH_WHEN_ERROR = '1' > > else '0'; > > end generate; > > end; > > > > However, that's a little messy because you must now use a > > complicated hierarchical configuration to assign the right > > generic value to each instance. An alternative possibility > > is to use a resolved signal for just one global debug signal. > > I don't have time to sketch that out now, but if the generics > > method doesn't work for you, reply to this and I'll try to post > > an example in the next day or two. > > -- > > Jonathan Bromley, Consultant > > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > Hi Jonathan, > Thank you for your help. > > I have used one of your post on how to generate random number such > that I know your name very well. > > Actually I would like to suggest to add a VHDL language element to > resolve the similar problem: how to set or reset a global signal > without consideration of their assertion or deassertion time. > > Why VHDL requires that programmers be allowed to assert or deassert a > signal only in one process is to keep their clock relationships > without ambiguity: on which conditions it must first be asserted or > deasserted and on what other conditions it must be deasserted or > asserted and so on. > > But in reality, there are times, for example, in global error > reporting mechanism, the timing to assert or deassert don't matters. > It will be very convenient for VHDL to have a global signal type a > signal of which can be asserted or deasserted in any processes many > times and without consideration of their timing relations. > > There are two global types of signals: assert first and deassert 2nd. > > If above mechanism exists, my design problem can be easily resolved: > 1. In a package, declare a signal of that type(global type with > assertion first and deassertion 2nd); > 2. In any process, code can be written to assert the signal or > deassert the signal with adding of package; > 3. Compiler is responsible to collect all assert conditions and all > deassertion conditions, then generate equations that first assert the > signal and then deasser the signal. The final equation is as follows: > if(all assertion conditions are ORed here) then > the-first-assert-2nd-deassert-global-signal <= '1'; > elsif(all deassertion conditions are ORed here) then > the-first-assert-2nd-deassert-global-signal <= '0'; > end if; > > This type of definitions will not add any harms to VHDL, but simplify > programming in some situations dramatically. > > I don't know if the similar definition exists in current VHDL. > > Thank you. > > Weng Hi, The thing which you are talking about is already there in the language since its inception. The signals in the larger scope can be assigned in multiple processes, you just have to use the appropriate library which has the resolved signal types. Thanks neoArticle: 115051
hi how to perform a boundary scan test after the FPGA is configured or in other words how do i know that the FPGA is configured properly Thanks and Regards Lokesh BODDUArticle: 115052
billu wrote: > Any ideas/pointers on how i can get started on a setup like this. So, > the USB 2.0 on the XUPV2P might not be able to support 480Mbps. What > USB chipset can I use to get the maximum transfer rate, and how would > I interface the chipset w/ the PC/FPGA? Try looking up the USRP. That uses a Cypress chip connected to a Cyclone II and appears to work reasonably well, although there are plenty of caveats with USB :( -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 115053
Hi Dear All, I have one ML403 board with ppc405 core,and I want to port LinuxPPC on it. are there anybody tell me, where can I get the linuxppc for ML403? are there some patchs for ML403? thanks in advance, RickyArticle: 115054
To declare and initialise a one-bit register in verilog we use the following statement reg one_bit_reg=1'b0; Similarly, to declare and initialise a one dimension reg (e.g. 8-bit) we can write reg [7:0] reg_len_8=8'd0; We can declare a two dimensional array (e.g. 16x8-bit) as reg [7:0] reg_dim_2 [15:0]; But how can we initialise this array in the same statement? or How do we declare the initial state (known non-zero values) of an array without using extra logic (especially when implementing on hardware (FPGAs))?Article: 115055
Hi all, I wonder what is curently state-of-the art in serial high-speed transmission and what are the prevailing data rates? I know about some SerDes in the gigabit-per-second range but I cannot imagine if 10 Gbps are really a challenge or the applied method or if it's 1 Gbps (or something in between)...? I recently heard about some 60 GHz in the mobile communication sector and 10 Gbit Ethernet but as far as I know there are those multi-level modulation methods (like QAM for example) that are able to provide 10 Gbit bandwidth with a bitrate of some Mbps (is that correct?). I'm not interested so much in those higher modulation methods (nor in optical transmission) but in the baseband communication where bitrate = clockrate, i.e. the line rate. What can be efficiently transmitted today electrically (over wire or PCB)? What is the prevailing technology of those circuits, is it CMOS or are there alternatives? I am a senior electrical engineer and unfortunately did not manage to keep up-to-date. After googling all night I'm really depressed because I finally couldn't find an unambiguous answer. Maybe some guys in the silicon-business or practitioners know the anser and are willing to share there knoledge with me? Best regards GeronimoArticle: 115056
"dan" <daniel.blake2@baesystems.com> writes: > Hi, I'm new to using the EDK and need some help. > > I'm working on a microblaze system which has become to big for the > BRAM, and having done some research i realise i need a bootloader. > > What i have made out from the scraps of information i've read is: > > 1) Create a new software project which is the bootloader, this simply > points to the external memory and says to the system, run this code. > 2) program the FPGA as normal, with the bootloader program. > 3) load data onto the external memory. > 4) It should work. > > So my first question is, have i understood the principles correctly? > > Moving on from here i've been struggling to find any detailed > tutorials/explinations about how to actually do this. > Could someone either explain to me or point to a good tutorial? > > One more point, when i program my FPGA, i don't directly program the > FPGA, i program a device which then with every boot of the development > board programs the FPGA. I have a feeling this will affect the steps > above(if they are correct in the first place) because i don't want to > be manually loading data onto the external memories every time i start > the thing running. My availible external memories are a DDR and a > flash. > It sounds like you have most of this understood. Your bootloader will live "inside" the FPGA bitstream and setup the BRAM that the microblaze will boot from. This bitstream will (probably) live in a configuration flash, or in your program flash in a different sector to the proper software. What configuration strategy are you using? Which FPGA? You'll then have to get your "proper" program into flash in some way and then the boot code can either jump straight to execute from flash (if you're lucky that'll execute quick enough for your application) or copy it into DDR at boot time and then execute from DDR. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 115057
"billu" <bkamakot@gmail.com> wrote in message news:1170134071.732630.323580@v45g2000cwv.googlegroups.com... > Thx for everyones replies. The reason we are looking into FPGA based > solutions is b/c we would preferably like a SMA output (since our > modules have a SMA interface). The Cypress EZUSB2 output interface is > convenient (not fast enough), but its not compatible with our RF > module. The EZUSB FX2 Slave fifo interface is (i.e. can be configured as) 16 bit @ 48MHz, which is faster than USB2. The FX2 won't be a bottleneck on a USB2 system, though you're likely to need the FPGA anyway to do your format conversion. As other people have said, it will be the PC which is more likely to limit you, though that's not as much of a problem as it used to be when USB first came out. WillArticle: 115058
On 30 Gen, 00:39, John Williams <jwilli...@itee.uq.edu.au> wrote: > > Do you know what kind of problem is this?If you post the error output from the compiler I might be able to help. > Ok, as soon as it possible, I'll post it. > I suggest you purchase one of the S3E-50 or -160 starter kits to get a > platform that will happily run embedded Linux on the MicroBlaze. These > boards have plenty of memory and were more or less designed with > MicroBlaze/Linux in mind. S3 Starter board isn't mine, I'm using it in University Lab. But we have also XUPV2P, that run very well uclinux, but my work it's to port uclinux on S3... Do you think is it possible? > Also, I suggest you subscribe to the microblaze-uclinux mailing list - > there's a greater concentration of people able to assist there than here > on comp.arch.fpga. Details here: > > http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List I'm already subscribed :-) Many thanks RegardsArticle: 115059
Hello, we want to use a Spartan-3A to collect signals of about 100 differential lines. This type offers the possibility for on-chip LVDS termination. Is there a limit how many pairs per bank can be terminated via the on-chip resistor? Where may I find further information? Thanks TomArticle: 115060
Thanks Martin. I am using a virtex 4 sx35. There are some specific details i am unsure of maybe you can help with. The development board i am using has a CPLD which connects to a flash memory and the FPGA, when i have new code i connect to the CPLD and upload it to the flash. With every boot of the developement board the CPLD then programs the FPGA with the code i have previously uploaded. I also have another flash memory(completely seperate from this programming interface) and a DDR. I can load my project with the bootloader application onto the board, run it and i get various error messages(throuhgh the RS232) because i have not loaded the main program. Now here comes the problem. The bootloader is trying to copy data from the 4MB flash to the DDR then run it, 1) how do i get the real program into the 4MB flash? It seems that i should be able to set this up as part of the hardware within the project but i can't find a way of "initialising" the memories. 2) tutorials i've been reading tell me to use the "program flash memory" option in the EDK, but this causes me a problem. From what i can make out, loading data to the flash in this way requires the hardware part of the project to be loaded on the FPGA already, does this mean when loading data to the flash i am interacting directly to the FPGA with the hardware part of the project? When i program my FPGA as i mentioned earlier i don't interact with it at all but instead interact with it via a CPLD. Can you see my problem? more importantly....can you see my answer? I hope you have time to answer. Thanks DanArticle: 115061
Hello all, Does anybody have a simple example I can load on this board, which works in EDK 8.2 and uses the xsga port? I want to understand how this thingie works. The only thing I achieved until now is reading buttons and enlighting leds... grtz, WouterArticle: 115062
Geronimo Stempovski wrote: > I recently heard about some 60 GHz in the mobile communication sector and 10 > Gbit Ethernet but as far as I know there are those multi-level modulation > methods (like QAM for example) that are able to provide 10 Gbit bandwidth > with a bitrate of some Mbps (is that correct?). Last I heard, 10GbaseT runs at 800Mbaud with the gloriously named 128-DoubleSquare line code. And lots of other clever stuff, such as Tomlinson-Harashima precoding, which others on c.a.f. will jump in to explain ;-) So the baud rate (i.e. symbol rate or changes on the line) is 800 million per second. TimArticle: 115063
billu <bkamakot@gmail.com> wrote: >Hi All, >I was wondering if its possible to stream data at 480Mbps from a PC to >a USB 2.0 port on a FPGA development board and send the data out of a >SMA port on the board. The XUPV2P board has an onboard USB 2.0 and SMA >ports. Can this board be used for this application? What's your requirements regarding: * Throughout * Latency * Ease of use * UbiquityArticle: 115064
I have a source code which is compiled by the Design Compiler from Synopsys. I also mapped my technology library to that, so it will generate a VHDL netlist. My problem is that there are Components declarations and instantiations in the netlist with no architecture. And I'd like to use this netlist as a component of my design in Altera's Quartus software. Can someone tell me how I get this fixed. ThanksArticle: 115065
"wallge" <wallge@gmail.com> writes:
> Are you saying that I don't need to activate/precharge the bank when
> switching to another?
Not necessarily.
> I am kind of unclear on this. When do activate and precharge
> commands need to be issued? I thought when switching to a new row or
> bank you had to precharge (close) the previously active one, then
> activate the new row/bank before actually reading from or writing to
> it. Where am I going wrong here?
You have to precharge a bank only when you switch to another row
within that bank.
> Also to the notion that I don't need to refresh since I am doing
> video buffering: I am actually buffering multiple frames of video
> and then reading out several frames later. In other words, there may
> be a significant fraction of a second (say 1/8~1/4 sec) of delay
> between writing data into a particular page of memory and actually
> reading it back out. Is this too much time to expect my pixel data
> to still be valid without refreshing?
That very much depends on the access patterns. The fact that you are
going to implement a frame buffer alone doesn't automatically mean
that you won't need a refresh. Double-, or triple-check your specs. If
in doubt I'd definitely recommend putting in a refresh as low priority
task.
Regards,
Marcus
--
note that "property" can also be used as syntaxtic sugar to reference
a property, breaking the clean design of verilog; [...]
-- Michael McNamara
(http://www.veripool.com/verilog-mode_news.html)
Article: 115066I'ved used the FX2 with a FPGA for several projects and it has worked well, but... it always take more work than I expect. >From my experience, the maximum data rate should plan for on the USB is 25 to 30 MB/sec, ie, 240 Mbits/sec. This is far below the 480Mb raw data rate, but I think it's hard to get a lot better than this given the s/ w driver overhead, etc. If you project *requires* a data rate near 480Mb/sec, you are probably doomed from the start to failure. I hope someone has expererience (and tips) that show me to be wrong! John Providenza On Jan 30, 5:25 am, pbF...@ludd.invalid wrote: > billu <bkama...@gmail.com> wrote: > >Hi All, > >I was wondering if its possible to stream data at 480Mbps from a PC to > >a USB 2.0 port on a FPGA development board and send the data out of a > >SMA port on the board. The XUPV2P board has an onboard USB 2.0 and SMA > >ports. Can this board be used for this application? > > What's your requirements regarding: > * Throughout > * Latency > * Ease of use > * UbiquityArticle: 115067
Hello, can anyone explain to me how to use the test bench waveform simulator. I am receiving a clock and another signal and some yellow spikes on the screen. Reg.Article: 115068
On Jan 29, 10:50 am, "wallge" <wal...@gmail.com> wrote: > Gabor, > > Are you saying that I don't need to activate/precharge the bank > when switching to another? First of all, you don't "switch" banks. There are four banks that can all potentially be active at a given time. Only the external interface works on one bank at a time. That being said, realise that the control interface (address, ras, cas, we) is somewhat independent of the data interface (dq). > I am kind of unclear on this. When do activate and precharge commands > need to be issued? I thought when switching to a new row or bank you > had > to precharge (close) the previously active one, then activate the new > row/bank before > actually reading from or writing to it. Where am I going wrong here? > You need to precharge a bank before opening a new row in _THAT_ bank. Other banks may remain open while this happens. When doing single burst accesses, I generally precharge using the read or write command with auto-precharge (A10 high during CAS). > Also to the notion that I don't need to refresh since I am doing video > buffering: I am actually buffering multiple frames of video and then > reading > out several frames later. In other words, there may be a significant > fraction > of a second (say 1/8~1/4 sec) of delay between writing data into a > particular page of memory and actually reading it back out. What's a page? These RAMs have rows. Each row must be accessed using row activate or else refreshed within the refresh period. If you store data in successive rows / banks first, and then successive columns (i.e. row/bank form LSB's of your address), you will usually refresh the entire part without accessing a large portion of the entire memory. Here's a typical sequence I use for writing streaming data into an SDRAM: Cycle Command Bank Addr Data startup sequence has unused cycles (NOPs) 1 ACT 0 row0 x 2 NOP x x x 3 ACT 1 row0 x 4 NOP x x x 5 ACT 2 row0 x full streaming starts here (burst size = 2) 6 WRITEA 0 col0 data0 7 ACT 3 row0 data0 8 WRITEA 1 col0 data1 9 ACT 0 row1 data1 10 WRITEA 2 col0 data2 11 ACT 1 row1 data2 12 WRITEA 3 col0 data3 13 ACT 2 row1 data3 14 WRITEA 0 col0 data4 15 ACT 3 row1 data4 16 WRITEA 1 col0 data5 above sequence (streaming can be repeated ad nauseum) end sequence has unused cycles (NOPs) 17 NOP x x data5 18 WRITEA 2 col0 data6 19 NOP x x data6 20 WRITEA 3 col0 data7 21 NOP x x data7 WRITEA is write command with autoprecharge (A10 = 1) Reading is similar except there are pipeline delays on the data bus due to CAS read access time. Regards, GaborArticle: 115069
johnp wrote: >>From my experience, the maximum data rate should plan for on the USB > is > 25 to 30 MB/sec, ie, 240 Mbits/sec. This is far below the 480Mb raw > data > rate, but I think it's hard to get a lot better than this given the s/ > w driver > overhead, etc. And the Windows XP latency can be several seconds. -- Tim From invalid@dont.spam Tue Jan 30 08:02:28 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!nx02.iad01.newshosting.com!newshosting.com!130.81.64.211.MISMATCH!cycny01.gnilink.net!spamkiller2.gnilink.net!gnilink.net!trndny04.POSTED!933f7776!not-for-mail From: Phil Hays <invalid@dont.spam> Subject: Re: Xilinx Timing Constraints and failures User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table) Message-Id: <pan.2007.01.30.16.06.04.6011@dont.spam> Newsgroups: comp.arch.fpga References: <1170100597.223585.85810@a75g2000cwd.googlegroups.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 46 Date: Tue, 30 Jan 2007 16:02:28 GMT NNTP-Posting-Host: 71.112.133.239 X-Complaints-To: abuse@verizon.net X-Trace: trndny04 1170172948 71.112.133.239 (Tue, 30 Jan 2007 11:02:28 EST) NNTP-Posting-Date: Tue, 30 Jan 2007 11:02:28 EST Xref: prodigy.net comp.arch.fpga:126348 moogyd wrote: > Master clock 16MHz, some logic is clocked at 8 or 4MHz, therefore only > get a pulse every 2 or 4 clock cycles (we actually have about 12 > clocks). In an ASIC flow, we can balance everything from the 16MHz clock > and it will work. > This is my first complex FPGA, and I have a number of questions > > - When ISE has completed, there are a number of unplaced components, > even thought utilization is low. > Is this because it has failed timing, so it doesn't even bother. - We > may change to locally gated clocks (i.e. so that we only have one global > clock). I still need to define the multi-cycle paths. > Can anyone supply, or provide a link to, some example constraint > files for this type of application. > - Any other pointers or suggestions would be greatly appreciated. My suggestions are: 1) Fix the clocking problem: a) spend money on "Synplify Pro" (www.synplicity.com), which is a synthesis tool that will do automatic "gated clock conversion". That is, convert a gated clock to a global clock with clock enables. Mentor has a similar product, (www.mentor.com) b) Or spend time, and write your code so that switching between a gated clock for the ASIC and clock enables for the FPGA is handled by a constant, generic, conditional compile, component, etc. Might want to use a DCM to generate lower frequency clocks, however minimum input frequency is 18 MHz. 2) Unplaced components next. What is "utilization is low", in percent? Gated clocks can limit utilization, so fixing clocking first may very well help this issue. More detail is needed to help much on this one. 3) Timing next. 16MHz isn't very fast, so you may not need to worry about multicycle paths. With the issues of clocking and unplaced components, the timing report isn't very meaningful, so fix the first two problems, then look at timing. -- Phil Hays (Xilinx, but writing for myself)Article: 115070
I just wanted to say thanks to everyone for responding with a lot of helpful answers and feedback in this post. Really great forum. On Jan 30, 10:32 am, "Gabor" <g...@alacron.com> wrote: > On Jan 29, 10:50 am, "wallge" <wal...@gmail.com> wrote: > > > Gabor, > > > Are you saying that I don't need to activate/precharge the bank > > when switching to another?First of all, you don't "switch" banks. There are four banks that can > all potentially be active at a given time. Only the external > interface > works on one bank at a time. That being said, realise that the > control interface (address, ras, cas, we) is somewhat independent > of the data interface (dq). > > > I am kind of unclear on this. When do activate and precharge commands > > need to be issued? I thought when switching to a new row or bank you > > had > > to precharge (close) the previously active one, then activate the new > > row/bank before > > actually reading from or writing to it. Where am I going wrong here?You need to precharge a bank before opening a new row in _THAT_ > bank. Other banks may remain open while this happens. When > doing single burst accesses, I generally precharge using the > read or write command with auto-precharge (A10 high during CAS). > > > Also to the notion that I don't need to refresh since I am doing video > > buffering: I am actually buffering multiple frames of video and then > > reading > > out several frames later. In other words, there may be a significant > > fraction > > of a second (say 1/8~1/4 sec) of delay between writing data into a > > particular page of memory and actually reading it back out.What's a page? These RAMs have rows. Each row must be accessed > using row activate or else refreshed within the refresh period. If > you > store data in successive rows / banks first, and then successive > columns (i.e. row/bank form LSB's of your address), you will usually > refresh the entire part without accessing a large portion of the > entire > memory. > > Here's a typical sequence I use for writing streaming data into > an SDRAM: > > Cycle Command Bank Addr Data > startup sequence has unused cycles (NOPs) > 1 ACT 0 row0 x > 2 NOP x x x > 3 ACT 1 row0 x > 4 NOP x x x > 5 ACT 2 row0 x > full streaming starts here (burst size = 2) > 6 WRITEA 0 col0 data0 > 7 ACT 3 row0 data0 > 8 WRITEA 1 col0 data1 > 9 ACT 0 row1 data1 > 10 WRITEA 2 col0 data2 > 11 ACT 1 row1 data2 > 12 WRITEA 3 col0 data3 > 13 ACT 2 row1 data3 > 14 WRITEA 0 col0 data4 > 15 ACT 3 row1 data4 > 16 WRITEA 1 col0 data5 > above sequence (streaming can be repeated ad nauseum) > end sequence has unused cycles (NOPs) > 17 NOP x x data5 > 18 WRITEA 2 col0 data6 > 19 NOP x x data6 > 20 WRITEA 3 col0 data7 > 21 NOP x x data7 > > WRITEA is write command with autoprecharge (A10 = 1) > > Reading is similar except there are pipeline delays on the data bus > due to CAS read access time. > > Regards, > GaborArticle: 115071
Yea, I figured that was the case. However, I have no always
statements that are not of the form:
always @(posedge clk)
begin
foo <= bar
end
all of my always statements are driven off of clock. I do have if
statements within the always statements that depend on rst. will this
cause it to be seen as a clock?
On Jan 29, 8:42 pm, Ben Jackson <b...@ben.com> wrote:
> On 2007-01-29, idp2 <ian.pei...@gmail.com> wrote:
>
>
>
> > I have assigned my two clock signals PCI_CLK and DHSM_CLK to GCLKBUF0
> > and GCLKBUF1 respectively. However, when I compile it gives an error
> > that PCI_RST should be assigned to a GCLK.I'm guessing that your HDL is not matching a standard sync or async
> reset flipflop and so RST ends up looking like a clk. For example,
> if you say:
>
> always @(posedge rst)
> foo <= bar;
>
> (maybe foo latches a config strapping pin 'bar') then rst is going to
> be treated as a clock.
>
> --
> Ben Jackson AD7GD
> <b...@ben.com>http://www.ben.com/
Article: 115072<boled> wrote in message news:45bf5d08$1_3@mk-nntp-2.news.uk.tiscali.com... > Hello, can anyone explain to me how to use the test bench > waveform simulator. I am receiving a clock and another > signal and some yellow spikes on the screen. > Reg. > > Have you bothered to look at the documentation for the simulator? MikeArticle: 115073
With that solution you will also be limited to a maximum rate of 30MHz which means you may see a data rate of 15Mbs if your lucky. ---Matthew Hicks > On 2007-01-29, billu <bkamakot@gmail.com> wrote: > >> Hi All, >> >> I was wondering if its possible to stream data at 480Mbps from a PC >> to a USB 2.0 port on a FPGA development board and send the data out >> of a SMA port on the board. The XUPV2P board has an onboard USB 2.0 >> and SMA ports. Can this board be used for this application? >> > The USB2 port on the XUPV2P board is only designed as a USB > programming cable replacement for the purpose of configuring the FPGA. > It is actually possible to work around this (look for the xup > programming tool), but I guess it will be a lot of work to actually > get it working on the XUPV2P board. > > /Andreas >Article: 115074
"Geronimo Stempovski" <geronimo.stempovski@arcor.de> wrote in message news:45bf1bb4$0$27613$9b4e6d93@newsspool2.arcor-online.net... > I'm not interested so much in those higher modulation methods (nor in > optical transmission) but in the baseband communication where bitrate = > clockrate, i.e. the line rate. What can be efficiently transmitted today > electrically (over wire or PCB)? It's around 1Gbps that you really need to start paying attention to your board materials, transmission lines, etc.: With inexpensive boards (e.g., FR-4), you're at the point where you're starting to get significant loss, dispersion, and distance limitations. Check out this file: http://www.xilinx.com/esp/wired/optical/collateral/xaui_xgmii.pdf -- XAUI achieves 10Gbps using four 3.125Gbps differential signals (there's overhead on each one...), and they manage to run it 20" on cheap PCBs -- that's pretty impressive.
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