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Hi, Is there any way of implementing DPRAM from single port RAM's?(may be by connecting two SPRAM's) ThanksArticle: 115776
vlsi_learner wrote: > Hi, > > Is there any way of implementing DPRAM from single port RAM's?(may be > by connecting two SPRAM's) > > Thanks Maybe. Do you have extra clock cycles available to do multiple reads and writes in one memory and make it "look" like a mult-port memory? Is you SPRAM truly only one address? There are "pseudo" dual-port memories and "true" dual port memories. A true dual port can be made from 2 pseudo dual ports. So. What is the structure of your SPRAM? What DPRAM structure do you want? What is your operating frequency versus maximum memory frequency? Are you targeting a specific device?Article: 115777
On Feb 19, 10:27 am, "Charles" <charles...@yahoo.com> wrote: > I have some very basic problems getting simple things to work on this > platform. Is there a quirk of this product this i don't know about?? > seem to have problems with counters and state machines.. All adders are ripple carry, so timing is a big concern. Also read the data sheet carefully. Their JTAG interface has problems. You can actually powerup the device with the boundry scan logic enabled in an arbitrary state that can damage the device. It happen to me. I ended up with a 150 ohm resistor tied to TRST to ground to keep the JTAG in reset when not in use. Also with the Flash Pro, it took 5 mins to program a APA150. DaveArticle: 115778
Hello, I'm new in using ISE and I'm trying to start project for Virtex2 FPGA with 1M gates - but in Project Properties (after selecting "Virtex2" in Family field) I can't find xc2v1000 as an option in Device field. Only options I find are "xc2v40", "xc2v80", "xc2v250" and "xc2v500". I'm using ISE 9.1i with Service Pack 1, but the same problem occurs wit ISE 7.1i with Service Pack 4. Does anyone have some suggestion what should I do to make option "xc2v1000" available? Thanks a lot for every help! All the best, VladimirArticle: 115779
On Feb 20, 9:48 am, "Vladimir Orlic" <vladimiror...@yahoo.com> wrote: > Hello, > > I'm new in using ISE and I'm trying to start project for Virtex2 FPGA with 1M gates - but in Project Properties (after selecting "Virtex2" in Family field) I can't find xc2v1000 as an option in Device field. Only options I find are "xc2v40", "xc2v80", "xc2v250" and "xc2v500". I'm using ISE 9.1i with Service Pack 1, but the same problem occurs wit ISE 7.1i with Service Pack 4. Does anyone have some suggestion what should I do to make option "xc2v1000" available? Thanks a lot for every help! All the best, > > Vladimir Vladimir My _guess_ is that you are using the free ISE WebPack. I think that only the $$$ version of ISE supports the larger chips. Somewhere on Xilinx's site there should be a list of which versions of ISE supports what chips. HTH -Dave PollumArticle: 115780
<dscolson@rcn.com> wrote in message news:1171982446.526621.96280@v33g2000cwv.googlegroups.com... > On Feb 19, 10:27 am, "Charles" <charles...@yahoo.com> wrote: >> I have some very basic problems getting simple things to work on this >> platform. Is there a quirk of this product this i don't know about?? >> seem to have problems with counters and state machines.. > > All adders are ripple carry, so timing is a big concern. Also read the > data sheet carefully. Their JTAG > interface has problems. You can actually powerup the device with the > boundry scan logic enabled in an arbitrary state that can damage the > device. It happen to me. I ended up with a 150 ohm resistor tied to > TRST to ground > to keep the JTAG in reset when not in use. This applies to other JTAG devices as well even very expensive space-qualified RT/RH Actel fpgas and microcontroller. http://www.klabs.org/richcontent/maplug/notices/na-gsfc-2004-04.pdf Also with the Flash Pro, it > took 5 mins to program a APA150. My APA1000 takes 22 minutes to program (and verify programmed/non-programmed bits) using a parallel port FlashPro-lite programmer, Hans www.ht-lab.com > Dave >Article: 115781
Hi John, My SPRAM will have only one address.The DPRAM needs to be such that I will only write through portA & only read through port B. On Feb 20, 6:28 am, John_H <newsgr...@johnhandwork.com> wrote: > vlsi_learner wrote: > > Hi, > > > Is there any way of implementing DPRAM from single port RAM's?(may be > > by connecting two SPRAM's) > > > Thanks > > Maybe. > > Do you have extra clock cycles available to do multiple reads and writes > in one memory and make it "look" like a mult-port memory? > > Is you SPRAM truly only one address? There are "pseudo" dual-port > memories and "true" dual port memories. A true dual port can be made > from 2 pseudo dual ports. > > So. What is the structure of your SPRAM? What DPRAM structure do you > want? What is your operating frequency versus maximum memory frequency? > Are you targeting a specific device?Article: 115782
On Feb 18, 12:34 am, Austin <aus...@xilinx.com> wrote: > ricky, > > Peter and I take this issue of pricing and availability quite seriously. > > We have begun discussions on the issue. Well, I guess finally someone notice it.. Obviously, Avnet and NuHorizon has bad attitude towards SME and consultants (and to those who dont want to buy 1000 pieces for prototyping). If I run Xilinx, I would choose another distributor that's willing to help prototyping industries or there are no more mass quantity order for Xilinx's. (no prototype, no mass product). -kunilArticle: 115783
Zara is correct: When CLKFX is used (by itself), the input clock can be lower than 24 MHz. Just make sure that you are not using CLK0, 90, 180, 270 nor CLK2X, nor CLKDV. Do not connect anything to the CLKFB input. AustinArticle: 115784
kunil, Just one small problem: what other distributor(s)? Seems that the distributor business has "consolidated" down to two major distis. One carries Altera, and one carries Xilinx. I know that in some parts of the world, there are still more than these two choices, but increasingly we will see consolidation even in those marketplaces. A distributor is increasingly challenged to provide value, and not add cost. How is this possible? If customers are unwilling to pay any premium whatsoever, and demand the lowest possible prices, they leave no room for anyone to profit, and as a result there is no shelf stock at all (anywhere). And, no services. "Just in time" becomes "just late." How does a distributor pay their 200 Field Applications Engineers? (rough estimate of how many FAEs support Xilinx, we also have a similar number of factory FAEs, and how do we pay for their work effort if not through the sales price?) Stockholders freak out if there is more than 120 days of inventory at the factory (and rightly so). If we overbuild, at the rate prices erode on a new process/product, we end up taking a loss if we don't ship everything as it is built. Imagine that this week is costs 1/2 as much to sell V5 as it did when it was introduced. Well, then all the inventory is now worth 1/2 as much. The result is a loss must appear on the financials. But, if we ship all the parts before the prices erode, we do not have to write off anything. Peter and I also understand that small companies sometimes become big companies. There are many examples of remarkably successful companies, and many of them (most of them) use FPGA technology. How do we continue to support the "onsy-twosy" crowd while also supporting the Nokia, Cisco, Huawei, Alcatel (etc) crowd? How do we keep customers happy? How do we provide the necessary engineering support? How do we make shareholders happy? Stay tuned.... AustinArticle: 115785
"kunil" <kunilkuda@gmail.com> wrote in message news:1171987031.968482.203320@p10g2000cwp.googlegroups.com... > Obviously, Avnet and NuHorizon has bad attitude towards SME and > consultants (and to those who dont want to buy 1000 pieces for > prototyping). I am a consultant, and have had good luck with Avnet and with the local rep organization. There's never been too much of a problem getting prototypes and pilot-production Xilinx parts for any of my clients. Have you tried getting in touch with the local rep organization? A good relationship with them could work wonders.Article: 115786
For the answers to all of your configuration questions read XAPP 501 and DS 123. ---Matthew Hicks > i have a problem while configuring the virtex2 pro fpga in slave > serial mode i am using platform flash RPOM of XC40FS serial flash > prom. i am not getting the done pin high after configuration. > > my doubt is whether i have to connect the external ossilator (slave > serial mode) in order to supply clk form PROM to CCLK of fpga. i read > that if it is in slave select map mode and if the PROM is of parllel > prom we need to supply clock though external ossilator what the case > with serial prom. i am not getting the cclk when i am debugging with > ossilocope. > > what is the major difference between master serial and slave serial > (its with rescpect to clock that fpga provides clock when it is in > master m9de and the prom or external ossilator supplies clock when it > is in slave serial mode or any other particular difference is there.) > > regards > srikArticle: 115787
And I'll repeat the other questions: What is your operating frequency versus maximum memory frequency? If you have a 50 MHz read/write clock and your memory can give you 300 MHz performance, you can use a faster clock and time multiplex your writes and reads. Are you targeting a specific device? If you don't know the device capabilities but have a specific FPGA or ASIC in mind, perhaps you could get specific help from those who know your target well. If this is just a homework problem - no specific device, no specific frequency - be up front about it and you're more likely to get good help. - John_H "vlsifresher" <bajajk@gmail.com> wrote in message news:1171986778.256284.152970@q2g2000cwa.googlegroups.com... > Hi John, > > My SPRAM will have only one address.The DPRAM needs to be such that I > will only write through portA & only read through port B. > > On Feb 20, 6:28 am, John_H <newsgr...@johnhandwork.com> wrote: >> vlsi_learner wrote: >> > Hi, >> >> > Is there any way of implementing DPRAM from single port RAM's?(may be >> > by connecting two SPRAM's) >> >> > Thanks >> >> Maybe. >> >> Do you have extra clock cycles available to do multiple reads and writes >> in one memory and make it "look" like a mult-port memory? >> >> Is you SPRAM truly only one address? There are "pseudo" dual-port >> memories and "true" dual port memories. A true dual port can be made >> from 2 pseudo dual ports. >> >> So. What is the structure of your SPRAM? What DPRAM structure do you >> want? What is your operating frequency versus maximum memory frequency? >> Are you targeting a specific device? > >Article: 115788
Hello, I have tried to implement uclinux (from Petalogix) in a Spartan 3E. I have followed the Spartan 3E tutorial, but when I reboot my fpga, the terminal says: No existing image in FLASH. So I program the FLASH again, but I can't boot uclinux. What I do is: U-Boot> loadb 0x22000000 ## Ready for binary (kermit) download to 0x22000000 at 115200 bps... (Back at localhost.localdomain) ---------------------------------------------------- C-Kermit 8.0.211, 10 Apr 2004, for Linux Copyright (C) 1985, 2004, Trustees of Columbia University in the City of New York. Type ? or HELP for help. (/home/pablo/) C-Kermit>send /bin /tftpboot/ub.config.img (/home/pablo/) C-Kermit>connect Connecting to /dev/ttyUSB0, speed 115200 Escape character: Ctrl-\ (ASCII 28, FS): enabled Type the escape character followed by C to get back, or followed by ? to see other options. ---------------------------------------------------- ## Total Size = 0x000003eb = 1003 Bytes ## Start Addr = 0x22000000 U-Boot> autoscr $(fileaddr) ## Executing script at 00000000 Bad magic number U-Boot> autoscr $(fileaddr) ## Executing script at 22000000 PetaLogix MicroBlaze-Auto Board Configuration --------------------------------------------- Network Configuration: MTD Configuration: Clobber DRAM Configuration: Bootloader Configuration: Kernel Configuration: Boot Configuration: Saving Configurations... Saving Environment to Flash... Un-Protected 2 sectors Erasing Flash... .. done Erased 2 sectors Writing to Flash... done Protected 2 sectors Configuration Completed U-Boot> loadb $(clobstart) ## Ready for binary (kermit) download to 0x22000000 at 115200 bps... (Back at localhost.localdomain) ---------------------------------------------------- (/home/pablo/) C-Kermit>send /tftpboot/u-boot-s.bin (/home/pablo/) C-Kermit>connect Connecting to /dev/ttyUSB0, speed 115200 Escape character: Ctrl-\ (ASCII 28, FS): enabled Type the escape character followed by C to get back, or followed by ? to see other options. ---------------------------------------------------- ## Total Size = 0x00018f58 = 102232 Bytes ## Start Addr = 0x22000000 U-Boot> protect off $(bootstart) + $(bootsize) Usage: protect - enable or disable FLASH write protection U-Boot> erase $(bootstart) + $(bootsize) Usage: erase - erase FLASH memory U-Boot> cp.b $(fileaddr) $(bootstart) $(filesize) Usage: cp - memory copy U-Boot> loadb $(clobstart) ## Ready for binary (kermit) download to 0x22000000 at 115200 bps... (Back at localhost.localdomain) ---------------------------------------------------- (/home/pablo/) C-Kermit>send /tftpboot/image.ub (/home/pablo/) C-Kermit>connect Connecting to /dev/ttyUSB0, speed 115200 Escape character: Ctrl-\ (ASCII 28, FS): enabled Type the escape character followed by C to get back, or followed by ? to see other options. ---------------------------------------------------- ## Total Size = 0x002ee040 = 3072064 Bytes ## Start Addr = 0x22000000 U-Boot> protect off $(kernstart) + $(kernsize) Usage: protect - enable or disable FLASH write protection U-Boot> erase $(kernstart) + $(kernsize) Usage: erase - erase FLASH memory U-Boot> cp.b $(fileaddr) $(kernstart) $(filesize) Usage: cp - memory copyArticle: 115789
I have an I2C master written in VHDL that sends init data to some off board chips via the expansion port. This is done in entirely with the ISE and not the software studio. If you are interested send me your email address and I'll send it to you. Brad Smallridge brad at aivision dot com <m.afgani@gmail.com> wrote in message news:1171967061.231366.262230@v45g2000cwv.googlegroups.com... > Hello, > > I recently obtained a ML402 Virtex-4 SX35 evaluation board from Xilinx > and would like to use it to communicate with some I2C slave devices. > What is the proper way to do this? I am new to FPGA / HDL designing > and feel a little lost. > > The data sheet for the ML402 states that there is an I2C bus that can > be used to connect additional hardware. Is there a hardware master > controller or do I still need to use a software I2C controller core? > > I'd really appreciate any help that I can get. > > Thanks in advance, > Mostafa >Article: 115790
Hi all, before doing the hardware implementation I wanna trace the instruction buffer in a simulator for some special algorithms. Could anyone suggest me a dual-issue simulator that allows to investigate the instruction buffer or that keeps a history of the instruction buffer to see at what cycle the instructions were in the buffer? Thanks for any suggestions, P.Article: 115791
Does anyone have any of these things for sale? I missed out when they came out, and would love to get my hands on a couple. If anyone has any unused laying around.. please let me know..Article: 115792
On Feb 19, 8:00 pm, "Aaron" <weiro...@gmail.com> wrote: > Hi all, > > I want to evaluate the area and time cost of an intermediate product > on Xilinx FPGA. But the number of > output ports exceed number of I/O pins. (Actually there will be much > less outputs in the final product. ) > > But currently, I need test the intermediate product by using Xilinx > ISE. Can I add some ISE specific declaration to avoid the fully IO > mapping while I can still get the area and time cost reports? > > Thanks a lot. > > Sincerely, > Aaron Theoretically (i.e. I have never tried this. sorry ;)) you can use "map -u" (do not remove unused logic) with "TPSYNC" and/or "TPTHRU" contraints. Cheers, Jim http://home.comcast.net/~jimwu88/tools/Article: 115793
Hi Vladimir, if you have the free version ISE 9.1i (Webpack), you won't get xc2v1000. You have to pay the full blown version of ISE to get that. However, there may be a workaround. Download the old ISE Webpack 6.3i and its Service Pack 3 from http://www.xilinx.com/webpack/classics/wpclassic/index.htm. When Xilinx released Service Pack 3 for Webpack 6.3i, they "accidentally" included larger FPGA families that is not supposed to be there. I remember that they include all members of Spartan 3. So, they may also include all members of Virtex 2 as well. Note that Webpack 6.3i does not include FPGA Editor and Core Generator. Good luck! FrankArticle: 115794
On Feb 20, 8:53 am, "cpope" <cep...@nc.rr.com> wrote: > Unfortunately I only have low speed serial links so it woudl take about an > hour to transfer the flash contents. > So run them faster when downloading the code. Or use an additional link for this purpose. Remember, jtag is just a synchronous serial interface, with a mode pin... there's no reason you can't get comparable throughput from a simple function temporarily downloaded into your FPGA. In fact you should be able to do better, as you could minimize the overhead.Article: 115795
Vladimir, another approach would be to use a more modern device, like the Virtex-4 LX25. This is almost the smallest part in that family, but has twice as many resources (>20 000 LUTs) than the XC2V1000, which -in its days- was considered one of the larger devices in its family. Evolution is very fast in our industry, and it may be wise to move to a more modern family (Virtex-4 is about 3 years old) with a lower price, faster performance, and better software support. If you want to compare logic sizes roughly: After Virtex-2 we knocked two zeros off the designator, so your -1000 is equivalent to a -10 in Virtex-4 and later (but the newer Virtex families do not have such small parts anymore). Logic has become very cheap... Take a look at it. Peter Alfke, Xilinx Applications On Feb 20, 6:48 am, "Vladimir Orlic" <vladimiror...@yahoo.com> wrote: > I'm new in using ISE and I'm trying to start project for Virtex2 FPGA with 1M gates - but in Project Properties (after selecting "Virtex2" in Family field) I can't find xc2v1000 as an option in Device field. Only options I find are "xc2v40", "xc2v80", "xc2v250" and "xc2v500". I'm using ISE 9.1i with Service Pack 1, but the same problem occurs wit ISE 7.1i with Service Pack 4. Does anyone have some suggestion what should I do to make option "xc2v1000" available? Thanks a lot for every help! All the best, > > VladimirArticle: 115796
Wow, your chisel gets a workout. I have a Nexys-1000 which seems to program correctly with an FX2 expansion board plugged in (using the Digilent software with the onboard USB JTAG) - did you have JTAG problems with the parallel cable or the onboard programmer (or both)? Your custom firmware and interface software sound really useful - do you have a web site detailing your modifications? cs_posting@hotmail.com wrote: > Recently I ordered a Nexys Spartan3-1000 / Cypress FX2 USB board from > Digilent for work. It's been fun and I may well buy one personally, > but like aways there are the suprises, the silly mistakes, and the 3 > am still-doesn't-work-yets. > > First impression is consistent with what I saw on the web site - it's > a nifty little board. > The stock version has a smaller FPGA, but the S3-1000 is only $20 more > (of course that meant I spent all night downloading a new Webpack) > > The new high density I/O connector finally has enough grounds (though > confusingly the connector family is referred to as fx2 - not to be > confused with the usb chip!) > > The mini-USB jack broke off the board within the first hour, and on > examination is seems that the metal shield tabs never really soldered > to the board. Not too hard to fix, though it took a ton of heat to > get it soldered down, and even then it is more the solder I added to > the board "encapsulating" the lugs than wetting them. > > It turns out the USB chip only has the 8 bits of port B connected to > the FPGA, so FIFO transfers will have to be 8 bit. Probably not a > problem, but one could wish for 16 bit. > > The other 8 bits include the JTAG signals, some control bits, and some > unused bits. Digilent's Adept software can download .bit files using > these. I was also able to program the board using an old digilent > budget parallel cable from an s3kit. > > The expansion boards that plug in are spacious and worth getting more > than one of. Unfortunately, plutting them in killed the jtag. Seeing > the jtag is extended onto the expansion board I suspected long trace > lengths and - it being Firday afternoon - simply chiseled them at the > connector. That worked (wondering why there were 5 traces instead of > 4) but turned out to be silly - turns out that plugging in the > expansion board over-rides (via the 5th trace) a resistor controlling > a gate shunting the expansion connector in other words, with the > expansion connector plugged in, the jtag needs to have a shunt on the > expansion board. Oh well, I can fix the expansion cards easily enough > in the unlikely event I ever need JTAG out there. > > I then embarked on a hacking binge trying to download Cypress firmware > and/or program the FPGA by using libusb on windows. 24 hours later, > both work, via modified versions of the XUP & XC3SProg projects. > > Some discoveries: > > - at least under windows, must call usb_set_configuration() before > usb_claim_interface(), had to modify the programs accordingly > > - for some reason, even building with MinGW g++ I get a reliance on > cygwin1.dll > > - Digilent put a VID/PID eeprom on the board. Can modify the software > to look for that VID/PID, or I finally just chiseled the trace across > JP2 and am back to talking to cypress default VID/PID. I plan to > install the jumper pins so I can quickly switch between compatability > with the Digilent ADEPT software vs. homegrown efforts, and leverage > the difference in identity to avoid any conflicts in having both > digilent and libusb drivers installed on the computer. > > - I modified XUP and it's X3SProg ioxusb.cpp to use the Nexys jtag pin > assignments to port PD instead of those of the s3ekit or usb > programming cable it was written for. > > - PD6 controls a gate which puts the USB chip in the JTAG path. > > - PD7 controls the voltage regulator for the rest of the board. > HOWEVER, the FPGA will run (via the protection diodes I assume) off > the JTAG signals if you leave them driven with this shut down. I > added a new command (0xff) to the xup <->firmware interface that > tristates all of the jtag signals when configuration is done to avoid > this. This also re-enables the jtag header on the board for other > programming methods. > > My hacked up xup and XC3Sprog are a bit messy right now, but I may see > about trying to contribute at least a description of the changes back > to their authors. > > Of course I'm still not doing anything _useful_ with the board... but > that may wait for Monday. >Article: 115797
Hi, > Has anybody: > > A) Used MIG to generate a DDR2 core in x16 configuration for V4? > (Antti, from one of your previous posts, I think you have a yes answer > to this) I have used MIG1.6 from coregenerator to generate DDR2 Controller Blocks (1st- 64-bit (4 x16-bit), 2nd - 32-bit (2 x16-bit). > B) Found any meaningful documentation of the MIG and/or the DDR2 core > specifically? (The user guide that comes with it is a little light.) You can find the documentation in docs directory of generated files. > C) If yes to A, what docs did you find the interface spec in? or did > you just start reading the source code? MIG documentation is good start along with XAPP702 and 703 app note. Had some problems with calibration - which the xilinx controller does to get delay values for IDELAYCTRL blocks. Still working on with it. Regards RaoArticle: 115798
Purchase a few hundred chips internally, sell them on your online store as not for production use (preferably with the aforementioned paypal button) and write off the declining book value as a marketing expense? Austin Lesea wrote: > kunil, > > Just one small problem: what other distributor(s)? Seems that the > distributor business has "consolidated" down to two major distis. > > One carries Altera, and one carries Xilinx. > > I know that in some parts of the world, there are still more than these > two choices, but increasingly we will see consolidation even in those > marketplaces. > > A distributor is increasingly challenged to provide value, and not add > cost. How is this possible? If customers are unwilling to pay any > premium whatsoever, and demand the lowest possible prices, they leave no > room for anyone to profit, and as a result there is no shelf stock at > all (anywhere). And, no services. > > "Just in time" becomes "just late." How does a distributor pay their > 200 Field Applications Engineers? (rough estimate of how many FAEs > support Xilinx, we also have a similar number of factory FAEs, and how > do we pay for their work effort if not through the sales price?) > > Stockholders freak out if there is more than 120 days of inventory at > the factory (and rightly so). If we overbuild, at the rate prices erode > on a new process/product, we end up taking a loss if we don't ship > everything as it is built. > > Imagine that this week is costs 1/2 as much to sell V5 as it did when it > was introduced. Well, then all the inventory is now worth 1/2 as much. > The result is a loss must appear on the financials. But, if we ship > all the parts before the prices erode, we do not have to write off anything. > > Peter and I also understand that small companies sometimes become big > companies. There are many examples of remarkably successful companies, > and many of them (most of them) use FPGA technology. > > How do we continue to support the "onsy-twosy" crowd while also > supporting the Nokia, Cisco, Huawei, Alcatel (etc) crowd? > > How do we keep customers happy? > > How do we provide the necessary engineering support? > > How do we make shareholders happy? > > Stay tuned.... > > AustinArticle: 115799
On Feb 21, 12:44 am, S Matthews <f...@cictec.com> wrote: > Wow, your chisel gets a workout. I have a Nexys-1000 which seems to > program correctly with an FX2 expansion board plugged in (using the > Digilent software with the onboard USB JTAG) - did you have JTAG > problems with the parallel cable or the onboard programmer (or both)? This was with the parallel cable that came with the old spartan 3 kit. IFIRC looking at the schematics that there's a gate which opens when the expansion board is plugged in, meaning you need to jumper it's tdi-tdo, which i didn't have set. Yes, chiselling it was stupid, but I'm unlikely to use the jtag out there anyway. > Your custom firmware and interface software sound really useful - do you > have a web site detailing your modifications? Not yet, will have to look back over what I did, how much is necessary and how much was just stuff that got put in there during debugging. I don't have a place to put it right now, considered contributing it back, but as that's a linux-oriented project I'm not sure how much they will like the windows compatability insertions (not that those should break the linux build - it seems more like linux libusb tolerating the violation of some this-before-that requirements which the windows version enforced). I'd also like to get it faster... mean to put a scope on it as see if I can figure out if the bottleneck is the USB proxifying of XC3Sprog, or the actual clock rate of the jtag output. Let me try to sort out some of what was important, and what was fluff.
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