Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Tim, We generally make one large device, which is "reticule limited." That has consistently been roughly the size you mention (~22 X ~24) for the last seven technologies. Going larger is not supported by most fabs, unless it is a special process (with special equipment). I once met someone from TRW, who told me they make imagers for the space program that are four times the X and Y dimensions of our largest die! His yield was one die per run of 25 wafers (if he was lucky). Of course, the imager sold for multi-hundreds of thousands of dollars. There is a real question that we always ask: "is it worth making the biggest part?" It seems the answer to this is never very clear. Are we doing this for our egos? Or, are we doing this because it is making money? We never really know where the "sweet spots" will be, as with every technology generation we also face a new set of designs by the customers. I am told that we are "caught up" with all 330 and 330T orders now. I hope my information matches that of our customers. AustinArticle: 116151
Hello, I'm having an instance being optimized away, although I'd like to keep the instance name hierarchy. I have "keep hierarchy" set to soft, because I'm utilizing some Chipscope ILA cores. The instance/block shows up fine in RTL viewer, but when I use Floorplanner after Translate, it's gone. I need to apply an AREA_GROUP constraint to it, so I can't easily do that w/o the correct instance name. Thx, -BrandonArticle: 116152
A long time ago we were bitten by this, and we added this to our
Makefile to check
that PAR met timing:
#
# Place and route the mapped netlist into the device
#
%_routed.ncd: %.ncd
par -w $(PAR_FLAGS) $< $@
@grep 'All constraints were met' $*_routed.par > /dev/null ||
false
Granted, it relies on Xilinx not changin the wording of the 'All
constraints...' line.
cheers,
aaron
On Mar 2, 8:56 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
> "Patrick Dubois" <prdub...@gmail.com> writes:
> >> This has just reminded me of something I discovered recently:
>
> >> Neither PAR nor TRCE return an error if the design fails timing, so
> >> any script/makefile which relies on the return code being non-zero as
> >> an error (like... well... just about anything sane!) will carry on
> >> through it's script as if everything is OK!
>
> >> You have to parse the PAR logfile for "No timing errors found" if you
> >> want to be sure.
>
> >> I have a change request in to fix this, please add your weight to the
> >> request (unless you think I'm bonkers for thinking that failing timing
> >> is an error!)
>
> >> Cheers,
> >> Martin
>
> > Very good point. I always try to remind new engineers here to always
> > remember to check the timing report part of the PAR log to make sure
> > that there are no timing errors. I'll try to open a webcase on the
> > issue. Do you have a CR number I can refer to?
>
> Not yet, I'll try and remember to post it here when I get it...
>
> Cheers,
> Martin
>
> --
> martin.j.thomp...@trw.com
> TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html
Article: 116153"Tim" <tim@nooospam.roockyloogic.com> wrote in message news:es5cod$952$1$8302bc10@news.demon.co.uk... > Symon wrote: >> I've looked for that after Teraspeed referenced it in an article and, >> like you, not found it yet. I was looking at something else the other day >> that had an elastomer with tiny wires in it <<snipped>> > > I'm pretty sure that general design has been around for 10+ years, and my > memory is that Samtec had an unsuccessful crack at productizing it some > time ago. It's about time they tried again! > > Here it is:- http://www.teraspeed.com/papers/connector%20launch%20optimization.pdf 'pariposer' Cheers, Syms.Article: 116154
Hey eascheiber, You can write your own bridge for this purpose. You know exactly what type of transfer the slave will accept. A stripped-down PLB master is quite easy to do (without Xilinx IPIF). Regards, MarcArticle: 116155
Awesome, thanks! I had originally tried to do this and it didn't work at the time.. just had to find a repository that had the package. Steve Luzerne wrote: > On 2 mar, 09:34, Steve Battazzo <thesteveman_i...@yahoo.co.jp> wrote: >> I've started playing around with this software a bit and when I tried to >> use floorplanner I got this error: >> >> error while loading shared libraries: libXm.so.3: cannot open shared >> object file: no such file or directory > > Open a terminal, and run this command : > $ sudo apt-get install libmotif3 > > This package contains the libXm.so.3 > > As explained in my french article, you may also require other lib that > can be installed by the following commands : > $ sudo apt-get install libxp6 > $ sudo apt-get install libcurl3 > > Luzerne GANHIR > > PS : with Ubuntu, an easy "GUI" way to find the package containing a > required library is to open > "synaptic" (System>Administration>Synaptic) and search for the name of > the lib. >Article: 116156
On Mar 2, 3:34 am, Steve Battazzo <thesteveman_i...@yahoo.co.jp> wrote: > Hello, guys... another question. > > I've started playing around with this software a bit and when I tried to > use floorplanner I got this error: > > error while loading shared libraries: libXm.so.3: cannot open shared > object file: no such file or directory > > Do I need to find this file and get it into the appropriate directory, > or is it there and I just need to point the program to it? > > Thanks, > > Steve You need the openMotif libraries installed. These were removed from Fedora due to being unfree in some fashion. I'm not sure if you can get them on Ubuntu. Also, I've tried Lesstif and it didn't work (crashed I believe). cheers, aaronArticle: 116157
On Mar 1, 7:03 am, Martin Thompson <martin.j.thomp...@trw.com> wrote: > "Patrick Dubois" <prdub...@gmail.com> writes: > > Hello, > > > I have been using batch files to handle the build process with a > > Xilinx flow for a while. Now I want to move to a more sophisticated > > approach to handle dependencies better. > > This has just reminded me of something I discovered recently: > > Neither PAR nor TRCE return an error if the design fails timing, so > any script/makefile which relies on the return code being non-zero as > an error (like... well... just about anything sane!) will carry on > through it's script as if everything is OK! > > You have to parse the PAR logfile for "No timing errors found" if you > want to be sure. > > I have a change request in to fix this, please add your weight to the > request (unless you think I'm bonkers for thinking that failing timing > is an error!) Failing timing is an error, but personally I don't want the tool to return an error code just because of timing errors: * I have seen people over-constraining designs. If par doesn't meet the over-constrained timing but meets the desired timing, I don't want my script to stop. * If I am in the lab debugging my design and want to quickly try out a few things, I don't want my script to stop just because one net failed timing by several ps. Cheers, Jim http://home.comcast.net/~jimwu88/tools/Article: 116158
Tim wrote: > Daniel S. wrote: > >> In any case, it sounds like quite a bit of trouble only to optimize >> tens of microwatts away from the bottom line. > > It has been 5 years since I did that sort of design, but at the > Spartan-2/2e generation the power savings were not microwatts - they > dominated power consumption on a 100MHz design. Could have been a design > wrinkle - my designs have been known to have wrinkles! > > It would be interesting to hear from Peter or Austin what the situation > is now - if ENA is deasserted, does BRAM power drop right down? This may > be answered in the User Guides - I'll get to read them one day... The user guide schematics and general description only scratch the surface. As I said, the schematic does look like ENA leaves the address decoder active but user specs are often only rough approximations of the actual hardware implementation's architecture, presented only to give the user an idea of what the thing is about. Having first-hand feedback about the scope of ENA's (near-)gate-level side-effects as a power-saving measure would certainly be ideal. Since I have some V2Pros here, I went to check if their datasheets had more concrete details but they turned out to be even more sparse. Maybe I will put together a dramatization of this case using four sets of 32BRAMs each (16k x 32bits with 16kx1 VS 512x32 BRAMs... and ENA VS clock gating, assuming this trick works with V2P) and see what happens.Article: 116159
I have one advantage: I can walk 50 steps and question the design engineer. And I did: The RAM Enable, when inactive, completely shuts down all dynamic RAM function, including the address registering and decoding. That leaves only the unavoidable leakage current. Note that WriteEnable, when inactive, keeps the address registering and decoding dynamically active, but only when the RAM is enabled. This is the best answer you could have expected. Hope it is clear now. Peter Alfke, Xilinx Applications On Mar 2, 10:59 am, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> wrote: > Tim wrote: > > Daniel S. wrote: > > >> In any case, it sounds like quite a bit of trouble only to optimize > >> tens of microwatts away from the bottom line. > > > It has been 5 years since I did that sort of design, but at the > > Spartan-2/2e generation the power savings were not microwatts - they > > dominated power consumption on a 100MHz design. Could have been a design > > wrinkle - my designs have been known to have wrinkles! > > > It would be interesting to hear from Peter or Austin what the situation > > is now - if ENA is deasserted, does BRAM power drop right down? This may > > be answered in the User Guides - I'll get to read them one day... > > The user guide schematics and general description only scratch the > surface. As I said, the schematic does look like ENA leaves the address > decoder active but user specs are often only rough approximations of the > actual hardware implementation's architecture, presented only to give > the user an idea of what the thing is about. Having first-hand feedback > about the scope of ENA's (near-)gate-level side-effects as a > power-saving measure would certainly be ideal. > > Since I have some V2Pros here, I went to check if their datasheets had > more concrete details but they turned out to be even more sparse. Maybe > I will put together a dramatization of this case using four sets of > 32BRAMs each (16k x 32bits with 16kx1 VS 512x32 BRAMs... and ENA VS > clock gating, assuming this trick works with V2P) and see what happens.Article: 116160
Mike Treseler wrote: > Daniel S. wrote: > >> Assigning a value to a signal from within a synchronous process will >> always infer FFs. Results with variables may vary wildly from one >> synthesis/simulation tool to another and how they get interpreted is >> also highly dependent on how the code is arranged. > > Synthesis results will match simulation. > Simulation will match the LRM. > Nothing varies wildly. > >> Using signals exclusively avoids introducing unnecessary confusion. > > As does using variables exclusively. > Some examples: > > http://home.comcast.net/~mike_treseler/ > > -- Mike Treseler The situation might have improved over the last 5+ years but from my experience in the ASIC field, "if it was broken five years ago, presume it is still broken today even if it has been fixed four years ago." When Modelsim gate-level disagrees with Cadence about what some bits of HDL does because either of them got confused by user-defined types, mixtures of signals and variables, etc., it turns into a costly and puzzling experience on the testbenches once A0 silicon comes around. Since I worked mostly with ASIC-minded people up to now, I was always asked to write the most plain, boring, simple and flat VHDL possible to avoid most language-feature-specific tool bugs elsewhere in the tool chain. When running gate-level netlist equivalence checks, there sometimes are startling discrepancies between what Cadence and Modelsim think of a particular design... this has been a major cause of dead ducks in the past and it still nearly scares the life out of the few people responsible for initial production sign-offs today.Article: 116161
Daniel S. wrote:
> Since I worked mostly with ASIC-minded people up to now, I was always
> asked to write the most plain, boring, simple and flat VHDL possible to
> avoid most language-feature-specific tool bugs elsewhere in the tool chain.
My comments were intended for FPGA designs
where VHDL source is still in the mainstream.
For some reason VHDL is depreciated for
ASIC designs in the USA.
-- Mike Treseler
Article: 116162On Mar 2, 11:59 am, "Brandon Jasionowski" <killerhe...@gmail.com> wrote: > Hello, > > I'm having an instance being optimized away, although I'd like to keep > the instance name hierarchy. I have "keep hierarchy" set to soft, > because I'm utilizing some Chipscope ILA cores. > > The instance/block shows up fine in RTL viewer, but when I use > Floorplanner after Translate, it's gone. I need to apply an AREA_GROUP > constraint to it, so I can't easily do that w/o the correct instance > name. > > Thx, > -Brandon FYI, I tried the keep_hierarchy in my .xcf, but that didn't help... It recognized the constraint tho: <SNIP from Synthesis Report> Set user-defined property "KEEP_HIERARCHY = true" for unit <my_entity_name>. </SNIP> It's really bothering me that the instance is maintained in the ngc, but not after Translate. What is going on exactly? Is there anything else I can do? Thanks.Article: 116163
hi every body ,
my problem is how to read a pixel for a picture (a pixel is composed
by three component Red, Green and Blue ) to get the three component.
this program is correct into syntax but i m not sure for the result
please help me , i m a beginner and i m not sure with the result that
gives me
--------------------------------------------------------------------------------------------------------------------------------------------------------------
entity lecteur_pixel is
Port ( clk : in STD_LOGIC;
composante : in STD_LOGIC_VECTOR (7 downto 0);
R : out STD_LOGIC_VECTOR (7 downto 0);
G : out STD_LOGIC_VECTOR (7 downto 0);
B : out STD_LOGIC_VECTOR (7 downto 0));
end lecteur_pixel;
architecture architecture_lecteur of lecteur_pixel is
signal count: STD_LOGIC_VECTOR (1 downto 0):="00";
--a meter that allows counting the number of clock top and decide the
composing to read
begin
-- To the first clock top one reads the composing R, to the 2ND one
reads G and to the third one reads B
process(clk)
begin
if clk='1' and clk'event then
count <= count + 1;
R <= composante when count ="01";
G <= composante when count ="10";
B <= composante when count ="11";
end if;
end process;
end architecture_lecteur;
-----------------------------------------------------------------------------------------------------------------------------------------------------
thank you
Article: 116164On Mar 2, 4:01 pm, "VHDL_HELP" <abai...@gmail.com> wrote: > hi every body , > my problem is how to read a pixel for a picture (a pixel is composed > by three component Red, Green and Blue ) to get the three component. > this program is correct into syntax but i m not sure for the result > please help me , i m a beginner and i m not sure with the result that > gives me > -------------------------------------------------------------------------------------------------------------------------------------------------------------- > entity lecteur_pixel is > Port ( clk : in STD_LOGIC; > composante : in STD_LOGIC_VECTOR (7 downto 0); > R : out STD_LOGIC_VECTOR (7 downto 0); > G : out STD_LOGIC_VECTOR (7 downto 0); > B : out STD_LOGIC_VECTOR (7 downto 0)); > end lecteur_pixel; > > architecture architecture_lecteur of lecteur_pixel is > signal count: STD_LOGIC_VECTOR (1 downto 0):="00"; > --a meter that allows counting the number of clock top and decide the > composing to read > > begin > -- To the first clock top one reads the composing R, to the 2ND one > reads G and to the third one reads B > process(clk) > begin > if clk='1' and clk'event then > count <= count + 1; > R <= composante when count ="01"; > G <= composante when count ="10"; > B <= composante when count ="11"; > > end if; > end process; > end architecture_lecteur; > ----------------------------------------------------------------------------------------------------------------------------------------------------- > thank you Your process should have a reset to put your FFs in a known state. I'd also use rising_edge(clk).Article: 116165
Greetings:
A previous poster,
http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/950f94cb6c98fd24/49a6e05e25f70edd?lnk=st&q=fpga+salvage&rnum=2#49a6e05e25f70edd
wrote:
> I showed my homebrew club how to reball and attach Xilinx BG560's
> here in my wifes digital convection oven well over a year ago. It takes
> a small amount of practice, which gets manageable when you also are
> willing to bake and reball. There are lots of trash FPGA's to be had on
> boards for a few dollars, and Solderquik preforms make reballing easy.
A list of consumer, industrial and mil. products, board names and part
numbers that contain reprogrammable array logic devices would be very
useful; this list could specify device type and part number,
programming technique and technology (ISP, JTAG, EEPROM, SRAM,
vendor programmer, etc.), package type, and comments. I'll kick it off
with a somewhat obscure board (was in quantity on eBay at one time):
VENDOR PART NUMBER DEVICE PROGRAMMING PACKAGE COMMENTS
------ ----------- ------ ----------- ------- --------
Waters PCB 510000150 Rev.B Altera EPM7064LC44-12 Vendor Prog. 44-pin plcc Medical related
EEPROM
Additions are much appreciated!
Regards,
Michael
msg _at_ cybertheque _dot_ org
Article: 116166
Hi,
We released an Embedded SATA Storage appnote (XAPP716) and reference
system last year. I recommend you to take a look at it. Basically it is an
embedded Linux system with SATA and Gigabit Ethernet connection targetting
ML405 demoboard. It is true there were some SATA support issues with V4 MGT
in particular the OOB detector. However it has been addressed in the design.
The release provides a time-limited evaluation bitfile for anyone with a
ML405 to try out. This release does not support SATA Gen2 (3Gbps) mainly
because we did not have time to implement. V5 GTP has improved and
functional OOB support. It works fine in SATA Gen1/2 in my testcase. Feel
free to ask if you need more info.
Regards,
Simon
<sam@catalpatechnology.com> wrote in message
news:1170955032.802747.211060@h3g2000cwc.googlegroups.com...
> I've read some of the heated discussions regarding Virtex 4 and SATA,
> but I'm still not sure what the answers are. My understanding is that
> with a modest amount of external circuitry (NOT an external phy) I can
> build a SATA interface. Some of the Xilinx answer database links
> regarding SATA are dead. Hopefully someone here can give me some
> pointers.
>
> 1) What about V4 fails to work for SATA?
> 2) Has anyone made it work, and willing to explain how it was done?
> 3) Can 3Gbps speeds be used?
> 4) Is there another programable device that would be easier (V5 still
> needs to age a bit).
>
> Thanks
>
> Sam
>
Article: 116167Hi every one, I see the Virtex 5 DLL has a DRP port however I can't find the register description to change it's configuration dynamically. For the virtex 4 that was in the "configuration guide", but looking at the equivalent guide for the virtex 5 I see no document describing the PLL DRP registers ... Does any one has info about this ? Thanks, SylvainArticle: 116168
Weng Tianxiang wrote: > Hi, > What is the running frequency for a typical FPGA application using > Virtex 5? > > A friend of mine told me long ago that we could expect to get 1/10 > running frequency of the fastest CPU for a fastest FPGA in market. > > Now the fastest CPU runs at 4GHz, can a FPGA application using the > fastest FPGA chip be expected to run at 400MHz, 1/10 of fastest CPU? > Is Virtex 5 the fastest FPGA so far? > > For example, DDR2 runs at 333MHz, can a DDR2 application core run > normally at 333MHz without any trouble such that there is no need to > reduce application core running frequency to meet 333MHz challenge? If > so for Virtex 5, it can be claimed that 333MHz is achievable. > > 1/10 ratio between the fastest CPU and the fastest FPGA chip running > frequencies is a reasonable expectation or not? > > Thank you. > > Weng > I expect V5 can be run at 400MHz with careful design fairly easily. It is faster than Virtex4, and I have successfully completed non-trivial V4 designs that run at 400 MHz. Issue 3 of the Xilinx DSP magazine, which should be coming out very soon, has an article in it about a 1.2 GSample/sec Floating point FFT design I did in it. The FFT engines in that design are clocked at 400MHz. The device is a Virtex4 SX55 -11. Clock rate around 1/10 of fastest CPU seems reasonable, but it will generally take an experienced FPGA designer to achieve that.Article: 116169
And make sure you have the synthesis tool NOT put in IO buffers. I do this quite often when evalutating the resource utilization of lower-level modules. JTW "Jim Wu" <jimwu88NOOOSPAM@yahoo.com> wrote in message news:1172021076.848945.277970@q2g2000cwa.googlegroups.com... > On Feb 19, 8:00 pm, "Aaron" <weiro...@gmail.com> wrote: >> Hi all, >> >> I want to evaluate the area and time cost of an intermediate product >> on Xilinx FPGA. But the number of >> output ports exceed number of I/O pins. (Actually there will be much >> less outputs in the final product. ) >> >> But currently, I need test the intermediate product by using Xilinx >> ISE. Can I add some ISE specific declaration to avoid the fully IO >> mapping while I can still get the area and time cost reports? >> >> Thanks a lot. >> >> Sincerely, >> Aaron > > Theoretically (i.e. I have never tried this. sorry ;)) you can use > "map -u" (do not remove unused logic) with "TPSYNC" and/or "TPTHRU" > contraints. > > Cheers, > Jim > http://home.comcast.net/~jimwu88/tools/ > >Article: 116170
msg wrote:
> A list of consumer, industrial and mil. products, board names and part
> numbers that contain reprogrammable array logic devices would be very
> useful...
A revised list:
VENDOR PART NUMBER DEVICE PROGRAMMING PACKAGE COMMENTS
------ ----------- ------ ----------- ------- --------
Waters PCB 510000150 Rev.B Altera EPM7064LC44-12 Vendor Prog. 44-pin PLCC Medical related
EEPROM
Compaq SP#136344-001 Remote Xilinx xc9572xl JTAG 100-pin TQFP Under daugherter bd
Insight Board
Matrox 706-02 Rev. A Video Xilinx xc5204 Ser/Par/Jtag 144-pin TQFP p/o MIL2/RRSTN VGA
Capture daughter bd.
Radius VideoVision Studio Lattice pLSI1032-80LJ Programmer 84-pin PLCC Mac Video Capture
NuBus 632-0156-02 EEPROM
Additions sought.
Regards,
Michael
Article: 116171I am using these programs in my digital class but do not know how to link modelsim to ISE. In our school lab, after I make my schematic, I can run model sim to simulate it from inside ISE. Does someone know how I would set this up?Article: 116172
On Mar 2, 4:43 pm, msg <msg@_cybertheque.org_> wrote: > A list of consumer, industrial and mil. products, board names and part > numbers that contain reprogrammable array logic devices would be very > useful; While I can appreciate the spirit of what you are trying to do... I don't see it as being too practical. With parts of interesting density, the cost of coming up with a board to put them on is going to be greater than the cost of buying a few of them from the likes of digikey... and then, for a one off, the true economics are going to suggest turning an eval board into your device. Recycling programmable logic doesn't make a lot of sense to me, unless perhaps you find a way to use it on the board it's already on, perhaps to improve the original device... that, could indeed be fun.Article: 116173
any IP vendor out there who supply hard/soft core for V.34 Modem?Article: 116174
Brandon Jasionowski wrote: > It's really bothering me that the instance is maintained in the ngc, > but not after Translate. What is going on exactly? Is there anything > else I can do? Unused logic is not removed until translate or par (can't remember now). In the schematic view even those things show up that get optimized away later. If your instance is not there after translate/map, then it was probably removed completely for some reason. Maybe because it was never used, produces only constant outputs or something. -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z