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"Sylvain Munaut" <tnt-at-246tNt-dot-com@youknowwhattodo.com> wrote in message news:45F81941.2030603@youknowwhattodo.com... > >> To clear the memory you either need to write every address or keep a >> separate bunch of registers as tags for each entry to label them as "not >> updated" in which case the value should be forced zero when read (at >> which >> time the flag is cleared). Some people call these "dirty bits" to keep >> track of which entries provides clean data and which don't. >> >> People who do fancy code can even have dirty bit registers to track a >> dirty >> bit memory array for those larger memory tasks. >> >> The basic idea is: >> >> Clear: Set all dirty bits. >> Read: value <= Dirty[addr] ? 0 : yourMem[addr]; Dirty[addr] <= 0; > > Well, I would only clear the dirty bits on writes ... > Or if it's bram, you must force wren to 1 and write 0x00...00 at the same > address you read to clear it. > > > Sylvain Thanks for the clarification - my mistake. You have things right, indeed.Article: 116651
"VHDL_HELP" <abaidik@gmail.com> wrote in message news:1173890111.962169.307570@e65g2000hsc.googlegroups.com... > On 14 mar, 13:44, "Dave Pollum" <vze24...@verizon.net> wrote: >> >> As John_H pointed out, taille only needs to be 2 bits. In other >> words: >> taille : in STD_LOGIC_VECTOR (1 downto 0); >> >> As for your simulation problem, your test bench needs to supply the >> values to be loaded into your signal "s". Otherwise, you will see X >> for dout. >> >> -Dave Pollum > > i dont know it still the same problem So, tell us please: what does your simulation say the values of s(0), s(1), s(2), and s(3) are? Troubleshooting involves breaking the problem down into smaller pieces, seeing if you can show the smaller pieces work or don't work. If you have a smaller piece that works, you can now ignore it and only need to concentrate on the smaller piece that doesn't work. You can cut that up into smaller pieces and isolate what works there.Article: 116652
On 14 Mar 2007 17:17:03 GMT, Colin Paul Gloster <Colin_Paul_Gloster@ACM.org> wrote: > >[..] any time that you form a combinatorial loop you have to be >concerned about how this will get implemented. A combinatorial loop >happens when you have multiple equations, none of which inherently >shows any feedback but taken together the whole set does. [..] > >[..]" > >Perhaps an unfortunate homonym of "combinatorial" has been used: do >people use "combinatorial" in this way? Most definitely, yes. > A circuit which is described >as "combinatorial" or its "combinational" in literature is one which >does not have an output of its as an input of its, unlike a >"sequential" (not in the VHDL sense) circuit. No-one was calling the *circuit* combinational; it's the *loop* that Kevin was so describing. In doing so he was conforming to long-established usage in the synthesis community for the description of any cycle in the network that is not broken by an explicit storage element. Of course, if you concern yourself with asynchronous state machines of any kind then you expect to deal with such cycles and you no longer speak of "combinational" circuits. But in the purely synchronous world of mainstream design, every storage element should have its synchronous inputs fed by the output of a purely combinational circuit. In such a context it is neither unreasonable nor ambiguous to use "combinational loop" to describe a specific and pernicious kind of design error. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 116653
On 14 Mar 2007 17:21:12 GMT, Colin Paul Gloster <Colin_Paul_Gloster@ACM.org> wrote: >A latch is a type of flip-flop. Please desist from nitpicking. Ralf's meaning was entirely self-evident. Common usage being what it is, when describing any kind of bistable element (not "flip-flop" please) that is *not* an edge-triggered D-type flip-flop, it is necessary to qualify the phrase "flip-flop" with something such as "S-R flip-flop". There is a tiresomely large lexicon of names for the different flavours of bistable element: bistable multivibrator flip-flop latch register Eccles-Jordan relay Save for the last one, I can easily find examples of multiple and overlapping meanings of all these. To disambiguate them we must rely either on tiresome and wordy qualification of each usage, or intelligent inference from context. Only the most irritatingly pedantic would insist on such blindness to context as your comment exhibits. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 116654
On Mar 14, 1:17 pm, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> wrote: > Perhaps an unfortunate homonym of "combinatorial" has been used: do > people use "combinatorial" in this way? A circuit which is described > as "combinatorial" or its "combinational" in literature is one which > does not have an output of its as an input of its, unlike a > "sequential" (not in the VHDL sense) circuit. If something is 'combinatorial' it does not imply anything about how it is used (i.e. whether or not the output is fed back to one of the inputs). As far as whether this combinatorial feedback gets used or not in designs...absolutely. Depending on just what you're designing you're either very aware of it or it is something happening behind the scenes. To the person designing the flip flops that go into the FPGA, you bet that they are very aware of the combinatorial feedback loop that they are in fact designing and it's characteristics. To the person writing code that will eventually get downloaded into that exact same FPGA, probably not...even though they should be aware of this (from the standpoint of avoiding ever creating such a thing in their own designs). Kevin JenningsArticle: 116655
On Mar 13, 8:34 pm, "Bob Golenda" <bgoli...@nospam.net> wrote: > Has anyone had any success in programming a Xilinx XCF using C code in a > MicroBlaze over the JTAG ports? Not exactly, but some closely related things, such as programming FPGA and config flashes whose JTAG signals have been connected to GPIO pins of ordinary (hardware) microcontrollers. I don't think you'll be able to program the config flash by driving the FPGA's jtag pins, so you would need some seperate connections from ordinary I/O pins. Once your microblaze can twiddle the config flash's jtag signals, you have a software problem. My preferences has been to make the embedded device behave like a jtag cable with some macro commands and act as a proxy for a program running on a PC. You could of course embed the whole thing, but that means putting the algorithm and the data into the embedded processor. Your microblaze system may have the resources for that, my embedded targets don't, so I use a much smaller block of code that acts as a proxy.Article: 116656
How do I get rid of bit latch type warnings compiling with Xilinx ISE
when I am assigning a value to part of a bit vector type signal in the
if/case structure e.g. below the code gives FRAME_STATUS bit latch
errors
if data_present=1 then
FRAME_STATUS(8)<='0';
FRAME_STATUS(7)<=OVR_FLOW;
FRAME_STATUS(6)<=FRAME_GOOD;
FRAME_STATUS(5)<=FRAME_BAD;
FRAME_STATUS(4 downto 0)<="00000";
end if;
I have tried the following and it does not work.
if data_present=1 then
FRAME_STATUS(8)<='0';
FRAME_STATUS(7)<=OVR_FLOW;
FRAME_STATUS(6)<=FRAME_GOOD;
FRAME_STATUS(5)<=FRAME_BAD;
FRAME_STATUS(4 downto 0)<="00000";
else
FRAME_STATUS<=FRAME_STATUS;
end if;
and the following
if data_present=1 then
FRAME_STATUS(8)<='0';
FRAME_STATUS(7)<=OVR_FLOW;
FRAME_STATUS(6)<=FRAME_GOOD;
FRAME_STATUS(5)<=FRAME_BAD;
FRAME_STATUS(4 downto 0)<="00000";
else
FRAME_STATUS<="00000000";
end if;
P.S Please ignore the previous posting as it was sent incomplete
Article: 116657<maurizio.gencarelli@dsto.defence.gov.au> wrote in message news:1173912290.382427.249070@p15g2000hsd.googlegroups.com... > How do I get rid of bit latch warnings when I compile my code in ISE > when I am assigning values to parts of bit vector type signals ? > > e.g > > > > if PROG_FULL<='0' then > > TEMP_DATA(8)<=FRAME_MRK; > TEMP_DATA(7 downto 0)<=DATA_IN; > TEMP_DATA(8)<=FRAME_MRK; > > else > > OVR_FLOW<='1'; > WREN<='0'; > > end if; What do you want from TEMP_DATA when NOT PROG_FULL<='0' ? If you no longer care about TEMP_DATA, you can assign it a zero value. Alternatively (I believe) you can set TEMP_DATA to a zero value before the clocked block such that only the PROG_FULL<='0' condition will update the value. This is a common method in Verilog which may or may not translate over to VHDL.Article: 116658
On 2007-03-14, John McCaskill <junkmail@fastertechnology.com> wrote: > What are some of the tricks you do with the xdl netlist? Does it give > you a way to take a core through map and PAR and then use it as a > block box in a design that is going to go through map/PAR again? > One thing I've tried is to take a place and routed design and then insert another core that peeked on some internal signals in the first design. Think chipscope but using RS232 instead of JTAG for communicating with the outside world. The flow I used basically looks like this: * Synthesize, map, and place and route your design to design.xdl * Synthesize and map the rs232 based logic analyzer to analyzer.xdl * Manually edit analyzer.xdl to remove stuff you are not interested in * Manually merge analyzer.xdl into design.xdl * convert xdl file to ncd and rerun par on it with exact guidemode * Optional: Correct mistakes that xdl and par complained about :) So it is not very streamlined I'm afraid :) But streamlining the process is really only a matter of writing a perl script. I haven't tried this on any large design either so I don't know if there are any gotchas... Anyway, I would guess that there are quite a few possibilities here for someone with a lot of time on their hands. Another use of XDL which is less radical is to extract information about the design. For a report I wrote some time ago I wrote an XDL to Postscript converter in order to avoid bitmap graphic of a floorplan :) And the xdlanalyze.pl script which I've mentioned on comp.arch.fpga earlier. > I have been wanting to harden some cores that I use in all my EDK > designs, does this help any? I already have several cores that I pull > in as black boxes and put area group constraints on. It would be nice > to take those cores through PAR, and bring an already placed net list > in as a block box. As you've probably guessed by now I'm afraid that my experimentation have not really been aimed at this... although I would be interested in knowing about such a solution as well. /AndreasArticle: 116659
On 2007-03-15, Andreas Ehliar <ehliar@lysator.liu.se> wrote: > * Synthesize, map, and place and route your design to design.xdl > > * Synthesize and map the rs232 based logic analyzer to analyzer.xdl > > * Manually edit analyzer.xdl to remove stuff you are not interested in > > * Manually merge analyzer.xdl into design.xdl I forgot to include an important part here: * Manually merge the constraints in design.pcf and analyze.pcf /AndreasArticle: 116660
Uncle Noah wrote: > Hi > > i'm outraged! Those guys from the X* company STOPPED DELIVERING > printed manuals with their boards!!!! > > This is not right. For $149 plus international shipping rates, I > demand a printed manual as well!!! > > What is your opinion? Does this happen for all (after mid 2006) Xilinx > boards? It could be worse: on top of not having printed manuals, the $300 XUP-V2P comes without software. Since ISE WebPack does not support the XC2VP30, anyone buying one of those boards is screwed unless they have access to a full copy of ISE+EDK or other suitable synthesis tools through some side/back-channel. I am still puzzled that Xilinx happily subsidizes $1300 to put these boards into future logic engineers' hands and into universities' labs but makes accessing the necessary tools so impractical. I heard even Xilinx's sales reps are surprised when they hear about this situation for the first few times. IMO, missing software easily tops a 'missing' printed manual. Like others here have said, I prefer the searchable digital format. If I find myself repeatedly referring to specific sections (like schematics), I can print them as necessary and any way I want... from two pages per side duplex on 8.5x11 for plain text to 11x17 for schematics.Article: 116661
<maurizio.gencarelli@dsto.defence.gov.au> wrote in message
news:1173913124.682142.163060@e1g2000hsg.googlegroups.com...
> How do I get rid of bit latch type warnings compiling with Xilinx ISE
> when I am assigning a value to part of a bit vector type signal in the
> if/case structure
The latch is created when there is some path through the code that does not
result in an assignment to the signal. In your cases, you have
if data_present = 1 then....
Well if data_present is not 1 then there is no assignment to FRAME_STATUS in
the first example, in the second example you did explicitly assign
FRAME_STATUS but you assigned it to hold it's current state which is exactly
the same thing as not having an assignment at all (therefore resulting in a
latch). Your last example should not produce a latch since if data_present
is not equal to 1 then you go down a path where it looks like you are trying
to assign all the bits of FRAME_STATUS to 0 (although it looks like you
missed a bit since FRAME_STATUS appears to be 9 bits wide and you've only
got 8 zeros in your string.
The way to get rid of the latches is to make them flip flops so your process
would be something like this instead
process(Clock)
begin
if rising_edge(Clock) then
-- Pasting your code from your first example here
> if data_present=1 then
>
> FRAME_STATUS(8)<='0';
> FRAME_STATUS(7)<=OVR_FLOW;
> FRAME_STATUS(6)<=FRAME_GOOD;
> FRAME_STATUS(5)<=FRAME_BAD;
> FRAME_STATUS(4 downto 0)<="00000";
> end if;
end if;
end process;
KJ
Article: 116662John is of course right. Memories have no global or parallel clear. Such a clear would require an extra input to every data storage cell, plus a wire interconnecting these inputs. Too expensive and too slow in the highly competitive high-density RAM market. Peter Alfke, Xilinx On Mar 14, 8:33 am, "John_H" <newsgr...@johnhandwork.com> wrote: > "Yrjola" <yrj...@op.pl> wrote in message > > news:et8ugq$uaq$1@node4.news.atman.pl... > > > Hi, I have set of registers implemented as internal RAM blocks (in Cyclone > > FPGA). Is there any way to clear contents of this registers on demand > > (just like clear signal in D flip-flops)? > > > For answers thanks in advance. > > Just like flops? Absolutely not. > > No memories come with resets. Not DDR SDRAMs, not SRAMs, not BlockRAMs, not > distributed CLB SelectRAMs, not TriMatrix Memory. > > To clear the memory you either need to write every address or keep a > separate bunch of registers as tags for each entry to label them as "not > updated" in which case the value should be forced zero when read (at which > time the flag is cleared). Some people call these "dirty bits" to keep > track of which entries provides clean data and which don't. > > People who do fancy code can even have dirty bit registers to track a dirty > bit memory array for those larger memory tasks. > > The basic idea is: > > Clear: Set all dirty bits. > Read: value <= Dirty[addr] ? 0 : yourMem[addr]; Dirty[addr] <= 0; > > - John_HArticle: 116663
On Mar 14, 7:36 pm, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > On 2007-03-15, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > > > * Synthesize, map, and place and route your design to design.xdl > > > * Synthesize and map the rs232 based logic analyzer to analyzer.xdl > > > * Manually edit analyzer.xdl to remove stuff you are not interested in > > > * Manually merge analyzer.xdl into design.xdl > > I forgot to include an important part here: > * Manually merge the constraints in design.pcf and analyze.pcf > > /Andreas Do you know if there is a way to get an xdl netlist back to an ngc netlist? What I would like to do is to take some of my IO cores that I use on all of my designs and take them through PAR until I am happy with the results and then be able to use them as hard macros from then on. Regards, John McCaskill www.fastertechnology.comArticle: 116664
Now that all silly disclaimers have been thoroughly eradicated, come and sign up for X-Fest in a city near you. Whether you are in the U.S. or Canada, in Europe or Isreal, in Asia or Australia or New Zealand,j there is an X-Fest near you. These are technical seminars with an absolute minimum of Marketing. I have been working on the keynote address, and many of our applications engineers have created the detailed presentations. I am sure you will learn something that helps you with your next design. You can google: "Avnet X-Fest 2007" to get to the sign-up page. Peter AlfkeArticle: 116665
I am currently working on an old board which have eight FPGA XC3130 on board and i dont have a source code for those FPGA's except for .bit file which was downloaded through VME bus. Currently i am redesigning the board eliminating all the PAL's on the board with high end FPGA and also want to incorporate the obsolescence XC3130 into them.But i dont have a source code except for .BIT (Bitstream)file. Is there any software which could convert the .bit file to VHDL/ Verilog?or even a functional block? Any alternative suggestions to go ahead with this board redesign ? Thank you NaveenArticle: 116666
On 2007-03-15, John McCaskill <junkmail@fastertechnology.com> wrote: > Do you know if there is a way to get an xdl netlist back to an ngc > netlist? Not that I know of. Well, you can use netgen to convert a .ncd design to vhdl or verilog and it might be possible to synthesize this one. However it would not contain routing information. > What I would like to do is to take some of my IO cores that I use on > all of my designs and take them through PAR until I am happy with the > results and then be able to use them as hard macros from then on. I've found conflicting information about routing in hard macros, some says the routing cannot be locked down like the following: http://www.cse.ucsc.edu/classes/cmpe225/Fall01/hardmacro.html And some say that it is possible, such as a hard bus macro that is used in partial reconfiguration. Perhaps you could download such a bus macro and see how they are constructed? Mind you, I haven't tried this at all so I have no idea if it is a good idea or not, but perhaps you could synthesize your I/O macros one after one and place the result in one large XDL file which you could then convert to NCD and use as a guide file for par. It is a quite ugly solution though, there must be a better way. But if you find an easy way to create such hard macros I'd be interested as well :) /AndreasArticle: 116667
lingamaneni.naveen@gmail.com wrote: > Is there any software which could convert the .bit file to VHDL/ > Verilog?or even a functional block? With or without comments? -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 116668
"Mark McDougall" <markm@vl.com.au> wrote in message news:45f8eb7a$0$8364$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > lingamaneni.naveen@gmail.com wrote: > >> Is there any software which could convert the .bit file to VHDL/ >> Verilog?or even a functional block? > > With or without comments? LOL. Reverse engineering is generally very difficult, but it could perhaps be possible to extract the netlist, i.e. the low-level connections between the individual registers, LUTs, etc. Not that I have the skill/time/knowledge, but perhaps someone else has already done something similar. Whether that is of any use for the OP is unknown to me. -Michael.Article: 116669
Hi, I'm working on a Virtex4 DDR2 interface based on the direct clocking design from MIG 1.6 (XAPP701). I'm clocking the DDR2 (Micron 1Gb) at 125MHz, so I would expect to see only one edge of DQS during calibration using the IDELAY. However, from chipscope I see two edges only approx 900ps apart. I notice there are lots of IDELAY queries on here... can anyone explain what is going on? The design uses an IDELAYCTRL clocked at 200MHz from a DCM CLKFX with a 50MHz clkin. The result is intermittant read errors, I suspect since the calibrated data delay is totally wrong... Many thanks, RobArticle: 116670
On Wed, 14 Mar 2007 09:24:38 -0700, Austin Lesea <austin@xilinx.com> wrote: >Often the reason for someone enforcing their "right to privacy" has to >do with them being caught by a spouse doing something they would rather >not have been caught doing. "I will be in London at the conference all >week" and there they are, at the dinner event, with a glass of wine it >their hands, and with their arm around someone not their spouse... > >Austin Or worst yet: "Honey, I'm going to off with my mistress for the day" , and then getting caught on film sitting at an X-Fest, studiously taking notes, surrounded in a sea of engineers!Article: 116671
hai, i am vishnu i have some doubt regarding verilog coding,i want to have 5 secs delay ,as delays are not synthesziable i have used counter, but my problem is i want to use that counter inside an always block,i have tried using events but that too are not synthesizable,i hope u can solve my problemArticle: 116672
<ravipativishnu@yahoo.co.in> wrote in message news:1173950673.894498.244900@y80g2000hsf.googlegroups.com... > hai, i am vishnu i have some doubt regarding verilog coding,i want to > have 5 secs delay ,as delays are not synthesziable i have used > counter, That's the way to do it. > but my problem is i want to use that counter inside an always > block i have tried using events but that too are not synthesizable,i > hope u can solve my problem You already solved it...use a counter. If putting the counter indisde an 'always block' causes you grief then don't do it Kevin JenningsArticle: 116673
> Reverse engineering is generally very difficult, but it could perhaps be > possible to extract the netlist, i.e. the low-level connections between the > individual registers, LUTs, etc. Not that I have the skill/time/knowledge, > but perhaps someone else has already done something similar. Oh. That would be *nasty*. JBArticle: 116674
> Has anyone had any success in programming a Xilinx XCF using C code in a > MicroBlaze over the JTAG ports? You can do the following: - Use IMPACT and record the JTAG programming sequence to an XSVF file. - Read XAPP058 and XAPP503 to learn about the XSVF file specification. - Implement an XSVF player using C code in a Microblaze. - Play the recorded JTAG programming sequence in your board. Using the batch mode of IMPACT, you can script this from your makefile. Regards, Marc
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