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Do you want to have conenction EMAC-SGMII-ext. Phy? Then its best to use CoreGen TemacWrapper v4.3/v4.3. You'll get a complete design here.Article: 116726
Thanks, I've try the tipps from Gabor, 1. It helps to improve the timing performence, to pack the output register into IOBs. 2. About the reset signal, i don't understand. But as Frai said, i should pay more attention to it. 3. Play with different IOSTANDARD is another way to improve the "clock to output". Here is the Data Sheet from XILINX about different IOSTANDARD, also about slow/fast slew-rate. :http://www.xilinx.com/ bvdocs/publications/ds302.pdf However, it seem to be that, I got to the end of this device XILINX Virtex-4 XC4VLX60 (It is speed grad -10, not -12). The following is the post-par static timing report from XILINX ISE. ========================================== Slack: -3.039 ns (requirement - (clock arrival + clock path + data path + uncertainty)) ------------------------------------------------------------------------------ Clock delay: Tiopi 0.938 // Input buffer net (fanout=1) 0.928 Tbgcko_O 0.900 net (fanout=534) 3.009 // Because i have a lot of registers clocked by this clock Total 5.775ns (1.838ns logic, 3.937ns route) (31.8% logic, 68.2% route) ------------------------------------------------------------------------------------ Data Delay: Tockq 0.584 net (fanout=1) 0.050 Tioop 3.630 // Output buffer Total 4.264ns (4.214ns logic, 0.050ns route) (98.8% logic, 1.2% route) =========================================== I think i have to re-design the code. What do you think? Thanks ChengArticle: 116727
Bonjour, My name is Julien Lochen, I work as FPGA Design Engineer in France. My question is about the init of FPGA's RAMs. In my design, some data are stored in a block-RAM. I need to init each byte stored in the block-RAM, but THE INIT VALUE ARE NOT THE SAME. To do this, I use the constraint file, in which I use the following keyword : "INIT_00 = 256'h ... INIT_01 = 256'h ... ... INIT_3F = 256'h ..." The block-RAM is mapped as follow : 256 lines of 1 byte. The question is : If I want to init only the five first addresses to "1", and the rest of the block-RAM to zero, am I correct if I write : "INIT_00 = 256'h0000000000000000000000000000000000000000000000000000FFFFFFFFFFFF; INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; ... INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;" regards, JulienArticle: 116728
Hi, i have used a parallel cable to download bitfile into my Virtex 4 FPGA. But when open Chipscope with this cable, the computer said it can't found the cable. Do anybody know how to solve this? thanks.Article: 116729
Hi Manfred, you should keep the project_assignments_defaults.qdf along with the cdf, qpf, qsf(s), eco, dpf and qws. I recommend backing up and archiving the other extensions just in case. The eco is used for logging operations done by the resource properrty editor and the dpf is used by the pin planner. The project_assignments_defaults.qdf is kept so that idf defaults change between releases, the set of defaults shipped with the version of Quartus when the project was first created, continue to be used for that project. Hope this helps, Subroto Datta Altera Corp. "Manfred Balik" <manfred.balik@tuwien.ac.at> wrote in message news:45fa62c3$0$11094$3b214f66@tunews.univie.ac.at... >I have to work again on an old project started 2004 with Quartus v3.0. Now >I'm working with the actual v6.1. > There are a lot of files in the project-directory :-((( therefore I want > to clean up now. > > does someone know, if the files with this extensions are necessary or old > ones: > project.csf > project.dpf > project.eco > project.esf > project.fld > project.psf > project.ssf > project_assignment_defaults.qdf > > I think, I only need: > project.cdf > project.qpf > project.qsf > project.qws > > Is this right? I don't want to erase files, and recognize in a few month > that they were necessary! > > Thanks, Manfred > > > >Article: 116730
Hi all, Thanks a lot guys for the response. I am currently changing the plb_ddr controller by removing the plb side interface and integrating the ddr interface into my code. D On Mar 13, 3:05 am, birla.man...@gmail.com wrote: > On Mar 11, 1:44 am,dhruvaks...@gmail.com wrote: > > > How can I get a ddr sdram controller for the MT46V16M16TG -75 micron > > chip. > > I want a controller without the plb or opb interface. I tried open > > cores.org but it says that the repository is empty with no files > > pertaining to the ddrsdram controller core. > > Could someone give me right pointers? > > Thanks, > > D. > > You might want to have a look at Xilinx website itself. Its not very > high performance, but gives a good heads up.Article: 116731
Hi, I have a input clock "i_clk_main", in my VHDL code, i divide this clk with factor 2, that means "clk_int" has the half frequenz as "i_clk_main", and i use "clk_int" to clock the output register. Now, i must in the constraint file define, how much ns delays the output relative to "clk_int" may maximal have. What should i do? The following is the error report fomr ISE. Checking timing specifications ... ERROR:XdmHelpers:634 - Signal "clk_int" is used as the clock in specification "OFFSET=OUT 7000 pS AFTER clk_int HIGH", but this clock signal is not connected directly to a pad. An OFFSET specification must use a pad signal to designate the clock. Thanks, and have a nice weekend ChengArticle: 116732
This is an interesting and frustrating issue that I have. I recently bought Modelsim MXE from xilinx. I generated a multiplier v9_0 core using corefie and am trying to compile it using modelsim but it gives me an error saying " Internal error : ../../vcom/genexpr.c" Core generator did give me the following status mesages -- Exception (null) getting Customizer GUI for component (com.xilinx.ip.mult_gen_v9_0.mult_gen_v9_0) Generating Implementation files. Generating the VHDL wrapper. Generating the VHDL instantiation template. Generating NGC file. Finished Generating. Successfully generated multiplier_v9_0. There is no such file called genexpr.c on my system. The other cores work fine. Thanks, DArticle: 116733
On 14 mar, 18:43, "John_H" <newsgr...@johnhandwork.com> wrote:
> "VHDL_HELP" <abai...@gmail.com> wrote in message
>
> news:1173890111.962169.307570@e65g2000hsc.googlegroups.com...
>
> > On 14 mar, 13:44, "Dave Pollum" <vze24...@verizon.net> wrote:
>
> >> As John_H pointed out, taille only needs to be 2 bits. In other
> >> words:
> >> taille : in STD_LOGIC_VECTOR (1 downto 0);
>
> >> As for your simulation problem, your test bench needs to supply the
> >> values to be loaded into your signal "s". Otherwise, you will see X
> >> for dout.
>
> >> -Dave Pollum
>
> > i dont know it still the same problem
>
> So, tell us please: what does your simulation say the values of s(0), s(1=
),
> s(2), and s(3) are?
>
> Troubleshooting involves breaking the problem down into smaller pieces,
> seeing if you can show the smaller pieces work or don't work. If you hav=
e a
> smaller piece that works, you can now ignore it and only need to concentr=
ate
> on the smaller piece that doesn't work. You can cut that up into smaller
> pieces and isolate what works there.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity somme is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
en : in STD_LOGIC_VECTOR (3 downto 0);
clk_out : out STD_LOGIC;
s : out STD_LOGIC_VECTOR (3 downto 0));
end somme;
architecture Behavioral of somme is
TYPE tab is array(3 downto 0) of std_logic_vector(3 downto 0);
begin
process
VARIABLE t:tab;
begin
SEQ_LOOP: loop
wait until clk'event and clk =3D '1';-- Lecture de premier =E9l=E9ment
du tableau 4 =E9l=E9ments
exit SEQ_LOOP when reset =3D '1';
clk_out <=3D '1';
wait until clk'event and clk =3D '1';
exit SEQ_LOOP when reset =3D '1';
t(0) :=3D en;
wait until clk'event and clk =3D '1';-- Lecture de deuxi=E8me
=E9l=E9ment du tableau 4 =E9l=E9ments
exit SEQ_LOOP when reset =3D '1';
clk_out <=3D '0';
wait until clk'event and clk =3D '1';
exit SEQ_LOOP when reset =3D '1';
t(1) :=3D en;
wait until clk'event and clk =3D '1';-- Lecture de troisi=E8me =E9l=E9m=
ent
du tableau 4 =E9l=E9ments
exit SEQ_LOOP when reset =3D '1';
clk_out <=3D '1';
wait until clk'event and clk =3D '1';
exit SEQ_LOOP when reset =3D '1';
t(2) :=3D en;
wait until clk'event and clk =3D '1';-- Lecture de quatri=E8me =E9l=E9m=
ent
du tableau 4 =E9l=E9ments
exit SEQ_LOOP when reset =3D '1';
clk_out <=3D '0';
wait until clk'event and clk =3D '1';
exit SEQ_LOOP when reset =3D '1';
t(3) :=3D en;
end loop;
s <=3D t(0) + t(1) + t(2) + t(3);
end process;
end Behavioral;
---------------------------------------------------------------------------=
---------------------------------------------------------------------------=
--------------------------------------------------------------
this is my problem:
for the s(0) , s(1) , s(2) and s(3) it gives me the numbers but for s
in simulation i have as a result 4'hU and 4'hX
Article: 116734Hi, I have a system with 2 PowerPCs connected to the same PLB. Each PPC has a ISOCM connected memory mapped at around 0xffff_ffff. I download the bitfile with bootloop programs, then I open XMD, download program for PPC0 and PPC1 in an SDRAM at different address ranges. Run PPC 0 then 1 and everything works fine. However; I want to get rid of the ISOCM and when I do that the system stops working. I tried the same hardware but don't download the bootloop, doesn't work, tried mapping 0xffff_ffff in the SDRAM use bootloop, doesn't work. Any suggestions? Regards, eArticle: 116735
On Mar 16, 10:07 am, "Bob Golenda" <bgoli...@nospam.net> wrote: > Ah, OK. Unfortunately, we care about: > > 1) how big the code it self is...so it fits in the XCF > 2) how big the data is, as it has to fit in available memory > 3) programming speed > > So, it doesn't seem like the XSVF player solution will work for us. Why not drip feed it? Run the XSVF player on a PC, with access to the data file, and use your embedded target as a glorified programmer cable? When you say you need speed, how fast do your need to be? Is two minutes okay? That's what I'm getting for a fairly large Altera part using the equivelent method.Article: 116736
Hi Julien,
For synthesis with Synplify, I initialize memories as shown below . The
text files contain the memory contents, one memory location per line.
Barry Brown
// for Synplify ram inference
reg [9:0] RdAddr_reg;
reg [17:0] mem1 [0:1023]/* synthesis syn_ramstyle="no_rw_check" */;
reg [17:0] mem2 [0:1023]/* synthesis syn_ramstyle="no_rw_check" */;
initial begin // ROM values stored in these files
$readmemh("Stage1_Ram1.txt", mem1);
$readmemh("Stage1_Ram2.txt", mem2);
end
// >>>>>>>>>>>>>>>> HARDWARE DESCRIPTION BEGINS HERE >>>>>>>>>>>>>>>>>
// >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
// This code causes Synplify to infer dual port block RAMs.
// >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
always @(posedge WrClk)
begin : DP_BRAM
if (WrEn[1])
mem1[WrAddr] <= WrData;
if (WrEn[2])
mem2[WrAddr] <= WrData;
end // DP_BRAM
always @(posedge RdClk)
begin : BRAM_reg
RdAddr_reg <= RdAddr;
end // BRAM_reg
assign RdData1 = mem1[RdAddr_reg];
assign RdData2 = mem2[RdAddr_reg];
Stage1_Ram1.txt :
00002
00007
00010
0001C
0002C
00040
00057
00072
00090
000B2
000D8
00101
0012E
0015F
00193
etc.
<lochen@noos.fr> wrote in message
news:1174052135.850473.202520@d57g2000hsg.googlegroups.com...
> Bonjour,
>
> My name is Julien Lochen, I work as FPGA Design Engineer in France.
>
> My question is about the init of FPGA's RAMs.
>
> In my design, some data are stored in a block-RAM.
>
> I need to init each byte stored in the block-RAM, but THE INIT VALUE
> ARE NOT THE SAME.
>
> To do this, I use the constraint file, in which I use the following
> keyword :
>
> "INIT_00 = 256'h ...
> INIT_01 = 256'h ...
> ...
> INIT_3F = 256'h ..."
>
> The block-RAM is mapped as follow : 256 lines of 1 byte.
>
> The question is :
>
> If I want to init only the five first addresses to "1", and the rest
> of the block-RAM to zero, am I correct if I write :
> "INIT_00 =
> 256'h0000000000000000000000000000000000000000000000000000FFFFFFFFFFFF;
> INIT_01 =
> 256'h0000000000000000000000000000000000000000000000000000000000000000;
> ...
> INIT_3F =
> 256'h0000000000000000000000000000000000000000000000000000000000000000;"
>
> regards, Julien
>
Article: 116737> > This is using XSVFPlayer? How many M Bytes is the file? Don't you have > > to > > actually do an output of the file and record that, and then use > > XSVFPlayer? > > > > We don't really care much about how big is the file as it gets downloaded > from an external server when needed and the whole purpose of this is a rare > in-field hardware upgrade. Ah, OK. Unfortunately, we care about: 1) how big the code it self is...so it fits in the XCF 2) how big the data is, as it has to fit in available memory 3) programming speed So, it doesn't seem like the XSVF player solution will work for us. That's why I asked about straight JTAG programming, which it seems like no one has actually done and gotten working. Thanks!Article: 116738
"VHDL_HELP" <abaidik@gmail.com> wrote in message news:1174054292.325732.224840@y80g2000hsf.googlegroups.com... <snip> > ----------------------------- > this is my problem: > for the s(0) , s(1) , s(2) and s(3) it gives me the numbers but for s > in simulation i have as a result 4'hU and 4'hX If by s( ) you mean t( ) and all the t values are numbers according to your simulation and your resulting sum is 4'hU and 4'hX according to your simulation, it sounds like your simulator is broken. VHDL gurus: is there *anything* that might go wrong with the addition given the libraries he has specified?Article: 116739
It looks like you have what you need if you ignore the fact that there are 12 F digits in your string rather than five 1s or five FFs. The question is where do you want to apply the INITs? The INITs work fine in the .ucf file. If you want them in your source code, you have to instantiate the BlockRAM primitive. Is that what you've done? In Verilog, I prefer to use the inline parameters rather than synthesis attributes or defparam values. One of these three methods will need to be used to attach the INITs properly to the instantiated BlockRAM. Which do you prefer? If you're inferring your memory, look to your synthesizer's reference for initialization. An initial block will work for some synthesizers and Barry Brown pointed out how Synplify likes to handle file-based memory initialization for Verilog. - John_H <lochen@noos.fr> wrote in message news:1174052135.850473.202520@d57g2000hsg.googlegroups.com... > Bonjour, > > My name is Julien Lochen, I work as FPGA Design Engineer in France. > > My question is about the init of FPGA's RAMs. > > In my design, some data are stored in a block-RAM. > > I need to init each byte stored in the block-RAM, but THE INIT VALUE > ARE NOT THE SAME. > > To do this, I use the constraint file, in which I use the following > keyword : > > "INIT_00 = 256'h ... > INIT_01 = 256'h ... > ... > INIT_3F = 256'h ..." > > The block-RAM is mapped as follow : 256 lines of 1 byte. > > The question is : > > If I want to init only the five first addresses to "1", and the rest > of the block-RAM to zero, am I correct if I write : > "INIT_00 = > 256'h0000000000000000000000000000000000000000000000000000FFFFFFFFFFFF; > INIT_01 = > 256'h0000000000000000000000000000000000000000000000000000000000000000; > ... > INIT_3F = > 256'h0000000000000000000000000000000000000000000000000000000000000000;" > > regards, Julien >Article: 116740
Xilinx gurus out there, I have a very very simple design with a 24 bit counter, and I am using bit 24 in an always block like this always @(posedge cnt[23]) Xilinx is telling me that it didnt automatically insert a clock buffer, and that it thinks this is a clock. I then added // synthesis attribute BUFFER_TYPE of cnt[23] is bufgp to my verilog and to a .xcf file (that I specified as synthesis constraints file in synthesis properties). However synthesis is still reporting that cnt[23] is a clock and the buffer type is NONE and that I need to specify buffer_type for if I want it to insert a buffer. What am I doing wrong? Based on what I read about synthesis attributes, they can just go inline with the verilog, but it doenst seem to be getting picked up. Any ideas? Thanks, -JArticle: 116741
On Fri, 16 Mar 2007 08:14:18 -0700, "John_H"
<newsgroup@johnhandwork.com> wrote:
>"VHDL_HELP" <abaidik@gmail.com> wrote in message
>news:1174054292.325732.224840@y80g2000hsf.googlegroups.com...
><snip>
>> -----------------------------
>> this is my problem:
>> for the s(0) , s(1) , s(2) and s(3) it gives me the numbers but for s
>> in simulation i have as a result 4'hU and 4'hX
>
>is there *anything* that might go wrong with the addition given
>the libraries he has specified?
Don't think so (although my dislike of STD_LOGIC_UNSIGNED
is well enough known by now).
The problem is simpler: SEQ_LOOP is an infinite loop
containing an implicit state machine. The loop exits
only when reset is asserted. If reset is held false, the
loop continues to iterate and the final assignment
is never executed, so 's' is never updated.
Could we please find the tutor (or book writer, or other
"authority") who is teaching beginners to use this
form of implicit state machine, and string him/her
up by a rope tied around some sensitive appendage?
It makes my blood boil so much that I'm willing to post
the (obvious, simple) code that works - assuming
the use of NUMERIC_STD instead of STD_LOGIC_ARITH:
process (clk, reset)
subtype T_chiffre is unsigned(3 downto 0);
type T_tableau4x4 is array (0 to 3) of T_chiffre;
variable lieu: unsigned(1 downto 0);
variable t: T_tableau4x4;
variable somme: T_chiffre;
begin
if reset = '1' then
-- remettre tout à zero
lieu := "00";
t := (others => (others => '0'));
clk_out <= '0';
s <= (others => '0');
elsif rising_edge(clk) then
-- faire le somme en ajoutant chaque numero memorisé
somme := (others => '0');
for i in t'range loop
somme := somme + t(i);
end loop;
-- mettre le somme en mémoire "s"
s <= somme;
-- sauvegarder le numéro prochain
t(to_unsigned(lieu)) := en;
-- ??? horloge /2 ???
clk_out <= not lieu(0);
-- préparer pour boucle prochain
lieu := lieu + 1;
end if;
end process;
Beware of arithmetic overflow. Output gives the sum of the
most recently seen 4 values. I have no idea why you want
clk_out.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 116742> That's > why I asked about straight JTAG programming, which it seems like no one > has > actually done and gotten working. Read again Antti's reply. He has done it. /MikhailArticle: 116743
> > Ah, OK. Unfortunately, we care about: > > > > 1) how big the code it self is...so it fits in the XCF > > 2) how big the data is, as it has to fit in available memory > > 3) programming speed > > > > So, it doesn't seem like the XSVF player solution will work for us. > > Why not drip feed it? Run the XSVF player on a PC, with access to the > data file, and use your embedded target as a glorified programmer > cable? That may be possible in some situations, but not this. The software that talks to the board is dedicated (and embedded), and the programming needs to be self contained. > When you say you need speed, how fast do your need to be? > > Is two minutes okay? That's what I'm getting for a fairly large > Altera part using the equivelent method. That would be fine, but the speed depends on a lot of things. Now, you are programming an Altera...I specifically asked about Xilinx XCF...Article: 116744
> Read again Antti's reply. He has done it. I read that he ported XCF player. When he said his first time was about a month, it's unclear exactly what it is he did, and how it operated. I will ask him off-line. But, let's say he has done it...has anyone else? So far, it appears not, and that doing it is no trivial task.Article: 116745
On Mar 16, 11:31 am, "Bob Golenda" <bgoli...@nospam.net> wrote: > > > Why not drip feed it? Run the XSVF player on a PC, with access to the > > data file, and use your embedded target as a glorified programmer > > cable? > > That may be possible in some situations, but not this. The software that > talks to the board is dedicated (and embedded), and the programming needs to > be self contained. And how is the new bit or XSVF file going to get into this "self contained" device to start with? Download? Flash Card? How? Answer that question and you are on the path to solving your problem. > > Is two minutes okay? That's what I'm getting for a fairly large > > Altera part using the equivelent method. > > That would be fine, but the speed depends on a lot of things. Now, you are > programming an Altera...I specifically asked about Xilinx XCF... Speed depends mostly on the size of the part and the efficiency of the implementation - for comparison, this is about 4x slower than the USB blaster doing the same job. You haven't specified how big your bitstream is, anyway. (I haven't told you how big mine is because I'm not exactly sure - the pof file is about 500k, but the jam file is only about 300k... I'm not really sure how big the actual prom image is)Article: 116746
John, I have not worked with partitions and can not offer any assistance there, but I did see a similar Answer Record (AR) that called out the same error in MAP. Check out AR23369: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=23369 I can not say if the environment variable change will help, but it is something to try. As the design is proprietary, is there a way you can create a non-proprietary design that exihibits the same error for the FAE? This is the best way for the SW developers to fix the bug / get a workaround to you. -David "johnp" <johnp3+nospam@probo.com> wrote in message news:1174000707.039560.139610@n59g2000hsh.googlegroups.com... > I've tired using the Xilinx 'partition' feature several times now with > very mixed/negative results. > > I tried partions again today with the 9.1.2 s/w and it dies with an > unhelpful message: > > DeleteInterpProc called with active evals > > This application has requested the Runtime to terminate it in an > unusual way. > Please contact the application's support team for more > information. > > Process "Place & Route" failed > > My FAE tells me Xilinx wants the HDL source to help resolve this > problem - this > can't happen since a chunk of it is highly proprietary. > > a) has anyone else seen this and found a work-around? > b) has anyone had a positive experience with partitions? > > Please don't suggest trying SmartGuide - it has it's own set of > problems > with this design. > > John Providenza >Article: 116747
Thanks for all the postings. On unix, impact created a _impact.cmd file when I ran it through the gui. I the copied the file to a new name gen_mcs.cmd and added an "exit" command at the end and ran on batch mode as "impact -batch gen_mcs.cmd". It worked fine. -DipankarArticle: 116748
Ken Soon wrote: > Hi, > I have a design that is implemented on the Virtex4 and it consumes 69 > FIFO16/RAMB16s. I hope to be able to implement it on a Spartan 3E evaluation > board but clearly, it is not enough as the 3E only has 36Block rams > My evaluation board has 4 DDR SDRAM of 512MBit, can I use those instead of > the insufficient block rams? > > Cheers, > Ken It depends on how much bandwidth you need and whether or not you can spare the logic for the necessary memory controller. I am working on a high-performance memory controller of my own to interface a PC3200 DDR DIMM to an XC2VP30 that can sustain anywhere from 100% read to 100% write and my preliminary data says this is pretty expensive: my final memory controller will consume about 40 BRAMs out of 136. About half of the BRAM cost comes from the quad x36 internal memory ring bus controllers' FIFOs and most of the other half comes from the dual-ported back-end's 128bits wide FIFOs. This design is overkill for a VP30 but I am currently unemployed so I am simply killing time by doing something that may be useful later - or at the very least instructive since I have never interfaced DRAMs directly before. If your DRAMs provide you only a 32bits-wide data bus and you can operate your internal data path at twice the DDR clock, things get much simpler and smaller. A 0 BRAM memory controller would be possible under these conditions... but I'd still slap on a BRAM FIFO or three (local RX, local TX, pass-through) with extra logic to 'ringify' it if more than one or two function blocks are going to share access.Article: 116749
Hello Cheng, I have just tried your design here. 6ns from inside clock to outside of the chip is not huge. If you want to go high up in frequency, you have two choices: - the fpga (when writing to the outside) needs to provide the clock alonside the data. This is done for instance by running the fpga at twice the frequency then dividing this clock in the IOB by two and this forms the clock you provide to the outside world. But in your case twice as much might be a pain. This way your system is said 'source synchronous'. - if your system is 'system synchronous' i.e. an external clock is fed to your fpga and the other chips it interfaces with, then what you can do is use a dcm inside the fpga and use clk270 to 'advance the clock (1/4Tcycle). This will help the fpga-writes case but make sure it doesn't break the fpga-read (you can do the math: 1/4Tcycle in your case is 2ns). I hope this helps, jb
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