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On 19 Mrz., 13:42, Joseph Samson <jsam...@the-company-name.com> wrote: > Yes, the default is LVCMOS25. I always specify the IOSTANDARD, but I > usually don't use LVCMOS25. Thanks! Did you get that information from the documentation? I did not find it when I tried. BTW: Is there a way to add a CONFIG STEPPING directive to the generated .ucf file from a .xbd file? Anyone? ;-) Greetings, TorstenArticle: 116826
On 19 Mar, 15:15, cs_post...@hotmail.com wrote:
> So you were able to get some unix make utility and GCC to process the
> included makefile for the jam player?
>
Not exactly
First, if you get the original jp_25.exe
(https://www.altera.com/support/software/download/programming/jam/dnl-
player.jsp)
, you need to unpack it with "unzip -LL jp_25.exe" - to get lowercase
filenames.
Then I convert all the DOS end-of-lines into U**X ones:
$for i in *; do dos2unix $i ; done
Then you have to convert the makefile.mak:
All ".obj" you should replace with ".o"
You should also change two compilation rules:
==============================================
.c.obj :
cl /W4 /c /O2 /ML /DWINNT $<
# LINK: add appropriate linker command here
jam.exe : $(OBJS)
link $(OBJS) advapi32.lib /out:jam.exe
==============================================
Should be replaced with:
==============================================
.c.o :
gcc -c $*.c -O2
# LINK: add appropriate linker command here
jam.exe : $(OBJS)
gcc -o jam.exe $(OBJS)
==============================================
Finally you should set port to UNIX in jamport.h:
/* change this line to build a different port */
#define PORT UNIX
And make some corrections in jamstub.c:
You should comment out:
#include <io.h>
#include <process.h>
#include <conio.h>
Now it should compile (but YOU SHOULD ADJUST THE I/O ROUTINES!)
> I couldn't get the combination of GNU make (cygwin win32) and GCC
> (cygwin win32) to do so (a bunch of wierd errors about circular
> definitions) which is what prompted my question.
The above description was tested on GCC+Linux. I don't know if it will
work
for GCC+Cygwin :-(.
--
HTH & Regards,
Wojtek
Article: 116827On Mar 16, 11:28 pm, "Ulsk" <a...@ljs.com> wrote: > I noticed XST 9.1 still doesn't support multi-dim arrays in an always @* > block. > Here's a (perhaps poor) example: > > reg signed [15:0] table [0:255]; > reg signed [23:0] sum; > > integer i; > always @* > begin > sum = 0; > for ( i =0; i < 256; i = i + 1 ) > sum = sum + table[i]; // yes, I know this will synthesize a suboptimal > imbalanced adder-tree! > end Ulsk, I've heard that this is a "grey" area of the Verilog standard. It shouldn't be at all - the intended behavior is quite clear in your example, and the tools should do the correct thing. Unfortunetly XST doesn't get it right yet. Xilinx promised to fix this is ISE9.x. Now, they've put it off again until 10.x. We've used VERY similar constructs - except we used SystemVerilog packed arrays, instead of your verilog-2001 "unpacked" array equivalent. This has worked fine for us in ASIC and FPGA flows. It works with VCS, modelsim, dc_shell, and Precision. Of course, you'll need to use the "Systemverilog" switch of the tools - which Xilinx doesn't have yet either. For your example in SystemVerilog, just change the table definition to: reg signed [ 255 : 0 ] [ 15 : 0 ] table; And it would work. I'm thinking in the IEEE Std 1800-2005 (SystemVerilog IEEE standard), they may have cleaned this up, and you're original example would work. --MarkArticle: 116828
Torsten Landschoff wrote: > On 19 Mrz., 13:42, Joseph Samson <jsam...@the-company-name.com> wrote: > >>Yes, the default is LVCMOS25. I always specify the IOSTANDARD, but I >>usually don't use LVCMOS25. > > > Thanks! Did you get that information from the documentation? I did not > find it when I tried. Just from experience. --- Joe Samson Pixel VelocityArticle: 116829
John_H wrote: > The one condition I recall having to pay attention to the signal > polarity in general logic - where it can affect timing - is when going > in to a carry chain as a direct input to the MUXCY primitive. I can > infer an add or subtract fine, but sometimes a needed inversion results > in an extra LUT of delay before coming onto the carry chain because the > .DI (or MULT_AND) inputs can't absorb the input. Often it's just a > matter of producing an inverted form of the registers that feed the > logic; this is sometimes referred to as "not gate push-back" if it's > handled for you by the synthesizer. > > - John_H I believe that particular "feature" has been addressed in the V5 carry chain structure so that now you have a LUT-like programmability in place of the former MULT_AND primitive on the MUXCY DI input. Yes, this particular thing has been the source of many not-so-obvious work-arounds to avoid having a non-absorbable inverter messing up the timing closure.Article: 116830
I'll put a post up. It will probably go out on our newsletter as well. We are very overdue for a newsletter. John Adair Enterpoint Ltd. On 19 Mar, 12:46, Thomas Glanzmann <sithg...@stud.uni-erlangen.de> wrote: > Hello John, > > > I hope we will also be finally showing the DDR2 and SDRAM modules for > > Raggedstone1 this week or maybe next. They have been assembled and > > awaiting test for those interested in these. Proving there are not any > > issues they they will be on sale shortly after. > > Michael Gernoth and I am very interested in this. Can you give us a > heads up when the modules are available? > > ThomasArticle: 116831
On Mar 18, 4:47 pm, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> wrote: > I might have some reps' contact info jotted down on a note somewhere from many months ago > but I have no idea where that note is now. If your prof is involved in Xilinx-sponsored > research projects or anything else of the sort, he should have some equivalent contacts of > his own. I have worked on post-doc projects (telecom/DSP) as an intern and back then, > Xilinx was quite happy to sponsor projects that pushed the frontier of FPGA-based > applications... they most likely still do today. Okay, thanks again. I'll check with my prof, see what he says. (Being new to this group (and never really having used the USENET much) I was curious to see that my original thread was no longer around. Until I realized that it could be hijacked with a simple change of the Subject line! I added the new topic to my original subject line)Article: 116832
Your are right about the pound/dollar exchange rate but to a degree it works 2 ways as we buy a lot of components that are referenced to a dollar pricing so some of our cost base reduces with the current high rate. To a much smaller extent we have the same thing for the euro. I think even at the current rate we are still competitive which isn't too bad as we build all of the development boards in the UK not exactly known for low cost labour. We just have to be more inventive on how we do things and we do have a high hit rate on first time right boards. I won't say which but a number of our current boards are basically the same boards as came back as initial prototypes for the team to test. It some cases we cosmetically changed minor details like silkscreen and up-revisioned them. As of today I believe we have only ever had one return and it wasn't faulty which is probably better than our competitors. All of that together makes good economics. John Adair Enterpoint Ltd. On 18 Mar, 19:57, "Rivas" <odof...@yahoo.com> wrote: > John, > Thanks for your response. As Daniel mentions, Xilinx subsidizes their > silicon so that Digilent can offer the board at a very low price (when > considering the value of just the FPGA). The XUP is $300 for > educational purposes. It's a *much* larger FPGA (2x the PPC cpu's, > nearly an order of magnitude larger in slices and BRAM) than the > Virtex II-Pro I worked with. No slouch. Not *the* bleeding edge nor a > good idea for new commercial designs but it looks good to learn on. > I'll check out your site, although the $/pound exchange is unfavorable > for British products in the US right now. > > Daniel, > Thank you, that is exactly what I needed to know to make the XUP board > worth considering. The prof I took the class with does tons with > Xilinx products so I'll ask him if he has Xilinx rep contacts. You > don't happen to have a rep's contact info, do you? > > Accdg to the digilent site, it seemed to allow me to get all the way > to credit card # entry in the check-out process with a $300 invoice > for the XUP. Do you think I still need an acct with Digilent? I'm > eager to buy, but I'll wait to see if I can network to the Xilinx > folks. > > Another Digilent alternative for $300 is the FX12 board:https://www.digilentinc.com/Products/Detail.cfm?Prod=FX12&Nav1=Produc... > > Not as feature rich and I don't see much in the way of app notes or > reference designs. It does have gigabit ethernet. > > -Ed > > On Mar 18, 12:27 pm, "Daniel S." > > > > <digitalmastrmind_no_s...@hotmail.com> wrote:> > > Hi, > > > I got a pair of these XUPs when I took my last undergrad digital system design class. > > Sure, the V2P is not the newest or greatest chip around and falls short in a few areas but > > the board is otherwise fairly well-rounded for the price... even more so when you consider > > that the board costs $300 even though the FPGA on it is listed at around $800 - these > > boards are heavily subsidized by Xilinx. > > > Before you order this board, you need someone from your university to setup an account > > with Digilent before you can buy those subsidized boards. After that, you need someone to > > contact a Xilinx sales rep. to ask for the necessary software to support those boards. > > Since the company my teacher back then works at is a major Xilinx account in the area, we > > had no problem setting up the Digilent account and getting Xilinx's authorization for > > copies of ISE/EDK DVDs and keys. The story says the Xilinx sales rep. was surprised to > > hear that no software came with those boards. > > > Your mileage may vary, so delay your order until you have secured both the tools and valid > > keys should you decide to try going XUP.- Hide quoted text - > > - Show quoted text -Article: 116833
I'm trying to install the alliance toolset <http://www-asim.lip6.fr/recherche/alliance/> on an Ubuntu linux machine. I've downloaded both a tarball and RPM sources. The site says to see the README to install the tarball, but there is no README. The RPM sources won't build because there is no libiberty.so. Anyone know where there are either instructions for installing the binaries or source for libiberty?Article: 116834
Daniel S. wrote: >> >> Xilinx BRAMs do initialize in a known state on FPGA configuration. >> The memory can be set to specific contents, or will default to all zero. > > > True, but device reprogramming happens only once at power-up unless > triggered by other means afterwards. Since the OP was about clearing > memory "on-demand", none of those power-up-specific details are relevant > though. Right, I realize that. I made this comment because someone brought up the power-up state of commodity memories.Article: 116835
On Mar 16, 9:04 pm, "Patrick Dubois" <prdub...@gmail.com> wrote: > Hi, > > I'm about to buy a new workstation for FPGA development and I'm > hesitating between a Core 2 Extreme @ 2.93 GHz (X6800) and the new > quad-core @ 2.66 GHz (QX6700). The price difference is 100$. > > Does Xilinx have any roadmap for multi-core CPU support in the future? > I'd hate to buy a dual-core CPU just to learn that ISE v10.1 features > quad-core support... > > If there is no multi-core support planned for the foreseeable future, > I'll probably buy the dual-core CPU because it's slightly faster than > the quad-core one. I'm going to work on a Virtex 4 FX100 soon so I'll > need all the horsepower I can get for the P&R runs... > > Patrick Hi Patrick, If you're into doing some script-buildning yourself, it is possible to speed up builds by quite alot by hand-coding a build-file for the Synthesis-part, but maybe your problem is the P&R and that is probably another story. I posted something on it here. http://tech.groups.yahoo.com/group/s3_kit/message/123 If I remember correctly the initial Build time was about 6-7 minutes. I've mostly done Verilog in ISE but just now I'm attending a VHDL- course at a university and they use Altera's QuartusII tools. They also include Multi-CPU-support and at least it is possible to select how many of your CPU's that will be used from QuartusII. Can anyone comfirm this? Is the SMP-support in Alteras QuartusII better that the non-existant in Xilinx ISE? My project has been so small so I can't measure any difference! :-)Article: 116836
Hi Marc, Thanks for the info. But, it sounds to me like you "play" the XSVF file, using your own code/interpreter instead of porting the Xilinx XSVFPlayer, and you don't actually do the JTAG protocol your self? Not a problem, that's one way to skin this cat...but I'm just trying to understand the relationship between what you did and having a true JTAG programmer that just uses .mcs files. Thanks! <jetmarc@hotmail.com> wrote in message news:1174296634.687631.196780@n76g2000hsh.googlegroups.com... > Hi Bob, > > Yes, I've actually done this and it works. > > I didn't use or port the XSVF Player, because when I didn't know about > it until I had half of my code finished already. I based my code on > the XSVF file description in XAPP503. I found it is sufficient to > program an XCF08P chip, but not for a V4FX FPGA. The FPGA XSVF file > uses some states not covered in XAPP503. They are covered in the > source code of XAPP058 and actually they are not difficult to guess > either. > > For what it's worth: The XSVF is about the same size as the (ASCII) > MCS file. It's binary but contains lots of redundant patterns. > Unfortunately the XCF08P erase time is very slow, because it's > implemented as simple delay. The XCF08P datasheet documents how to > poll the erase state, so it's possible to "replace" the delay with a > poll function on-the-fly in your XSVF interpreter code. > > In theory you can't stream an XSVF file because the byte order of some > commands require you to access the last byte first. The command size > can be any 32-bit integer, so effectively this puts an unknown memory > size requirement on your embedded stream buffer. It can be as large > as the whole file size. In practice however, I never observed > commands larger than 768 bytes produced by Impact as XSVF generator. > To be on the safe side, my code interprets the XSVF on the Windows PC, > and produces a stream of proprietary command tokens. This stream is > sent to an 8-bit MCU on my target board to produce the actual JTAG > patterns. > > To produce the XSVF file with Impact (batch mode), I found the most > simple solution is to load a working project file with all chips > already configured. This reduces the size of the batch command file > to less than 10 lines. > > I hope this helps, > Marc >Article: 116837
Weng,
If Ax is of type std_logic, you only has 2 very trivial cases to
cover. Using multipliers would be a gigantic waste of FPGA
resources... since you have no "non-trivial" cases to concern
yourself with, you have a much simpler option than multipliers.
Personally, I don't think students should be given answers from a
message board, so that's as much of a hint as I am personally willing
to give you (sorry, the problem is trivial enough to be a quite
obvious homework assignment) But, think about what I said and why
your 2 cases are very trivial....
-Paul
P.S. - It's actually trivial enough that a decent synthesizer would
not synthesize multipliers if you did it that way anyway.... at least
it shouldn't.
On Mar 16, 10:02 pm, "Weng Tianxiang" <wtx...@gmail.com> wrote:
> Hi,
> What official functions should I call to genertate a sum of products
> in VHDL?
>
> S(...) <= A0*B0(...) + A1*B1(...) + A2*B2(...) + ... + An*Bn(...);
>
> Ax is a type of std_logic or bool; Bx() is a type of std_logic_vector
> or unsigned.
>
> I use the following two libraries:
> USE ieee.std_logic_1164.all;
> use ieee.numeric_std.all;
>
> Thank you.
>
> Weng
Article: 116838hi all i am an engineering final year student in english i am doing a project on "CONFIGURING FPGA USING XC9500 CPLD AND PARALLEL PROM" i am staring frm the scratch i studied some literature... but i am not understanding the following things * how to create bitstream * how to create configuration file * how to load bitstream how to use and what is the role of vhdl in this application.. plz helpArticle: 116839
On Mar 18, 2:03 pm, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> wrote: > If you can postpone this purchase for a few more months, I suggest you wait and get a C2D > E6850 when they are released: these will be much less expensive (266 USD) yet a bit faster > (3GHz with 1333MHz FSB) than the X6800. Thanks for the suggestion, I was not aware of the E6850. Quite a price difference indeed! Unfortunately I can't really wait very long. Too bad that the E6850 is still a few months away...Article: 116840
On Mar 19, 2:53 pm, "spartan3wiz" <magnus.wedm...@gmail.com> wrote: > If you're into doing some script-buildning yourself, it is possible to > speed up builds by quite alot by hand-coding a build-file for the > Synthesis-part, Yep, I did that already. I have about 10 different modules at the moment, each synthesized with a separate batch file. > but maybe your problem is the P&R and that is probably > another story. I posted something on it here.http://tech.groups.yahoo.com/group/s3_kit/message/123 > If I remember correctly the initial Build time was about 6-7 minutes. Yes, the P&R is my problem. It's especially frustrating when all you're doing is changing a few Chipscope signals and you have to go through the whole P&R from scratch.Article: 116841
Take a look at this old discussion: http://tinyurl.com/277l9a /MikhailArticle: 116842
"jd" <jaggunitj@yahoo.co.uk> wrote in message news:1174332556.604594.212410@d57g2000hsg.googlegroups.com... > hi all > > i am an engineering final year student in english > i am doing a project on "CONFIGURING FPGA USING XC9500 CPLD AND > PARALLEL PROM" > i am staring frm the scratch > i studied some literature... > but i am not understanding the following things > > * how to create bitstream Use the Xilinx tools for an FPGA design to produce the .bit file in the "Generate Programming File" step in the Xilinx ISE GUI. > * how to create configuration file "Generate PROM, ACE, or JTAG file" (under "Generate Programming File" in the GUI) to launch and use the Xilinx Impact utility. > * how to load bitstream Read the "Configuration" section in the data sheet for the part you're going to program. > how to use and what is the role of vhdl in this application.. You need to learn how to use VHDL on your own. "how to use assembly language" might be an equivalent question. It's the language used to describe the functionality of the part. As far as the role: you can use VHDL to describe the functionality of your CPLD and to design the FPGA that you'll be generating the bitstream for. > plz help Do you know anything about VHDL? If you're taking this on as a project, you should have certain prerequisites, one of which is certainly the use of RTL languages in hardware design.Article: 116843
On Mon, 19 Mar 2007 12:39:11 -0700, Patrick Dubois wrote: > On Mar 18, 2:03 pm, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> > wrote: >> If you can postpone this purchase for a few more months, I suggest you >> wait and get a C2D E6850 when they are released: these will be much >> less expensive (266 USD) yet a bit faster (3GHz with 1333MHz FSB) than >> the X6800. > > Thanks for the suggestion, I was not aware of the E6850. Quite a price > difference indeed! Unfortunately I can't really wait very long. Too bad > that the E6850 is still a few months away... The E6700 has a lot of headroom, I'm running mine overclocked to 3GHz using the stock Intel cooler and 4G of DDR2 800 RAM slightly underclocked to 750MHz (the RAM speed is set to 667 in the BIOS, the core clock is at 300 instead of 266 which gives you 752). I'm running the system 24/7 doing NC Verilog simulations and Xilinx place and routes. It's been up since Dec without any problems.Article: 116844
On Mar 19, 4:41 pm, "Bob Golenda" <bgoli...@nospam.net> wrote: > Thank you very much for that pointer. It still appears that aside from what > Antti did, no one (at least on this list) has successfully done a real JTAG > programmer for the XCF...just XSVF Player type programmers. I just find > that odd. I don't find it odd that few people have reversed engineered and implemented a proprietary interface. An XSVF player does do the jtag. What it is not is something which knows by itself the syntax of the proprietary commands to send via jtag to the xilinx config device; it gets around that by following explicit instructions in the XSVF file. The proprietary commands become part of the "data"Article: 116845
Thank you very much for that pointer. It still appears that aside from what Antti did, no one (at least on this list) has successfully done a real JTAG programmer for the XCF...just XSVF Player type programmers. I just find that odd. "MM" <mbmsv@yahoo.com> wrote in message news:5684abF27jrufU1@mid.individual.net... > Take a look at this old discussion: > http://tinyurl.com/277l9a > > /Mikhail > >Article: 116846
On Mar 19, 4:06 pm, "B. Joshua Rosen" > The E6700 has a lot of headroom, I'm running mine overclocked to 3GHz > using the stock Intel cooler and 4G of DDR2 800 RAM slightly underclocked > to 750MHz (the RAM speed is set to 667 in the BIOS, the core clock is at > 300 instead of 266 which gives you 752). I'm running the system 24/7 > doing NC Verilog simulations and Xilinx place and routes. It's been up > since Dec without any problems. I wish I could buy a system that has overclocking potential. Unfortunately we are mostly limited to Dell machines, which do not provide any overclocking possibilities in the bios. Maybe I can convince the IT guy to buy from another supplier. Do you have any recommendation for a reputable PC builder company which doesn't lock its bioses as much as Dell does (for a reasonnable price)? Thanks.Article: 116847
On Mon, 19 Mar 2007 15:11:48 -0700, Patrick Dubois wrote: > On Mar 19, 4:06 pm, "B. Joshua Rosen" >> The E6700 has a lot of headroom, I'm running mine overclocked to 3GHz >> using the stock Intel cooler and 4G of DDR2 800 RAM slightly >> underclocked to 750MHz (the RAM speed is set to 667 in the BIOS, the >> core clock is at 300 instead of 266 which gives you 752). I'm running >> the system 24/7 doing NC Verilog simulations and Xilinx place and >> routes. It's been up since Dec without any problems. > > I wish I could buy a system that has overclocking potential. > Unfortunately we are mostly limited to Dell machines, which do not > provide any overclocking possibilities in the bios. Maybe I can convince > the IT guy to buy from another supplier. Do you have any recommendation > for a reputable PC builder company which doesn't lock its bioses as much > as Dell does (for a reasonnable price)? > > Thanks. I built my system from components I bought from Newegg. I don't know of any reliable online sources for custom machines, I used to use Monarch but they've gone backrupt. Any local white box builder could put the system together for you, that's you best bet for a system that can be overclocked.Article: 116848
Hello: Today, Altera announced the Cyclone III device family. Highlights: Industry's first 65nm low cost FPGA Shipping now (yes, really) Up to 120,000 logic elements, Up to 4 Mbits RAM, 288 18*18 multipliers Aggressive family plan with 8 packages, 8 devices, 3 speed grades, 3 temp grades, leaded/lead free packaging Example of power spec: 120K Logic element device static power spec is ~170mW at 85C typical Device samples, low cost dev kits, documentation and software are all available today on www.altera.com Link to main page: http://www.altera.com/products/devices/cyclone3/cy3-index.jsp Handbook: http://www.altera.com/literature/lit-cyc3.jsp Just a friendly notice to the designer community on this usenet. Best regards, Luanne Schirrmeister Director, Low cost products AlteraArticle: 116849
lschi...@gmail.com wrote: > Hello: > > Today, Altera announced the Cyclone III device family. > > Highlights: > > Industry's first 65nm low cost FPGA > Shipping now (yes, really) > Up to 120,000 logic elements, Up to 4 Mbits RAM, 288 18*18 multipliers > Aggressive family plan with 8 packages, 8 devices, 3 speed grades, 3 > temp grades, leaded/lead free packaging > Example of power spec: 120K Logic element device static power spec is > ~170mW at 85C typical > Device samples, low cost dev kits, documentation and software are all > available today on www.altera.com and the MAX III is due when ?
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