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"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1174155080.360848.315970@n59g2000hsh.googlegroups.com... > Hi, > In my many projects, some signals have both positive reference and > negative reference, does it cause an additional LUT delay? Are you talking about differential signals? If so, most newer parts support differential I/O signals directly although many, if not most, might only be the lower voltage form, LVDS (which is usually what you want...but not always). In any case, this support is generally 'free' in that it is simply an I/O standard so there is no additional delay incurred in generating each half of the differential pair. > > For example, in the following statement Rx and not Rx are both used > and they cannot be put together by a LUT. > > A1 : process(CLK) > begin > if(CLK'event and CLK = '1') then > A <= Sx; > end if; > end process; > > A2 : process(CLK) > begin > if(CLK'event and CLK = '1') then > B <= not Sx; > end if; > end process; > If you are talking about differential I/O, then you wouldn't explicitly write equations for each output, just the 'positive' half (which in the above case appears to be signal 'A'. You would then specify that 'A' is a differential pair and there would then be two physical pins assigned, one to each half. Depending on the actual targetted part, there might be restrictions about just which pins can be differential and which can not and once you've picked the physical pin for the 'positive half' of the pair that also implicitly picks the pin for the 'negative half' as well. > > I am wondering whether Xilinx interconnect resources is capable of > inversing a passing signal based on the need. > Not sure what you mean, but maybe the answer is in what I've already posted. Kevin JenningsArticle: 116776
Nico Coesel wrote: > "Joel" <jceven@gmail.com> wrote: > >> Yes I am using the counter outputs as a clock, and cnt[23] will be fed >> into the clk input of the flop thats going to be synthesized. Based >> on the example of xilinx synthesis constraints I either put the >> synthesis attribute as a verilog comment, or in a xilinx constraints >> file. >> >> I don't think using a bit from a counter is a bad thing to do for a >> clock and that is what I want to do (provided if I make sure the tools >> know its going to be a clock) in digital logic, but again its not so >> much the point that I am using the counter msb as a clock, then how do >> I get the xilinx tools to pick up my synthesis constraints. >> >> I could instantiate a BUFG primitive aswas mentioned but, I'd like to >> learn why my synthesis attribute is being ignored, or not picked up by >> the synthesis tool. > > The answer should be somewhere in the log files. However, the number > of BUFG elements is limited (because they drive low skew global clock > nets). You can use the counter outputs as a local clock without the > BUFG. > > It is a good idea to also specify the period of the local clocks as > well so the routing tools can do a proper placement. BUFGs are not the only limited clocking resource: most devices are further divided into clocking regions and some devices provide as little as two regional clock trees. Depending on how much logic depends on the modified clock, local distribution using hex/long lines can be sufficient but may require some careful constraining to avoid race conditions and all manners of weird issues. When in doubt, synthesis logs are indeed the first thing everybody should look into to determine what went according to plan, what needs improvement and what messed up.Article: 116777
> "Homuncilus" <Sha.Craig@gmail.com> wrote in message > news:1174121624.193180.150560@n59g2000hsh.googlegroups.com... > On 3??17¨¨?, ????2¨º¡À28¡¤?, "Ulsk" <a...@ljs.com> wrote: > I noticed XST 9.1 still doesn't support multi-dim arrays in an always @* > > block. > > Here's a (perhaps poor) example: > > > > reg signed [15:0] table [0:255]; > > reg signed [23:0] sum; > > > > integer i; > > always @* > > begin > > sum = 0; > > for ( i =0; i < 256; i = i + 1 ) > > sum = sum + table[i]; // yes, I know this will synthesize a > > suboptimal > > imbalanced adder-tree! > > end > > I think the code can not be synthesize correctly by any tool not only > ISE! ASIC synthesis tools (like Synopsys Design Compiler, Cadence RTL Compiler, etc.) have no difficulty synthesizing the above example.Article: 116778
Weng, there are no inverters in the interconnect structure. But the obvious flexibility of a ROM=LUT means that you can fold the inversion into the LUT. Remember, LUTs have 4 inputs and one output, except in Virtex-5, where they have 6-inputs and one output, but can optionally have 5 inputs and 2 outputs. I think you can figure out the rest. Peter Alfke, Xilinx ================ On Mar 17, 11:11 am, "Weng Tianxiang" <wtx...@gmail.com> wrote: > Hi, > In my many projects, some signals have both positive reference and > negative reference, does it cause an additional LUT delay? > > For example, in the following statement Rx and not Rx are both used > and they cannot be put together by a LUT. > > A1 : process(CLK) > begin > if(CLK'event and CLK = '1') then > A <= Sx; > end if; > end process; > > A2 : process(CLK) > begin > if(CLK'event and CLK = '1') then > B <= not Sx; > end if; > end process; > > Sx may be a combinational signal or a flip-flop output. > > I am wondering whether Xilinx interconnect resources is capable of > inversing a passing signal based on the need. > > Thank you. > > WengArticle: 116779
On Mar 17, 5:12 pm, "Peter Alfke" <a...@sbcglobal.net> wrote: > Weng, there are no inverters in the interconnect structure. > But the obvious flexibility of a ROM=LUT means that you can fold the > inversion into the LUT. > Remember, LUTs have 4 inputs and one output, except in Virtex-5, where > they have 6-inputs and one output, but can optionally have 5 inputs > and 2 outputs. > I think you can figure out the rest. > Peter Alfke, Xilinx > ================ > On Mar 17, 11:11 am, "Weng Tianxiang" <wtx...@gmail.com> wrote: > > > > > Hi, > > In my many projects, some signals have both positive reference and > > negative reference, does it cause an additional LUT delay? > > > For example, in the following statement Rx and not Rx are both used > > and they cannot be put together by a LUT. > > > A1 : process(CLK) > > begin > > if(CLK'event and CLK = '1') then > > A <= Sx; > > end if; > > end process; > > > A2 : process(CLK) > > begin > > if(CLK'event and CLK = '1') then > > B <= not Sx; > > end if; > > end process; > > > Sx may be a combinational signal or a flip-flop output. > > > I am wondering whether Xilinx interconnect resources is capable of > > inversing a passing signal based on the need. > > > Thank you. > > > Weng- Hide quoted text - > > - Show quoted text - Hi Peter, Thank you for your answer. Your answer is good enough to meet my curiosity. 1. Interconnect has no inverter; 2. Any inverted signals will be absorbed by a LUT. I very much appreciate Peter's EXCELLENT service for Xilinx company as an expert to answer all questions none of Xilinx clients can satisfactorily and authoritatively answers. WengArticle: 116780
Howdy, I'm looking at Xilinx FPGA boards in the $300 range. In a grad school course I worked with a Memec Virtex II-Pro board (V2P4 single PPC core) using EDK. I'd like to continue developing my skills, broaden to either or both HDL languages, Linux or other OS, and DSP implementations/applications. Additional vague requirements: -I'd *like* to have access to accessory boards to make development simpler. -I'd *like* to have a decent variety of peripherals (serial, ethernet, video, compact flash if possible) on board. -I'd *love* to have app notes and reference designs ready to run and dissect. What I want is an Virtex 4 FX based board. Like the ML 403, but that starts at $500 with no cable or development tools and it has a smaller FX12 chip on it. Avnet and Nu Horizon/Digilent also have a board at the $300-350 price point but the boards are similarly limited and the Digilent board doesn't seem to have a library of sample projects or app notes. If I check my ego, I would probably do very well with the Digilent XUP V2P board. Lot's of documentation out there, sample projects, good peripherals, accessory boards, larger FPGA (XC2VP30), good peripherals, etc, etc... http://digilentinc.com/Products/Detail.cfm?Nav1=Products&Nav2=Programmable&Prod=XUPV2P BUT (and you know there's always a but) there is NO support from WebPack. Should this be a deal killer if I can't afford ISE or don't want to be limited to a 30-day license? I guess it's meant to be used in a university lab where all the tools are free to the school but I don't want to be limited by my access to a lab. How is one expected to use the board with no WebPack? Finally, would EDK only be available to me via an evaluation? What's the lone experimenter to do? Thanks, EdArticle: 116781
I am working on TCL scripts that go with EDK pcores that I am developing. The MPD file allows me to specify that I want TCL functions in the files I provide to be called at certain times. I would like to be able to determine the directory that the pcore/data/ *.tcl file that is being used is located in. There are a number of xget_* functions that allow a TCL script to query for information about the project, but I can not find one that will tell me the source of a pcore. Does anyone know how to do this? Regards, John McCaskill www.fastertechnology.comArticle: 116782
On 3=E6=9C=8818=E6=97=A5, =E4=B8=8A=E5=8D=886=E6=97=B617=E5=88=86, "Ulsk" <= a=2E..@ljs.com> wrote: > > "Homuncilus" <Sha.Cr...@gmail.com> wrote in message > >news:1174121624.193180.150560@n59g2000hsh.googlegroups.com... > > On 3??17=C2=A8=C2=A8?, ????2=C2=A8=C2=BA=C2=A1=C3=8028=C2=A1=C2=A4?, "U= lsk" <a...@ljs.com> wrote: > > I noticed XST 9.1 still doesn't support multi-dim arrays in an always @* > > > block. > > > Here's a (perhaps poor) example: > > > > reg =C2=A0signed [15:0] table [0:255]; > > > reg =C2=A0signed [23:0] sum; > > > > integer i; > > > always @* > > > begin > > > =C2=A0 sum =3D 0; > > > =C2=A0 for ( i =3D0; i < 256; i =3D i + 1 ) > > > =C2=A0 =C2=A0 sum =3D sum + table[i]; =C2=A0// yes, I know this will = synthesize a > > > suboptimal > > > imbalanced adder-tree! > > > end > > > I think the code can not be synthesize correctly by any tool not only > > ISE! > > ASIC synthesis tools (like Synopsys Design Compiler, Cadence RTL > Compiler, etc.) have no difficulty synthesizing the above example.- =E9= =9A=90=E8=97=8F=E8=A2=AB=E5=BC=95=E7=94=A8=E6=96=87=E5=AD=97 - > > - =E6=98=BE=E7=A4=BA=E5=BC=95=E7=94=A8=E7=9A=84=E6=96=87=E5=AD=97 - Could you tell me the result about the above example being synthesized by the ASIC tools and could you sure that the function runs well?Article: 116783
Ed I don't think you are going to have much luck on your budget. I agree about Webpack thing and indeed on our products we in many cases choose to use a XC3S400-1500 as device options for exactly that reason. You aren't likely to get a Virtex based board for US$300 due to the price of the silicon although we may have something that will get close to that for students coming in our line. Commercial pricing will be a bit more. Details of the products coming won't released for a little early even for me to talk about other than there will be some boards very different concepts to our existing lines. EDK has previously been available as trial software but I believe the current Xilinx thinking is not to offer that at present. As to modular boards we have a reasonable range including RS232, RS485, ADC, PS2 to name a few. I hope we will also be finally showing the DDR2 and SDRAM modules for Raggedstone1 this week or maybe next. They have been assembled and awaiting test for those interested in these. Proving there are not any issues they they will be on sale shortly after. We should have some more lab materials appearing on our site shortly. They have been prepared some time ago but never made it to the website yet. If anyone would like to contribute materials I'm hoping we can get a user group area going on our website for people to swap ideas and projects. John Adair Enterpoint Ltd. - Home of the Raggedstone1. Low cost FPGA Development Board. On 18 Mar, 03:40, "elr" <odof...@yahoo.com> wrote: > Howdy, > I'm looking at Xilinx FPGA boards in the $300 range. In a grad school > course I worked with a Memec Virtex II-Pro board (V2P4 single PPC > core) using EDK. I'd like to continue developing my skills, broaden to > either or both HDL languages, Linux or other OS, and DSP > implementations/applications. > > Additional vague requirements: > -I'd *like* to have access to accessory boards to make development > simpler. > -I'd *like* to have a decent variety of peripherals (serial, ethernet, > video, compact flash if possible) on board. > -I'd *love* to have app notes and reference designs ready to run and > dissect. > > What I want is an Virtex 4 FX based board. Like the ML 403, but that > starts at $500 with no cable or development tools and it has a smaller > FX12 chip on it. Avnet and Nu Horizon/Digilent also have a board at > the $300-350 price point but the boards are similarly limited and the > Digilent board doesn't seem to have a library of sample projects or > app notes. > > If I check my ego, I would probably do very well with the Digilent XUP > V2P board. Lot's of documentation out there, sample projects, good > peripherals, accessory boards, larger FPGA (XC2VP30), good > peripherals, etc, etc...http://digilentinc.com/Products/Detail.cfm?Nav1=Products&Nav2=Program... > > BUT (and you know there's always a but) there is NO support from > WebPack. Should this be a deal killer if I can't afford ISE or don't > want to be limited to a 30-day license? I guess it's meant to be used > in a university lab where all the tools are free to the school but I > don't want to be limited by my access to a lab. > > How is one expected to use the board with no WebPack? > > Finally, would EDK only be available to me via an evaluation? > > What's the lone experimenter to do? > > Thanks, EdArticle: 116784
Thank you for all your reply. I saw on the document to use bitgen -w -g USerID:<userID> -g StartupClk:JTAGClk my_design my_design What I used is bitgen -w <-g StartupClk:JTAGClk> -f bitgen.ut system I also changed the JTAG clock as 200Khz in the ChipScope setting, with or without -g StartupClk:JTAGClk, but all are same: "waiting for core to be armed". Here are the commands I used after inserted the ILA core. system.ngo is generated by chipscope. ngdbuild -p xc5vlx50ff676-1 -nt timestamp -bm system.bmm system.ngo -uc system.ucf system.ngd map -o system_map.ncd -w -pr b system.ngd system.pcf par -w -ol std system_map.ncd system.ncd system.pcf trce -e 3 -xml system.twx system.ncd system.pcf bitgen -w <-g StartupClk:JTAGClk> -f bitgen.ut system Anything wrong here?Article: 116785
On Mar 16, 9:35 am, loc...@noos.fr wrote: > Bonjour, > > My name is Julien Lochen, I work as FPGA Design Engineer in France. > > My question is about the init of FPGA's RAMs. > > In my design, some data are stored in a block-RAM. > > I need to init each byte stored in the block-RAM, but THE INIT VALUE > ARE NOT THE SAME. > > To do this, I use the constraint file, in which I use the following > keyword : > > "INIT_00 = 256'h ... > INIT_01 = 256'h ... > ... > INIT_3F = 256'h ..." > > The block-RAM is mapped as follow : 256 lines of 1 byte. > > The question is : > > If I want to init only the five first addresses to "1", and the rest > of the block-RAM to zero, am I correct if I write : > "INIT_00 = > 256'h0000000000000000000000000000000000000000000000000000FFFFFFFFFFFF; > INIT_01 = > 256'h0000000000000000000000000000000000000000000000000000000000000000; > ... > INIT_3F = > 256'h0000000000000000000000000000000000000000000000000000000000000000;" > > regards, Julien The "first five addresses" are different for different BRAM data width setting, so it is hard to say whether your values in UCF is correct or not without knowing the bus width. Cheers, Jim http://home.comcast.net/~jimwu88/tools/Article: 116786
how to transform Arun's LDPC code to max-product (Min-sum)? comp.dsp LDPC Advice would be appreciated on how to transform Arun's code given on http://arun-10.tripod.com/ldpc/ldpc.htm from sum-product to max-product (or min-sum) algorithm. He follows the MacKay's algorithm, introducing delta to simplify the computation. In max-product computation of sum() is replaced by computation of max(), so basically because in Arun's code the algorithm avoids computing the sum() - does it mean that it is not transformable to make max-roduct? George.Article: 116787
Patrick Dubois wrote: > Hi, > > I'm about to buy a new workstation for FPGA development and I'm > hesitating between a Core 2 Extreme @ 2.93 GHz (X6800) and the new > quad-core @ 2.66 GHz (QX6700). The price difference is 100$. > > Does Xilinx have any roadmap for multi-core CPU support in the future? > I'd hate to buy a dual-core CPU just to learn that ISE v10.1 features > quad-core support... > > If there is no multi-core support planned for the foreseeable future, > I'll probably buy the dual-core CPU because it's slightly faster than > the quad-core one. I'm going to work on a Virtex 4 FX100 soon so I'll > need all the horsepower I can get for the P&R runs... > > Patrick Considering how touchy the ISE tools can be and how much tougher PAR can be to parallelize than synthesis, translation and mapping, I am not expecting PAR to parallelize any time soon. While it certainly would be nice, I would be more interested in seeing existing (crash-)bugs and other annoyances get squished than seeing PAR&all crash twice as fast and twice as often. If you can postpone this purchase for a few more months, I suggest you wait and get a C2D E6850 when they are released: these will be much less expensive (266 USD) yet a bit faster (3GHz with 1333MHz FSB) than the X6800. The CPU economy alone will be sufficient to finance most of the new quad-core system (or replacement quad-core CPU) by the time ISE becomes fully multi-threaded, stable and reasonably scalable beyond two CPUs.Article: 116788
Weng Tianxiang wrote: > > Hi Peter, > Thank you for your answer. Your answer is good enough to meet my > curiosity. > > 1. Interconnect has no inverter; > 2. Any inverted signals will be absorbed by a LUT. > > I very much appreciate Peter's EXCELLENT service for Xilinx company as > an expert to answer all questions none of Xilinx clients can > satisfactorily and authoritatively answers. > > Weng > Not *all* inverters must be absorbed by LUTs. I'm worried you'll take this answer too far. The SLICEs and IOBs both have a significant amount of control over inversions for input signals. If you open a design with FPGA Editor, you'll see many of the signals in the SLICE and IOB (even the BlockRAMs and Multipliers) such as clock, reset, the direct-input BX and BY values, and most of the signals *except* for the LUT inputs have a normal/invert option where the invert gets absorbed into the SLICE. The data and address into BlockRAMs and arguements of the multiply might not have automatic inversion available but their control signals mostly do. The one condition I recall having to pay attention to the signal polarity in general logic - where it can affect timing - is when going in to a carry chain as a direct input to the MUXCY primitive. I can infer an add or subtract fine, but sometimes a needed inversion results in an extra LUT of delay before coming onto the carry chain because the .DI (or MULT_AND) inputs can't absorb the input. Often it's just a matter of producing an inverted form of the registers that feed the logic; this is sometimes referred to as "not gate push-back" if it's handled for you by the synthesizer. - John_HArticle: 116789
elr wrote: > > If I check my ego, I would probably do very well with the Digilent XUP > V2P board. Lot's of documentation out there, sample projects, good > peripherals, accessory boards, larger FPGA (XC2VP30), good > peripherals, etc, etc... > http://digilentinc.com/Products/Detail.cfm?Nav1=Products&Nav2=Programmable&Prod=XUPV2P > > BUT (and you know there's always a but) there is NO support from > WebPack. Should this be a deal killer if I can't afford ISE or don't > want to be limited to a 30-day license? I guess it's meant to be used > in a university lab where all the tools are free to the school but I > don't want to be limited by my access to a lab. > > How is one expected to use the board with no WebPack? > > Finally, would EDK only be available to me via an evaluation? > > What's the lone experimenter to do? Hi, I got a pair of these XUPs when I took my last undergrad digital system design class. Sure, the V2P is not the newest or greatest chip around and falls short in a few areas but the board is otherwise fairly well-rounded for the price... even more so when you consider that the board costs $300 even though the FPGA on it is listed at around $800 - these boards are heavily subsidized by Xilinx. Before you order this board, you need someone from your university to setup an account with Digilent before you can buy those subsidized boards. After that, you need someone to contact a Xilinx sales rep. to ask for the necessary software to support those boards. Since the company my teacher back then works at is a major Xilinx account in the area, we had no problem setting up the Digilent account and getting Xilinx's authorization for copies of ISE/EDK DVDs and keys. The story says the Xilinx sales rep. was surprised to hear that no software came with those boards. Your mileage may vary, so delay your order until you have secured both the tools and valid keys should you decide to try going XUP.Article: 116790
John, Thanks for your response. As Daniel mentions, Xilinx subsidizes their silicon so that Digilent can offer the board at a very low price (when considering the value of just the FPGA). The XUP is $300 for educational purposes. It's a *much* larger FPGA (2x the PPC cpu's, nearly an order of magnitude larger in slices and BRAM) than the Virtex II-Pro I worked with. No slouch. Not *the* bleeding edge nor a good idea for new commercial designs but it looks good to learn on. I'll check out your site, although the $/pound exchange is unfavorable for British products in the US right now. Daniel, Thank you, that is exactly what I needed to know to make the XUP board worth considering. The prof I took the class with does tons with Xilinx products so I'll ask him if he has Xilinx rep contacts. You don't happen to have a rep's contact info, do you? Accdg to the digilent site, it seemed to allow me to get all the way to credit card # entry in the check-out process with a $300 invoice for the XUP. Do you think I still need an acct with Digilent? I'm eager to buy, but I'll wait to see if I can network to the Xilinx folks. Another Digilent alternative for $300 is the FX12 board: https://www.digilentinc.com/Products/Detail.cfm?Prod=FX12&Nav1=Products&Nav2=Programmable Not as feature rich and I don't see much in the way of app notes or reference designs. It does have gigabit ethernet. -Ed On Mar 18, 12:27 pm, "Daniel S." <digitalmastrmind_no_s...@hotmail.com> wrote:> > Hi, > > I got a pair of these XUPs when I took my last undergrad digital system design class. > Sure, the V2P is not the newest or greatest chip around and falls short in a few areas but > the board is otherwise fairly well-rounded for the price... even more so when you consider > that the board costs $300 even though the FPGA on it is listed at around $800 - these > boards are heavily subsidized by Xilinx. > > Before you order this board, you need someone from your university to setup an account > with Digilent before you can buy those subsidized boards. After that, you need someone to > contact a Xilinx sales rep. to ask for the necessary software to support those boards. > Since the company my teacher back then works at is a major Xilinx account in the area, we > had no problem setting up the Digilent account and getting Xilinx's authorization for > copies of ISE/EDK DVDs and keys. The story says the Xilinx sales rep. was surprised to > hear that no software came with those boards. > > Your mileage may vary, so delay your order until you have secured both the tools and valid > keys should you decide to try going XUP.Article: 116791
On Mar 15, 10:49 pm, "motty" <mottobla...@yahoo.com> wrote: > I have 2 DCM's in the project. Each DCM's lock signal is routed out > to an LED on the board. Each DCM's output clock is routed to a header > pin (as well as elsewhere in the design). After configuration (or > after a pushbutton RESET to the FPGA) the lock LED's light and the > output clocks are valid. This lasts about half a second. Then > everything goes dead. So lock is high and valid clocks are output for > at least hundreds of thousands of cycles. Then nothing. > [...] > One difference I noticed is that the ISE reports that the DCM > hierarchical names have changed due to DCM Autocalibration. There are > also multiple refences to this DCM autocalibration in various > reports. I just went through this last week. Had the same behavior. Went about the debug the same way that you did. Turning off the DCM autocalbration soved the problem. THe following line in your UCF will work: INST dcm_0/dcm_0/Using_DCM_ADV.DCM_ADV_INST DCM_AUTOCALIBRATION="FALSE"; (Substitute the name of your DCM for mine...) Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 38 Chauncy St #1101; Boston, MA 02111 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 116792
I might have some reps' contact info jotted down on a note somewhere from many months ago but I have no idea where that note is now. If your prof is involved in Xilinx-sponsored research projects or anything else of the sort, he should have some equivalent contacts of his own. I have worked on post-doc projects (telecom/DSP) as an intern and back then, Xilinx was quite happy to sponsor projects that pushed the frontier of FPGA-based applications... they most likely still do today. As for the Digilent site, yes, it does list the price as $300 when you file the order but Digilent will call back to verify whether or not your school and yourself qualify for the reduced price. Maybe they do not call to verify all orders but they did call for mine, they asked for the school's name, teacher's name, my name and a few other details. For the FX12, V4 may be newer and able to reach higher clocks... but much of the V4 is taken directly from the V2Pro. If could re-pick my first ~$300 student-oriented board again today, I think I would still go with the V2P30 until a comparable V5 board appears. Filling a VP30 to 25% can happen pretty fast so there is no way I would select anything significantly smaller than that for a general-purpose experimental platform, even more so if both are comparably priced. Of course, the FX12 board is still a good choice for those not eligible for the $300 XUP deal and/or are stuck with ISE WebPack. But for the kind of things I am playing with (or planning to), the V2P30's extra headroom is highly welcome... and since I have two of 'em, I can experiment with MGT cross-connecting should I ever run out of space. Rivas wrote: > John, > Thanks for your response. As Daniel mentions, Xilinx subsidizes their > silicon so that Digilent can offer the board at a very low price (when > considering the value of just the FPGA). The XUP is $300 for > educational purposes. It's a *much* larger FPGA (2x the PPC cpu's, > nearly an order of magnitude larger in slices and BRAM) than the > Virtex II-Pro I worked with. No slouch. Not *the* bleeding edge nor a > good idea for new commercial designs but it looks good to learn on. > I'll check out your site, although the $/pound exchange is unfavorable > for British products in the US right now. > > Daniel, > Thank you, that is exactly what I needed to know to make the XUP board > worth considering. The prof I took the class with does tons with > Xilinx products so I'll ask him if he has Xilinx rep contacts. You > don't happen to have a rep's contact info, do you? > > Accdg to the digilent site, it seemed to allow me to get all the way > to credit card # entry in the check-out process with a $300 invoice > for the XUP. Do you think I still need an acct with Digilent? I'm > eager to buy, but I'll wait to see if I can network to the Xilinx > folks. > > Another Digilent alternative for $300 is the FX12 board: > https://www.digilentinc.com/Products/Detail.cfm?Prod=FX12&Nav1=Products&Nav2=Programmable > > Not as feature rich and I don't see much in the way of app notes or > reference designs. It does have gigabit ethernet. > > -Ed > > On Mar 18, 12:27 pm, "Daniel S." > <digitalmastrmind_no_s...@hotmail.com> wrote:> >> Hi, >> >> I got a pair of these XUPs when I took my last undergrad digital system design class. >> Sure, the V2P is not the newest or greatest chip around and falls short in a few areas but >> the board is otherwise fairly well-rounded for the price... even more so when you consider >> that the board costs $300 even though the FPGA on it is listed at around $800 - these >> boards are heavily subsidized by Xilinx. >> >> Before you order this board, you need someone from your university to setup an account >> with Digilent before you can buy those subsidized boards. After that, you need someone to >> contact a Xilinx sales rep. to ask for the necessary software to support those boards. >> Since the company my teacher back then works at is a major Xilinx account in the area, we >> had no problem setting up the Digilent account and getting Xilinx's authorization for >> copies of ISE/EDK DVDs and keys. The story says the Xilinx sales rep. was surprised to >> hear that no software came with those boards. >> >> Your mileage may vary, so delay your order until you have secured both the tools and valid >> keys should you decide to try going XUP. > >Article: 116793
Yep, that is what I did. I have my DCM configured such that the CLKFB is not connected. I don't really need it for my application and thought I would save some clock buffers. Apparently, the DCM Autocal circuitry will hold the DCM in reset if EITHER the CLKFB or CLKIN loses a clock signal. Well, CLKFB never had one, so I guess the Autocal cicuitry waits for lock until it performs its function. So now I have everything working as should be! Thanks for the reply!Article: 116794
On Mar 16, 6:00 am, "uvbaz" <u...@stud.uni-karlsruhe.de> wrote: > Hi, > > I have a input clock "i_clk_main", in my VHDL code, i divide this clk > with factor 2, that means "clk_int" has the half frequenz as > "i_clk_main", and i use "clk_int" to clock the output register. > > Now, i must in the constraint file define, how much ns delays the > output relative to "clk_int" may maximal have. What should i do? The > following is the error report fomr ISE. > > Checking timing specifications ... > ERROR:XdmHelpers:634 - Signal "clk_int" is used as the clock in > specification "OFFSET=OUT 7000 pS AFTER clk_int HIGH", but this > clock > signal is not connected directly to a pad. An OFFSET specification > must use a > pad signal to designate the clock. > > Thanks, and have a nice weekend > Cheng Instead of tying using clk_int as a clock, you might try using it as an enable for your synchronous devices, and clock them using i_ckk_main. Then the tool can calculate your OFFSETs. One hazard with this approach is that if you are already using the CE pins, this will add more logic to the CE paths. With this approach, you also have to use multi-cycle timing contraints. This can be done by creating a group with clk_int: NET "clk_int" TNM_NET = "slow_devs"; and then TIMESPEC "TS_slow_devs" = FROM "slow_devs" to "slow_devs" = main_period*2; The hazard here is that your synthesis tool may replicate clk_int, and you have to chase all copies of it to include all half-speed devices in the slow_devs group. Once the above is done, you can make all your OFFSETs relative to i_clk_main. HTH Just JohnArticle: 116795
On Mar 18, 11:14 am, John_H <newsgr...@johnhandwork.com> wrote: > Weng Tianxiang wrote: > > > Hi Peter, > > Thank you for your answer. Your answer is good enough to meet my > > curiosity. > > > 1. Interconnect has no inverter; > > 2. Any inverted signals will be absorbed by a LUT. > > > I very much appreciate Peter's EXCELLENT service for Xilinx company as > > an expert to answer all questions none of Xilinx clients can > > satisfactorily and authoritatively answers. > > > Weng > > Not *all* inverters must be absorbed by LUTs. I'm worried you'll take > this answer too far. > > The SLICEs and IOBs both have a significant amount of control over > inversions for input signals. If you open a design with FPGA Editor, > you'll see many of the signals in the SLICE and IOB (even the BlockRAMs > and Multipliers) such as clock, reset, the direct-input BX and BY > values, and most of the signals *except* for the LUT inputs have a > normal/invert option where the invert gets absorbed into the SLICE. The > data and address into BlockRAMs and arguements of the multiply might not > have automatic inversion available but their control signals mostly do. > > The one condition I recall having to pay attention to the signal > polarity in general logic - where it can affect timing - is when going > in to a carry chain as a direct input to the MUXCY primitive. I can > infer an add or subtract fine, but sometimes a needed inversion results > in an extra LUT of delay before coming onto the carry chain because the > .DI (or MULT_AND) inputs can't absorb the input. Often it's just a > matter of producing an inverted form of the registers that feed the > logic; this is sometimes referred to as "not gate push-back" if it's > handled for you by the synthesizer. > > - John_H Hi John, Thank you for your advice. I am reading Virtex-5 CLB block diagram now. It is no doubt that the better the FPGA internal structure is understood, the high performance one can achieve. WengArticle: 116796
On Mar 18, 12:09 pm, "GB" <1...@excite.com> wrote: > how to transform Arun's LDPC code to max-product (Min-sum)? > comp.dsp LDPC > Advice would be appreciated on how to transform Arun's code given onhttp://arun-10.tripod.com/ldpc/ldpc.htm > from sum-product to max-product (or min-sum) algorithm. > He follows the MacKay's algorithm, introducing delta to simplify the > computation. In max-product computation of sum() is replaced by > computation of max(), so basically because in Arun's code the > algorithm avoids computing the sum() - does it mean that it is not > transformable to make max-roduct? > George. Maybe I'm the only one here who doesn't know what "Arun's LDPC code" exactly is, but from what little I can understand from your question: Yes, it is probably not easily transformable to max-product if it's not exactly a sum-product algorithm in the first place. JuliusArticle: 116797
julius wrote: ... > Maybe I'm the only one here who doesn't know what "Arun's > LDPC code" exactly is, ... There are at least two of us. Jerry -- Engineering is the art of making what you want from things you can get. ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯Article: 116798
On Mar 16, 11:28 pm, "Ulsk" <a...@ljs.com> wrote: > I noticed XST 9.1 still doesn't support multi-dim arrays in an always @* > block. > Here's a (perhaps poor) example: > > reg signed [15:0] table [0:255]; > reg signed [23:0] sum; > > integer i; > always @* > begin > sum = 0; > for ( i =0; i < 256; i = i + 1 ) > sum = sum + table[i]; // yes, I know this will synthesize a suboptimal > imbalanced adder-tree! > end Correct me if I'm wrong, but I believe that this is not valid verilog - you cannot use an array as a term in the always() sensitivity list, and the always* implies that the array is in the sensitivity list. I know that the ncverilog simulator warns about this (but does work). It states that this is non-portable verilog. Synopsys DC does indeed synthesize this correctly, but it's not a good idea to use non- standard verilog statements. ISE seems to err on the side of adhering to the strict rules of the verilog language. I could be wrong about this, but from the warning given by ncverilog, I believe this to be the case. Maybe try a verilog linting tool? formality/conformal should set you straight, if you have them. Cheers JohnArticle: 116799
Hi, I couldn't find any comparison between FPGA and GPP. I thought I could get some of the expert two-cents on this matter especially in terms of cost, power and performance from this group. Cheers, Ace
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