Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I need a production station that can (a) burn my xilinx xf08p serial prom and (b) xdownload some code to be burned to flash. I currently have to use Impact for the prom and XMD for the flash. I don't want to pay for a whole extra EDK and ISE just for this. Can anyone suggest another solution? Thanks, ClarkArticle: 115751
Hello, I am trying to debug the sdram interface on a custom board I built. I need to look at some of the internal signals of the PLB_DDR interface. I modified the VHDL code and the .mpd file. However, the changes that I made to the .mpd file don't show up in EDK. Has anyone seen this before? I know I modified the correct mpd because when I select view mpd in EDK, the changes that I made show up. I have created custom peripherals before, and changes that I've made to other non-xilinx created mpd files show up in EDK. So is this a known issue with xilinx predefined mpd files? Thanks, HarryArticle: 115752
Frank, I did this for all my coregen components, but I did it all manually, not through the xilinx gui. I have a folder for my custom IP cores called "myProcessorIPLib" and under this directory I created pcores -> CoregenLib -> hdl -> vhdl this is the standard directory stucture that xilinx uses. You can but all of your common VHDL files in the vhdl directory. In your pao file you will need to add the vhdl files that you want to compile. so for example, if you have a file called tmp.vhdl you will have something like this lib CoregenLib tmp vhdl You can change CoregenLib to whatever your peripheral name is, so it's probably going to look like lib myperipheral_v1_00_a tmp vhdl Once you have modified you pao file, you can instantiate your vhdl file in your user_logic.vhd file as you would with any other component instantiation. Harry I've done this before, but I had to do it the manual way.way to do this is to create a shared components directory. You will still need the directory stucture "Frank van Eijkelenburg" <someone@home.com.invalid> wrote in message news:45d4cec3$0$738$5fc3050@dreader2.news.tiscali.nl... > Hi, > > I have a small microblaze system with my own ipif peripheral. In this > peripheral I want to use a vhdl block which is also used in another part > of my project. Is this possible? Because when building the system, the edk > looks in the pcores/<peripheral name>/hdl/vhdl directory for sources > (where it doesn't find the shared vhdl part and I don't want to place the > shared vhdl code in this directory!). > > TIA, > FrankArticle: 115753
CAN ANY BODY EXPLAIN ROC PORT AND GIVE SOME INFORMATION ABOUT IT? HOW CAN WE ACTIVATE IT IN OUR VHDL CODE? THANK YOUArticle: 115754
"Charles" <charlesg77@yahoo.com> wrote in message news:1171898866.806419.234510@p10g2000cwp.googlegroups.com... >I have some very basic problems getting simple things to work on this > platform. Is there a quirk of this product this i don't know about?? > seem to have problems with counters and state machines.. > Not much info to go on...... I had no problems with the ProASIC+ (http://www.ht-lab.com/hardware/APABoard/APABoard.html) except that the P&R is very slow, Hans www.ht-lab.comArticle: 115755
Peter Alfke a écrit : > Yes, comprehensive testing is very complicated, but we have one > advantage: > We can reconfigure the chips during testing, and we do that hundreds > of times. > That's why we joke that we actually sell "used FPGAs". Hey !! Gimme back my money ! I bought them as new, not second hand stuff ! ;o) NicolasArticle: 115756
Sean Durkin wrote: >Jon Elson wrote: > > >>The distributors have warehouses full of non-RoHS compliant parts they >>need to get >>rid of before they can fill them back up with more stuff they won't be >>able to move. >> >> >The way I see it, they don't even have warehouses anymore in most cases. >They forward your order to the chip manufacturer and put a new sticker >on the package before they forward it to you. > > Umm, maybe. Check the return address on sample parts you get from TI and I think Analog Devices, at least. Hmm, 701 Brooks Ave. South, Thief River Falls, MN. Isn't that the address of Digi-Key? What a coincidence! So, at least in some cases, the manufacturer doesn't keep their own stock, or just doesn't want to deal with the hundreds of little envelopes going out. > > JonArticle: 115757
On Feb 19, 10:27 am, "Charles" <charles...@yahoo.com> wrote: > I have some very basic problems getting simple things to work on this > platform. Is there a quirk of this product this i don't know about?? > seem to have problems with counters and state machines.. 1) If you are used to programming SRAM-based FPGA's, you may have gotten lazy about explicit resets for registers, as they tend to get implicitly initialized when the bitstream is loaded. In contrast, flash-based archictures are more likey to come up in an unusual state, and not necessarily just a random selection from the states you planned on having happen. So make sure everything has an explicit reset. 2) The actel tools, and synplify which they use, tend to be a bit pickier than xilinx or altera. For example, if you temporarly remove any dependence on an input signal it may get optomized out of the design, which is fine. What you don't expect is to find out that it's been optomized out of the pin assignments, such that when you un- comment-out the use of that signal, you now have logic depending on an un-assigned pin. 3) What I really hate though is the programmer's insistence on programming and then verifying the _unused_ bits. I don't usually have verification turned on during debug, and a programmer which doesn't give you a choice, plus is slow to start with...Article: 115758
cs_posting@hotmail.com wrote: > 3) What I really hate though is the programmer's insistence on > programming and then verifying the _unused_ bits. I don't usually > have verification turned on during debug, and a programmer which > doesn't give you a choice, plus is slow to start with... So how fast/slow are these devices to pgm ? -jgArticle: 115759
Hi Harry,
Harry Stello wrote:
> I am trying to debug the sdram interface on a custom board I built. I need
> to look at some of the internal signals of the PLB_DDR interface. I
> modified the VHDL code and the .mpd file. However, the changes that I made
> to the .mpd file don't show up in EDK. Has anyone seen this before? I know
> I modified the correct mpd because when I select view mpd in EDK, the
> changes that I made show up.
>
> I have created custom peripherals before, and changes that I've made to
> other non-xilinx created mpd files show up in EDK. So is this a known issue
> with xilinx predefined mpd files?
If you haven't done so already, do a "clean" on your project. Xilinx
cores are all marked as "CORE_STATE = ACTIVE", so changes in MPD and VHD
files won't be picked up between builds (synthesis results are cached).
When you are core hacking, make sure you have CORE_STATE = DEVELOPMENT
in the MPD file to prevent EDK from caching.
A related suggestion: Never modify MPD/PAO/VHD files in the
${EDK}/hw/... pcores hierarchy. Why? Because you'll surely forget,
then one day have some utterly un-debuggabble issue that traces back to
munging you've done on standard cores.
Much better to copy the core of interest into your project-local pcores
directory, and hack on it there. The search path is
local pcores directory
overridden edk_user_repository path specified in XMP file.
${EDK}/../edk_user_repository
${EDK}/hw/XilinxProcessorIPLib/pcores
When doing the local copy trick of standard Xilinx cores, you can get
cute and only copy the files you need to modify - e.g. the MPD and one
or two VHD files. Xilinx do this sometimes with EDK reference designs
that need some massaging of standard cores.
It's also not a bad idea to change the core version number to something
silly like 99.99.z to make it clear in your designs that it's not the
standard one. This requires some directory renaming and editing of PAO
and VHD files to get the package names correct.
Hope this helps,
John
Article: 115760Hi all, Does MIG1.6 work on ISE9.1i+SP1? I plan to implement a DDR2-SDRAM controller. Thanks in advance Mehdi.Article: 115761
I am trying to use the Xilinx Memory Interface Generator (MIG) version 1.6 to generate a DDR2 x16 core for initiall testing of a XC4VFX12-10SF363 board that we are bringing up this week. The memory is a Micron MT47H32M16BT-3. After some challenges, not the least of which, MIG doesn't want to run from CORE Generator; the standalone user interface needs to be guessed, as all data isn't passed through the GUI... I have generated a core in VHDL that seems to be quite similar (but not exactly) to XAPP721. I hope this isn't an RTFM question... as I can't find the manuals to read... Has anybody: A) Used MIG to generate a DDR2 core in x16 configuration for V4? (Antti, from one of your previous posts, I think you have a yes answer to this) B) Found any meaningful documentation of the MIG and/or the DDR2 core specifically? (The user guide that comes with it is a little light.) C) If yes to A, what docs did you find the interface spec in? or did you just start reading the source code? I am using ISE/EDK 8.1 and MIG 1.6. I will probably have to move this project to 8.2 by the end of the week for various reasons. For the short term this seems like a decent moderate-performance way to get a x16 DDR2 onto a x64 PLB bus. Long term we will need to write our own core to get the performance we need, but for the next few weeks, this will be fast enough. D) Am I overlooking any obvious quick and dirty paths to getting a x16 DDR2 onto a x64 PLB? (I did not see anything in EDK.) E) Am I in for a world of hurt going down the path that I have selected? (Positive experiences with MIG would be reassuring.) Thanks for the help in advance. I will start a case tomorrow with X... in the meantime I would appreciate it very much if somebody had some experience that he wants to share. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 38 Chauncy St #1101; Boston, MA 02111 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 115762
Hi all, I want to evaluate the area and time cost of an intermediate product on Xilinx FPGA. But the number of output ports exceed number of I/O pins. (Actually there will be much less outputs in the final product. ) But currently, I need test the intermediate product by using Xilinx ISE. Can I add some ISE specific declaration to avoid the fully IO mapping while I can still get the area and time cost reports? Thanks a lot. Sincerely, AaronArticle: 115763
I found the documentation that I needed... turns out it was an RTFM
question for the most part.
Though, if anybody has any direct experience with MIG 1.6, DDR2 x16
used in V4, I would love to hear how it went.
Regards,
Erik.
On Feb 19, 7:46 pm, "Erik Widding" <widd...@birger.com> wrote:
> I hope this isn't an RTFM question... as I can't find the manuals to
> read...
>
> Regards,
> Erik.
>
> ---
> Erik Widding
> President
> Birger Engineering, Inc.
>
> (mail) 38 Chauncy St #1101; Boston, MA 02111
> (voice) 617.695.9233
> (fax) 617.695.9234
> (web)http://www.birger.com
From dave@comteck.com Mon Feb 19 19:58:38 2007
Path: newssvr27.news.prodigy.net!newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!news.linkpendium.com!news.linkpendium.com!newspeer1.nwr.nac.net!border2.nntp.dca.giganews.com!nntp.giganews.com!uns-out.usenetserver.com!news.usenetserver.com!pc02.usenetserver.com!COMTECK.COM-a2kHrUvQQWlmc!not-for-mail
From: Dave <dave@comteck.com>
Subject: Re: need help on our thesis proposal in our school.
Date: Mon, 19 Feb 2007 22:58:38 -0500
User-Agent: Pan/0.14.2 (This is not a psychotic episode. It's a cleansing moment of clarity.)
Message-Id: <pan.2007.02.20.03.58.38.510478@comteck.com>
Newsgroups: comp.arch.fpga
References: <1171858551.756265.140630@j27g2000cwj.googlegroups.com> <YomdnXb1pphht0TYnZ2dnUVZ_oGlnZ2d@web-ster.com> <1171873153.839169.316500@v45g2000cwv.googlegroups.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 8bit
X-Complaints-To: abuse@usenetserver.com
Organization: UseNetServer.com
Lines: 20
X-Trace: 377e345da7226e51d977317515
Xref: prodigy.net comp.arch.fpga:127190
On Mon, 19 Feb 2007 00:19:13 -0800, rits11 wrote:
> On Feb 19, 12:44 pm, Tim Wescott <t...@seemywebsite.com> wrote:
>> rit...@gmail.com wrote:
>> Tim Wescott
>> Wescott Design Serviceshttp://www.wescottdesign.com
>>
>> "Applied Control Theory for Embedded Systems" came out in April.
>> See details athttp://www.wescottdesign.com/actfes/actfes.html
>
> Sir, do you have some
> tutorials or reading materials regarding Mathlab and Scilab so that we
> can use them in our thesis? Thank you again Mr. Tim Wescott for your
> post.
Well, you could try his book mentioned above and browse his website.
~Dave~
Article: 115764On Feb 19, 10:45 am, "cpope" <cep...@nc.rr.com> wrote: > I need a production station that can (a) burn my xilinx xf08p serial prom > and (b) xdownload some code to be burned to flash. I currently have to use > Impact for the prom and XMD for the flash. I don't want to pay for a whole > extra EDK and ISE just for this. Can anyone suggest another solution? For the serial prom, have you tried impact from the downloadable, no- cost webpack version of ISE? While the bitstream generation tools in that won't handle the larger parts, I'd be a little suprised if they limited impact. Or if they did, how about digilent's USB cable and software, for much less than Xilinx's cable (think "export" can do a prom via and svf file, but it would be worth double checking)? As for the flash rom, I don't know what is most cost effective (what your time making it work is worth), but cheapest hardware would probably be to put some function in your fpga that can accept data over an external interface (spi?) and program it. Perhaps a small design that you download directly to the FPGA temporarily?Article: 115765
On Feb 19, 6:44 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > cs_post...@hotmail.com wrote: > > 3) What I really hate though is the programmer's insistence on > > programming and then verifying the _unused_ bits. I don't usually > > have verification turned on during debug, and a programmer which > > doesn't give you a choice, plus is slow to start with... > > So how fast/slow are these devices to pgm ? > Next time I have to do one I'll try to remember to time it. My gut impression is that the little APA100 takes siginificantly longer then the conflig flash for moderately large altera parts with a lot of complied in data tables. I think my tossed-together embedded processor stub which a customized altera jam-player can control over a serial line to reconfigure a config flash in the field may go faster (its about 1/4 the speed of usb blaster) Actel has a presumably modified version of the altera jam player source code on their site (with attribution of course) and I'm thinking I may waste an afternoon on that and see if it isn't faster, given that I can probably force it not to verify.Article: 115766
i have a problem while configuring the virtex2 pro fpga in slave serial mode i am using platform flash RPOM of XC40FS serial flash prom. i am not getting the done pin high after configuration. my doubt is whether i have to connect the external ossilator (slave serial mode) in order to supply clk form PROM to CCLK of fpga. i read that if it is in slave select map mode and if the PROM is of parllel prom we need to supply clock though external ossilator what the case with serial prom. i am not getting the cclk when i am debugging with ossilocope. what is the major difference between master serial and slave serial (its with rescpect to clock that fpga provides clock when it is in master m9de and the prom or external ossilator supplies clock when it is in slave serial mode or any other particular difference is there.) regards srikArticle: 115767
Hi all I have a clock of 20Mhz on my board and I want Digital clock manager to generate a clock of 130MHz in my Xilinx Virtex-2 xc2v1000 FPGA. Now , the problem is that the DCM requires atleast 24Mhz input clock for proper working. Is there any solution other than changing the clock on board ?? regards MHArticle: 115768
On 19 Feb 2007 23:22:06 -0800, "mh" <moazzamhussain@gmail.com> wrote: >Hi all >I have a clock of 20Mhz on my board and I want Digital clock manager >to generate a clock of 130MHz in my Xilinx Virtex-2 xc2v1000 FPGA. >Now , the problem is that the DCM requires atleast 24Mhz input clock >for proper working. Is there any solution other than changing the >clock on board ?? > >regards >MH The limit of 24 MHz applies to the use of DCM as DLL. If your are going to use it multiply the frquency, then you are using CLKFX as output and the limits are 1MHz (LF mode) ansd 3 MHZ (HF mode), so you will have no problems with your design. Best regards, ZaraArticle: 115769
Hi, I have one of these with the S3-1000 aswell as the FX2 breadboard. Great little board. If you hadn't noticed, Digilent updated their MemUtil to V2.2. in the last few days. Now handles the flash roms on the Nexys board. Cheers, Red <cs_posting@hotmail.com> wrote in message news:1171748354.874055.271700@j27g2000cwj.googlegroups.com... > Recently I ordered a Nexys Spartan3-1000 / Cypress FX2 USB board from > Digilent for work. It's been fun and I may well buy one personally, > but like aways there are the suprises, the silly mistakes, and the 3 > am still-doesn't-work-yets. .......Article: 115770
Hello, I recently obtained a ML402 Virtex-4 SX35 evaluation board from Xilinx and would like to use it to communicate with some I2C slave devices. What is the proper way to do this? I am new to FPGA / HDL designing and feel a little lost. The data sheet for the ML402 states that there is an I2C bus that can be used to connect additional hardware. Is there a hardware master controller or do I still need to use a software I2C controller core? I'd really appreciate any help that I can get. Thanks in advance, MostafaArticle: 115771
"Aaron" <weirongj@gmail.com> writes: > Hi all, > > I want to evaluate the area and time cost of an intermediate product > on Xilinx FPGA. But the number of > output ports exceed number of I/O pins. (Actually there will be much > less outputs in the final product. ) > > But currently, I need test the intermediate product by using Xilinx > ISE. Can I add some ISE specific declaration to avoid the fully IO > mapping while I can still get the area and time cost reports? > Can you instantiate a Chipscope ILA (and ICON) and wire the IO up to that? That's worked for us in the past. Or send the output ports into a big shift register and shift them out of one pin, just to persuade the SW they get used? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 115772
On 20 Feb., 00:44, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > cs_post...@hotmail.com wrote: > > 3) What I really hate though is the programmer's insistence on > > programming and then verifying the _unused_ bits. I don't usually > > have verification turned on during debug, and a programmer which > > doesn't give you a choice, plus is slow to start with... > > So how fast/slow are these devices to pgm ? About 3min for an APA300 with Flashpro Lite. Other programmers could be faster, never used Flashpro or Silicon Sculpture for APA. bye ThomasArticle: 115773
Erik Widding wrote: > I found the documentation that I needed... turns out it was an RTFM > question for the most part. > > Though, if anybody has any direct experience with MIG 1.6, DDR2 x16 > used in V4, I would love to hear how it went. We have an SX55 design with DDR2 mini-DIMM (72-bit data path). I used MIG 1.5 instead of rolling my own controller. I only had a few problems; I had to play with the clock phases of commands and data to get the read data to come back at the right time. One thing I would recommend is to change out the FIFO16 in the command path. It had a tendency to go empty but not update the empty flag, so it would execute the same command over and over again. Replacing the FIFO with one created by CoreGen was an easy fix. The downside to the MIG is that they only allow one bank to be open at a time. Peter hinted that the V5 MIG designs will allow multiple banks to be open. I'm hoping that this migrates to teh other designs. --- Joe Samson Pixel VelocityArticle: 115774
<cs_posting@hotmail.com> wrote in message news:1171946369.780602.304170@t69g2000cwt.googlegroups.com... > On Feb 19, 10:45 am, "cpope" <cep...@nc.rr.com> wrote: > > I need a production station that can (a) burn my xilinx xf08p serial prom > > and (b) xdownload some code to be burned to flash. I currently have to use > > Impact for the prom and XMD for the flash. I don't want to pay for a whole > > extra EDK and ISE just for this. Can anyone suggest another solution? > > For the serial prom, have you tried impact from the downloadable, no- > cost webpack version of ISE? While the bitstream generation tools in > that won't handle the larger parts, I'd be a little suprised if they > limited impact. Or if they did, how about digilent's USB cable and > software, for much less than Xilinx's cable (think "export" can do a > prom via and svf file, but it would be worth double checking)? Thanks I'll try that. > > As for the flash rom, I don't know what is most cost effective (what > your time making it work is worth), but cheapest hardware would > probably be to put some function in your fpga that can accept data > over an external interface (spi?) and program it. Perhaps a small > design that you download directly to the FPGA temporarily? > Unfortunately I only have low speed serial links so it woudl take about an hour to transfer the flash contents. Thanks, Clark
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z