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Hi all, I have created a peripheral and attached it to the OPB bus. This peripheral is composed of a controller and also BRAM block directly attached to it. There is no bus between the controller and the BRAM block. The BRAM block is a 32KB block which is composed of 16 RAMB16 primitives. I have synthesized the peripheral which happens with out a glitch and then generated the netlist followed by the bitstream generation. All this happens but then the design report does not show that the peripheral is using the RAMB16 primitive. Someone please tell me what is wrong here. Also is there any example code which could guide me about how to use RAMB16's. I am using XPS 8.2i and ISE 8.2i and a virtex-4 board. Thanks, BhanuArticle: 116501
Ben Popoola wrote: > Hi, > I have a PCB design with a FPGA and other devices that require a clock > input. Is it a good idea to first feed a single clock into the FPGA and > then through the FPGA distribute this clock to the other devices? > > Ben This depends on whether or not you can live with anywhere from no less than 30ps to possibly over 200ps of *extra* jitter and many more picoseconds if you are concerned about skew between replicated clocks. If the other devices can live with ~300ps clock jitter, it should work with all current FPGAs with minimal (if any) hassle. If you need something better than that, you can find some VCO ICs capable of generating low-skew clocks with down to sub-picosecond jitter, so finding ones with less than 100ps jitter+skew should be easy and inexpensive.Article: 116502
Bhanu Chandra <vbhanu@gmail.com> wrote: > Hi all, > I have created a peripheral and attached it to the OPB bus. This > peripheral is composed of a controller and also BRAM block directly > attached to it. There is no bus between the controller and the BRAM > block. The BRAM block is a 32KB block which is composed of 16 RAMB16 > primitives. > I have synthesized the peripheral which happens with out a glitch and > then generated the netlist followed by the bitstream generation. All > this happens but then the design report does not show that the > peripheral is using the RAMB16 primitive. Someone please tell me what > is wrong here. > Also is there any example code which could guide me about how to use > RAMB16's. > I am using XPS 8.2i and ISE 8.2i and a virtex-4 board. Read the synthesis report with care. It looks like the all the blockram and the surrounding circuits were removed because the output of the circuit is not used or the input is perhaps stable. Some typo in the instantiation may cause this. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 116503
hi, Pile of data books in search of a good home... I have a collection of perhaps 80 or 100 data books for various logic, CPU and DSP devices and device families, mostly dating from around 1988-1994 but with a few earlier and later than this. Don't expect them to be any use for real day-to-day work; they describe devices almost all of which are entirely obsolete. Some are real curiosities - the first and, I think, only data book for Crosspoint FPGAs, for example. Others are more mundane: Philips 74FTTL and suchlike. With a heavy heart, I now think it's time to part with them. I had dreams of settling down and writing some kind of history of the development of logic design over the 1970-2000 period, but by the time I have enough leisure to do it I suspect I won't have the skill or stamina. So, they're yours if you can offer them a loving home and can work out with me how to get them from south-east England to you without it costing me anything. cheers -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 116504
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message news:4mj8v2lk9rr5i7gibf0lgvtk7hnts33ruq@4ax.com... > hi, > > Pile of data books in search of a good home... > > I have a collection of perhaps 80 or 100 data books for various > logic, CPU and DSP devices and device families, mostly dating > from around 1988-1994 but with a few earlier and later than this. > > Don't expect them to be any use for real day-to-day work; > they describe devices almost all of which are entirely obsolete. > > Some are real curiosities - the first and, I think, only data book > for Crosspoint FPGAs, for example. Others are more mundane: > Philips 74FTTL and suchlike. With a heavy heart, I now think > it's time to part with them. I had dreams of settling down and > writing some kind of history of the development of logic design > over the 1970-2000 period, but by the time I have enough > leisure to do it I suspect I won't have the skill or stamina. > > So, they're yours if you can offer them a loving home and > can work out with me how to get them from south-east > England to you without it costing me anything. > > cheers > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.bromley@MYCOMPANY.com > http://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. Hi Jonathan, Do you have a list or good enough picture somewhere on the web? I'd like to have a peek and see if there's anything I'd like (if you don't mind splitting up the collection). Would paying shipment by Paypal work for you? Alvin.Article: 116505
Xilinx has the ridiculous peculiarity of requiring sized cases in a
case statement.
I allow users of my module to set parameters that are used to
calculate other local parameters, and those local parameters are then
used in several case statements as the cases.
How am I supposed to meet XST requirements?
Will requiring that all parameter definitions be sized do the trick?
I think not, since one of my calculations is:
localparam LOCAL = PARAM - 1;
Is Xilinx also too stupid to use the size given when PARAM is set?
Any help would be appreciated.
PS
How can anybody put up with Xilinx? In my experience, their software
has been utter trash.
Article: 116506Jonathan Bromley wrote: > hi, > > Pile of data books in search of a good home... > > I have a collection of perhaps 80 or 100 data books for various > logic, CPU and DSP devices and device families, mostly dating > from around 1988-1994 but with a few earlier and later than this. > > Don't expect them to be any use for real day-to-day work; > they describe devices almost all of which are entirely obsolete. > > Some are real curiosities - the first and, I think, only data book > for Crosspoint FPGAs, for example. Others are more mundane: > Philips 74FTTL and suchlike. With a heavy heart, I now think > it's time to part with them. I had dreams of settling down and > writing some kind of history of the development of logic design > over the 1970-2000 period, but by the time I have enough > leisure to do it I suspect I won't have the skill or stamina. > > So, they're yours if you can offer them a loving home and > can work out with me how to get them from south-east > England to you without it costing me anything. > > cheers There's always ebay. I suspect you might have one or two books in the collection that someone might want for nostalgia or something. I tossed my collection dating from about the same time period...including that same crosspoint data book...a few years ago when I was remodeling my office. I did save a few books like the TRW data book with DSP components, a hardcover 1976 Signetics data book and a few others that I had a particular attachment to. I reduced four full bookcases of outdated data books to half a shelf worth. Mine went to the recycling center.Article: 116507
Harry Stello wrote: >Hello, > >I am trying to debug the sdram interface on a custom board I built. I need >to look at some of the internal signals of the PLB_DDR interface. I >modified the VHDL code and the .mpd file. However, the changes that I made >to the .mpd file don't show up in EDK. Has anyone seen this before? I know >I modified the correct mpd because when I select view mpd in EDK, the >changes that I made show up. > >I have created custom peripherals before, and changes that I've made to >other non-xilinx created mpd files show up in EDK. So is this a known issue >with xilinx predefined mpd files? > >Thanks, > >Harry > > > > What version of EDK are you using. Starting EDK 8.2, there is a __MpdDataBase.txt file in the pcores area of Xilinx installation area that's essentially a cat of all the MPD files. So, unless you also make changes to this file, XPS won't see the changes in MPD. The recommended way is to make a local copy of the desired pcore and start making changes. Thanks, AmitArticle: 116508
Hi people, In last my design, I made a fpga board using IC xc3s400. Now i would like to modify it some following things. I want to add a part into Fpga board. I want to use a chip W5100 to comunicated between FPGA board with ethernet. Do any one can give me some ideas? I hope that someone worked with this chip and got some experienced. please show me. i lloking forward hearing from people soon Him LamArticle: 116509
lingwitt wrote: > Xilinx has the ridiculous peculiarity of requiring sized cases in a > case statement. > > I allow users of my module to set parameters that are used to > calculate other local parameters, and those local parameters are then > used in several case statements as the cases. > > How am I supposed to meet XST requirements? > > Will requiring that all parameter definitions be sized do the trick? > I think not, since one of my calculations is: > > localparam LOCAL = PARAM - 1; > > Is Xilinx also too stupid to use the size given when PARAM is set? > Any help would be appreciated. > > PS > How can anybody put up with Xilinx? In my experience, their software > has been utter trash. Dimension everything: localparam [3:0] LOCAL = PARAM - 1;Article: 116510
On Mar 12, 1:05 am, John_H <newsgr...@johnhandwork.com> wrote: > lingwitt wrote: > > Xilinx has the ridiculous peculiarity of requiring sized cases in a > > case statement. > > > I allow users of my module to set parameters that are used to > > calculate other local parameters, and those local parameters are then > > used in several case statements as the cases. > > > How am I supposed to meet XST requirements? > > Dimension everything: > > localparam [3:0] LOCAL = PARAM - 1; Excellent! Thank you very much. I had no idea that parameters could be dimensioned in this way. Most language guides are by example rather than rule, so I hadn't come across this before. Thanks again!Article: 116511
Thanks for the reply! Sorry it took me a while to get back, I haven't had time to check the newsgroup for a couple days. I'm using a Digilent Nexys board with a Spartan3 1000k gate chip, no multiplication, just some DFFs, MUXs, decoders, and simple logic. WebPack 9.1i on this computer. Steve davide wrote: > Steve, > > Can you tell me a little bit more about what device you are targeting and > the version of WebPACK you are using. Are you using any multiplier blocks > or doing any multiplication operations and pipelining the output? > > -David > > > > "Steve Battazzo" <thesteveman_ice9@yahoo.co.jp> wrote in message > news:m6KdnZIfoIUuVnLYnZ2dnUVZ_rmdnZ2d@comcast.com... >> At the XST-synthesize stage, I'm getting this weird warning: >> "Property use_dsp48" is not applicable for this technology. >> I don't have anything in my code that I know of that calls for any such >> thing.. it doesn't affect the program actually running on my board, but >> I'm curious anyway. >> >> Anyone know what this means? >> >> Thanks, >> >> Steve > >Article: 116512
On Mar 12, 1:40 am, "lingwitt" <lingw...@gmail.com> wrote: > On Mar 12, 1:05 am, John_H <newsgr...@johnhandwork.com> wrote: > > > lingwitt wrote: > > > Xilinx has the ridiculous peculiarity of requiring sized cases in a > > > case statement. > > > > I allow users of my module to set parameters that are used to > > > calculate other local parameters, and those local parameters are then > > > used in several case statements as the cases. > > > > How am I supposed to meet XST requirements? > > > Dimension everything: > > > localparam [3:0] LOCAL = PARAM - 1; > > Excellent! > > Thank you very much. > > I had no idea that parameters could be dimensioned in this way. > Most language guides are by example rather than rule, > so I hadn't come across this before. > > Thanks again! Well of course! There it is right there! Right in the BNF grammar specification! ;-)Article: 116513
Gentlemen, Sorry if this is the wrong newsgroup for this. If someone can suggest a more appropriate forum, I'd be quite grateful. I'm looking for some help bringing up our first PCIe product. We're using a Philips PX1011A PHY and a Xylinx Virtix-3 FPGA. We think we've followed the layout specs in the Philips design notes to the letter, but after two PCB revisions, we just can't get it to lock on. We've got some urgent calls into Philips' apps engineers, but we haven't heard back from them yet. So, I'm looking for a contractor or a vendor who's dealt with this PHY in particular, and knows what the gotchas are. If push comes to shove, we can punt and go with an Intel or a TI part instead, but I'd like to have someone who's been through the process of bringing up a PCIe product before to help us out with this. If this is up your alley, please drop me a note at jcr at mac dot com, and let me know what you've done and what your rate is. BTW, I really only want to hear from people with the skills. No headhunters, please. Thanks, -jcr John C. Randolph, VP, Engineering Stealth Imaging, LLC. <jcr@stealthimaging.com>Article: 116514
On Sun, 11 Mar 2007 20:11:12 +0100, "Alvin Andries" <Alvin_Andries.no_spam@no.spam.versateladsl.be> wrote: >> Pile of data books in search of a good home... ... >Do you have a list or good enough picture somewhere on the web? I'd like to >have a peek and see if there's anything I'd like (if you don't mind >splitting up the collection). Would paying shipment by Paypal work for you? I'll post a complete list as soon as I get back home on Thursday. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 116515
Hi newsgroup,
As shown in the VHDL code I am feeding two flip flop chains
with the same input. The chains use complementary clocks (200Mhz).
In the process "rise_fall" I do some combinational logic
to detect rising and falling of the sampled input.
Now I want to use one of the combinational signals as a clock
in a process "clksel" to sample the second combinationl signal.
Speaking in terms of functional simulation the function
of the hardware description is the following:
The signal which gets active first
is used for ClockSel.
The output ClockSel is then used to feed a DCS module.
The problem I see in this hardware description is that
the clock in the process "clksel" is a gated clock.
What is your opinion about the desription ? How can
I modify it to make it synthesizable ? Is there some
need for additional constraints ?
library ieee;
use ieee.std_logic_1164.all;
entity ana is
port( Reset : in std_logic;
Clk : in std_logic;
DataIn : in std_logic;
ClockSel : out std_logic
);
end ana;
architecture arch_ana of ana is
signal r_p1, r_p2, r_p3 : std_logic;
signal f_p1, r_p2, r_p3 : std_logic;
signal trig_rise, trig_fall : std_logic;
begin
------------------------------------
sync_redge: process(Reset, Clk)
begin
if Reset='1' then
r_p1 <= '0';
r_p2 <= '0';
r_p3 <= '0';
elsif rising_edge(Clk) then
r_p1 <= DataIn;
r_p2 <= r_p1;
r_p3 <= r_p2;
end if;
end process sync_redge;
------------------------------------
sync_fedge: process(Reset, Clk)
begin
if Reset='1' then
f_p1 <= '0';
f_p2 <= '0';
f_p3 <= '0';
elsif falling_edge(Clk) then
f_p1 <= DataIn;
f_p2 <= f_p1;
f_p3 <= f_p2;
end if;
end process sync_fedge;
------------------------------------
rise_fall: process(r_p2, r_p3,
f_p2, f_p3)
begin
trig_rise <= ((not r_p3) AND r_p2);
trig_fall <= ((not_f_p3) AND f_p2);
end process rise_fall;
------------------------------------
-- ?????????????????????????????????
clksel: process(Reset, trig_fall)
begin
if Reset='1' then
ClockSel <= '0';
elsif rising_edge(trig_fall) then
ClockSel <= trig_rise;
end if;
end process clksel;
end arch_ana;
Article: 116516In article <g76av2padktldg73o3oj7akrqd805cn4q6@4ax.com>, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote: > I'll post a complete list as soon as I get back home on Thursday. Hello stranger, (to s.e.d these days anyway). -- Tony Williams.Article: 116517
On Mar 11, 11:13 pm, Uwe Bonnes <b...@hertz.ikp.physik.tu- darmstadt.de> wrote: > Bhanu Chandra <vbh...@gmail.com> wrote: > > Hi all, > > I have created a peripheral and attached it to the OPB bus. This > > peripheral is composed of a controller and also BRAM block directly > > attached to it. There is no bus between the controller and the BRAM > > block. The BRAM block is a 32KB block which is composed of 16 RAMB16 > > primitives. > > I have synthesized the peripheral which happens with out a glitch and > > then generated the netlist followed by the bitstream generation. All > > this happens but then the design report does not show that the > > peripheral is using the RAMB16 primitive. Someone please tell me what > > is wrong here. > > Also is there any example code which could guide me about how to use > > RAMB16's. > > I am using XPS 8.2i and ISE 8.2i and a virtex-4 board. > > Read the synthesis report with care. It looks like the all the blockram and > the surrounding circuits were removed because the output of the circuit is > not used or the input is perhaps stable. Some typo in the instantiation may > cause this. > > Bye > -- > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Could someone please share a sample code which instantiates the BRAM blocks? Thanks, BhanuArticle: 116518
Bhanu Chandra <vbhanu@gmail.com> wrote:
> Could someone please share a sample code which instantiates the BRAM
> blocks?
Here I use one block as 8/32 Bit:
/*
* Tie unused data/address High (ug331, p.155
* Readout data is in upper portion
*/
RAMB16_S9_S36 ram1(
.DOA(scaler_dout),
.DOB(scaler_read_data),
.DOPA(),
.DOPB(),
.ADDRA({{3{1'b1}},byteaddress[7:0]}),
.ADDRB({{2{1'b1}},scaler_addr}),
.CLKA(clk),
.CLKB(clk),
.DIA({8{1'b1}}),
.DIB(scaler_write_data),
.DIPA(4'b1),
.DIPB(4'b1),
.ENA((address == `SCALER)),
.ENB(scaler_ena),
.SSRA(1'b0),
.SSRB(scaler_rst_cycle),
.WEA(1'b0),
.WEB(scaler_wea)
);
The 8-bit side only reads the ram
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 116519Hi All, In the process of creating a custom board definition file for a new board I've developed I've discovered a few things about the naming and location of the .kbd files. Here's the file location: ~/EDKLibs/MyProcessorIP/boards/RISATest_Rev1/data/RISATest_Rev1_v2_2_0.xbd Firstly, it seems the kbd filename must end in _v2_2_0. Any ideas what that's all about? Secondly, the board directory (RISATest_Rev1), must match the kbd filename minus the _v2_2_0 part. I couldn't find anything in the docs explaining these requirements. Has anyone else? Cheers AndyArticle: 116520
This is what I have, please tell me if something seems wrong here.
RAMB16_S36_S36 CAC1 (.DOA (DOA_CAC1),
.DOB (DOB_CAC1),
.DOPA (DOPA_CAC1),
.DOPB (DOPB_CAC1),
.ADDRA (ADDRA_CAC1),
.ADDRB (ADDRB_CAC1),
.CLKA (Bus2IP_Clk),
.CLKB (Bus2IP_Clk),
.DIA (DIA_CAC1),
.DIB (DIB_CAC1),
.DIPA (DIPA_CAC1),
.DIPB (DIPB_CAC1),
.ENA (ENA_CAC1),
.ENB (ENB_CAC1),
.SSRA (1'b0),
.SSRB (1'b0),
.WEA (WEA_CAC1),
.WEB (WEB_CAC1));
defparam CAC1.INIT_00 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
Thanks,
Bhanu
Uwe Bonnes wrote:
> Bhanu Chandra <vbhanu@gmail.com> wrote:
>
> > Could someone please share a sample code which instantiates the BRAM
> > blocks?
>
> Here I use one block as 8/32 Bit:
> /*
> * Tie unused data/address High (ug331, p.155
> * Readout data is in upper portion
> */
> RAMB16_S9_S36 ram1(
> .DOA(scaler_dout),
> .DOB(scaler_read_data),
> .DOPA(),
> .DOPB(),
> .ADDRA({{3{1'b1}},byteaddress[7:0]}),
> .ADDRB({{2{1'b1}},scaler_addr}),
> .CLKA(clk),
> .CLKB(clk),
> .DIA({8{1'b1}}),
> .DIB(scaler_write_data),
> .DIPA(4'b1),
> .DIPB(4'b1),
> .ENA((address == `SCALER)),
> .ENB(scaler_ena),
> .SSRA(1'b0),
> .SSRB(scaler_rst_cycle),
> .WEA(1'b0),
> .WEB(scaler_wea)
> );
>
> The 8-bit side only reads the ram
>
> --
> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 116521
This is what I have, please tell me if something seems wrong here
since this is the code that does not make BRAM usage appear in the
design report.
RAMB16_S36_S36 CAC1 (.DOA (DOA_CAC1),
.DOB (DOB_CAC1),
.DOPA (DOPA_CAC1),
.DOPB (DOPB_CAC1),
.ADDRA (ADDRA_CAC1),
.ADDRB (ADDRB_CAC1),
.CLKA (Bus2IP_Clk),
.CLKB (Bus2IP_Clk),
.DIA (DIA_CAC1),
.DIB (DIB_CAC1),
.DIPA (DIPA_CAC1),
.DIPB (DIPB_CAC1),
.ENA (ENA_CAC1),
.ENB (ENB_CAC1),
.SSRA (1'b0),
.SSRB (1'b0),
.WEA (WEA_CAC1),
.WEB (WEB_CAC1));
defparam CAC1.INIT_00 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
Thanks,
Bhanu
Uwe Bonnes wrote:
> Bhanu Chandra <vbhanu@gmail.com> wrote:
>
> > Could someone please share a sample code which instantiates the BRAM
> > blocks?
>
> Here I use one block as 8/32 Bit:
> /*
> * Tie unused data/address High (ug331, p.155
> * Readout data is in upper portion
> */
> RAMB16_S9_S36 ram1(
> .DOA(scaler_dout),
> .DOB(scaler_read_data),
> .DOPA(),
> .DOPB(),
> .ADDRA({{3{1'b1}},byteaddress[7:0]}),
> .ADDRB({{2{1'b1}},scaler_addr}),
> .CLKA(clk),
> .CLKB(clk),
> .DIA({8{1'b1}}),
> .DIB(scaler_write_data),
> .DIPA(4'b1),
> .DIPB(4'b1),
> .ENA((address == `SCALER)),
> .ENB(scaler_ena),
> .SSRA(1'b0),
> .SSRB(scaler_rst_cycle),
> .WEA(1'b0),
> .WEB(scaler_wea)
> );
>
> The 8-bit side only reads the ram
>
> --
> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 116522
On Mar 12, 4:04 pm, "Bhanu Chandra" <vbh...@gmail.com> wrote:
> This is what I have, please tell me if something seems wrong here
> since this is the code that does not make BRAM usage appear in the
> design report.
>
> RAMB16_S36_S36 CAC1 (.DOA (DOA_CAC1),
> .DOB (DOB_CAC1),
> .DOPA (DOPA_CAC1),
> .DOPB (DOPB_CAC1),
> .ADDRA (ADDRA_CAC1),
> .ADDRB (ADDRB_CAC1),
> .CLKA (Bus2IP_Clk),
> .CLKB (Bus2IP_Clk),
> .DIA (DIA_CAC1),
> .DIB (DIB_CAC1),
> .DIPA (DIPA_CAC1),
> .DIPB (DIPB_CAC1),
> .ENA (ENA_CAC1),
> .ENB (ENB_CAC1),
> .SSRA (1'b0),
> .SSRB (1'b0),
> .WEA (WEA_CAC1),
> .WEB (WEB_CAC1));
>
> defparam CAC1.INIT_00 =
> 256'h0000000000000000000000000000000000000000000000000000000000000000;
>
> Thanks,
> Bhanu
>
> Uwe Bonnes wrote:
> > Bhanu Chandra <vbh...@gmail.com> wrote:
>
> > > Could someone please share a sample code which instantiates the BRAM
> > > blocks?
>
> > Here I use one block as 8/32 Bit:
> > /*
> > * Tie unused data/address High (ug331, p.155
> > * Readout data is in upper portion
> > */
> > RAMB16_S9_S36 ram1(
> > .DOA(scaler_dout),
> > .DOB(scaler_read_data),
> > .DOPA(),
> > .DOPB(),
> > .ADDRA({{3{1'b1}},byteaddress[7:0]}),
> > .ADDRB({{2{1'b1}},scaler_addr}),
> > .CLKA(clk),
> > .CLKB(clk),
> > .DIA({8{1'b1}}),
> > .DIB(scaler_write_data),
> > .DIPA(4'b1),
> > .DIPB(4'b1),
> > .ENA((address == `SCALER)),
> > .ENB(scaler_ena),
> > .SSRA(1'b0),
> > .SSRB(scaler_rst_cycle),
> > .WEA(1'b0),
> > .WEB(scaler_wea)
> > );
>
> > The 8-bit side only reads the ram
>
> > --
> > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de
>
> > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
> > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Seems like this is not the issue. What happened is that I had created
a .h file within which I was doing all the instantiation. Possible
that it was not including the file? I am getting a little confused
here, XPS does not seem to support include directive of verilog. Has
anyone tried it? I have now included the instantiation also in the
main user_logic file, it now fails to resolve a function. Please
mention if someone has in the past experienced the same problems.
Thanks,
Bhanu
Article: 116523On 2007-03-12, Pablo <pbantunez@gmail.com> wrote: > How can I use the Power PC in a non xilinx platform? I cannot use EDK > from Xilinx. It is possible to use the PowerPC without having access to the EDK. I have done so myself and I know others have done so as well. In theory it is just a matter of reading the documentation about the PowerPC processor that is supplied by Xilinx, instantiate it correctly and connect memories containing a boot monitor to the OCM bus. In practice you really want to have a version of Modelsim (or some other simulator) that can handle SmartModels so that you are able to simulate the PPC405 block. Otherwise you are going to have troubles figuring out why nothing is working. Even so the SmartModel is a bit quirky to use and if something is not configured correctly you tend to get X on all outputs from it if I remember correctly. I've been thinking abot posting some code for this but I haven't gotten around to doing that yet. And truly, if you are going to do any commercial development on the board you are probably better off with the EDK. Perhaps you can save some money if you don't use the EDK and you don't use the PLB bus on the processor (the OCM and DCR bus are quite easy to interface to) but if you need for example an external SDRAM or DDR memory component you will save a lot of development/debugging time/money by simply using the EDK provided components. I'm speaking from experience here, I've spent some time on using the opencores DDR memory controller in a PowerPC system as a hobby project and getting it to the point that I could run programs from it reliably was not very fun. On the other hand, getting the system to the point that I could run the monitor off OCM-connected memories was quite fun though :) Now, if I could just get Linux to boot on the system I could do some really fun stuff... As to the question of erasing the PowerPC, no you can't. The PowerPC is located on the Virtex II Pro chip and your only choice is whether to use it or not. /AndreasArticle: 116524
On Mar 12, 1:57 am, "lingwitt" <lingw...@gmail.com> wrote: > > I had no idea that parameters could be dimensioned in this way. > > Most language guides are by example rather than rule, > > so I hadn't come across this before. > > > Thanks again! > > Well of course! > > There it is right there! Right in the BNF grammar specification! > > ;-) It would seem that this wasn't possible until Verilog-2001. Perhaps this is what the XST documentation means when it cryptically boasts about supporting "N sized parameters".
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