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Hi, this is the first time I work with a FPGA with a processor embeded. The FPGA is Xilinx Virtex II Pro, and the board belongs to Sundance. They say that FPGA has a Embeded Processor (POWERPC) and some communication modules. I need to know if I configure the FPGA with a new bitstream, could I erase these modules and the processor?. How can I use the Power PC in a non xilinx platform? I cannot use EDK from Xilinx. Have a nice day and thanks for your help. PabloArticle: 116526
On Mar 12, 5:49 am, Andrew Greensted <ajg...@ohm.york.ac.uk> wrote: > Hi All, > > In the process of creating a custom board definition file for a new > board I've developed I've discovered a few things about the naming and > location of the .kbd files. > > Here's the file location: > > ~/EDKLibs/MyProcessorIP/boards/RISATest_Rev1/data/RISATest_Rev1_v2_2_0.xbd > > Firstly, it seems the kbd filename must end in _v2_2_0. Any ideas what > that's all about? > > Secondly, the board directory (RISATest_Rev1), must match the kbd > filename minus the _v2_2_0 part. > > I couldn't find anything in the docs explaining these requirements. Has > anyone else? > > Cheers > Andy I am assuming that you meant .xbd files, not .kbd files. Am I correct, or are .kbd files something new? The documentation you want to read for creating .xbd files as well as the rest of the data files that go with cores is $EDK/doc/psm_rm.pdf, or the "Platform Specification Format Reference Manual". The information on how to create the .xbd files was a bit sparse when I created them for our cards a few versions of EDK back. It helps that the files are plain text so that you can look at all of the examples of other .xbd files in $EDK/board/Xilinx/boards/*. The psm_rm.pdf does mention the naming conventions for the directory and the .xbd file. It is on page 128 of v3.1. Regards, John McCaskill www.fastertechnology.comArticle: 116527
Hi all I'm absolutely new to FPGAs, in fact my work is much more related with the SW than with the HW, so I need to solve a problem that ideally I was not targeted to. The issue is this: I have to estimate (roughly) the number of FPGAs needed to support a typical signal processing algorithm, steps are as follows, always in single-precision: 1.16k complex samples FFT 2. 16k complex vector multiplication 3. 16k complex samples IFFT 4. 16k complex vector multiplication 5. 16 k complex vector sum The idea is to know how many FPGAs will cover this kind of processing in a given time, to compare with different types of processors. Por the later, it is really easy just counting number of operations in GFLOPs, but with hardware devices I am getting a lot of trouble, since I don't have a clear understanding on what should I count. Please, give me a hand! RubenArticle: 116528
On Mar 12, 1:35 pm, rbbla...@gmail.com wrote: [...] > > The issue is this: I have to estimate (roughly) the number of FPGAs > needed to support a typical signal processing algorithm, steps are as > follows, always in single-precision: > > 1.16k complex samples FFT > 2. 16k complex vector multiplication > 3. 16k complex samples IFFT > 4. 16k complex vector multiplication > 5. 16 k complex vector sum > > The idea is to know how many FPGAs will cover this kind of processing > in a given time, to compare with different types of processors. With hardware implementation you will need to specify the time you want this algorithm being processed in. It will make a difference in the implementation. The faster you want to go, the more you need to implement in parallel and the more resources you will need. For the FFT you can request a design fit from here: http://www.dilloneng.com/ip/fft/fftipfit_cpt But that is a specific design fit for their FFT. So you might find other vendors that get you a different fit. Cheers, GuenterArticle: 116529
>You can use the FPGA editor that is part of ISE to look at where the >EMAC and PPC are located with respect to the pins/pads for the package >that you are using. John, Just to be on the save side, and sorry if this is a dumb question, but with "FPGA editor" you mean the "Pinout and Area Constraints Editor (PACE)" ? If not, where do I find the FPGA editor, or better said, how do I invoke it? TIA MarkusArticle: 116530
There is additional information needed for this evaluation: - how often do you need a result (throughput and latency)? - what is the data type (integer? float? precision?) Unlike CPUs FPGAs have no native datatypes. For cryptographic applications you might want to run an FFT on vectors of single bits. For DNA matching you might have 2-bit or 4-bit data types. For DSP 18-bit or 36-bit integers are a common choice for Xilinx FPGAs. The algorithm that you describe implemented serially on 1-bit data would use 1% of a small FPGA and run for several hundred thousand clock cycles. Alternatively on a large FPGA OTOH you can perform a few hundred 18- bit x 18-bit Multiplications per cycle. Kolja Sulimma On 12 Mrz., 13:35, rbbla...@gmail.com wrote: > Hi all > > I'm absolutely new to FPGAs, in fact my work is much more related with > the SW than with the HW, so I need to solve a problem that ideally I > was not targeted to. > > The issue is this: I have to estimate (roughly) the number of FPGAs > needed to support a typical signal processing algorithm, steps are as > follows, always in single-precision: > > 1.16k complex samples FFT > 2. 16k complex vector multiplication > 3. 16k complex samples IFFT > 4. 16k complex vector multiplication > 5. 16 k complex vector sum > > The idea is to know how many FPGAs will cover this kind of processing > in a given time, to compare with different types of processors. Por > the later, it is really easy just counting number of operations in > GFLOPs, but with hardware devices I am getting a lot of trouble, since > I don't have a clear understanding on what should I count. > > Please, give me a hand! > > RubenArticle: 116531
Markus Fras wrote: > Well, Xilinx CoreGen created two additional files: > > fifo18w16d_fifo_generator_v2_3_xst_1.ngc > fifo18w16d_fifo_generator_v2_3_xst_1_blkmemdp_v6_2_xst.edn > > Even if I include both of the, I still get the same error message. > > The solution is to add the output directory of CoreGen to ngdbuild with > the switch `-sd'. Then you need only to include the *.v file in the > synthesis. Well, this sets the macro search path for the entire project, and ngdbuild just takes whatever it needs from there. Works fine if all your cores are in the same directory, but if they're scattered over several folders, the only way is to add them all to the project. If you don't set the macro search path explicitely, ngdbuild assumes the implementation directory as source directory for all cores. In this case, Precision has to copy the corresponding files there, which it should do if you add them to the project with the "-exclude"-option, that's what that's for. Don't know why that doesn't work for you, but I've never had any problems there, as long as I included all the files CoreGen produces. -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 116532
On Mar 12, 8:12 am, Markus Zingg <m.zi...@nct.ch> wrote: > >You can use the FPGA editor that is part of ISE to look at where the > >EMAC and PPC are located with respect to the pins/pads for the package > >that you are using. > > John, > > Just to be on the save side, and sorry if this is a dumb question, but > with "FPGA editor" you mean the "Pinout and Area Constraints Editor > (PACE)" ? > > If not, where do I find the FPGA editor, or better said, how do I > invoke it? > > TIA > > Markus No, I did not mean the PACE tool, but I think it might show you what you want to know. I have not used PACE in quite a while now. I am working in EDK so I generate area group constraints with TCL scripts that are part of my core designs. On a Windows computer, the FPGA editor is at: Start->All Programs->Xilinx ISE 8.2i->Accessories->FPGA Editor This should be the same menu that has the PACE tool in it. I am not sure, but I do not think that the FPGA Editor is not part of the Web Pack version of the tools if that is what you are using. I have the ISE Foundation version. Regards, John McCaskill www.fastertechnology.comArticle: 116533
On 2007-03-10 16:09:43 -0800, "Peter Alfke" <alfke@sbcglobal.net> said: > Rest assured that the offensive paragraph will be killed. Actually, that just looked like a standard media release clause, but normally you'd ask a speaker to sign it, not an attendee. I signed forms with similar language when I was a presenter at Apple's WWDC. -jcrArticle: 116534
Hi all, I have a peripheral written in verlog, this is getting synthesized by ISE but then when I generate netlist using XPS it fails to resolve a function symbol. Could someone please explain what could be wrong here? Thanks, BhanuArticle: 116535
John McCaskill wrote: > On Mar 12, 5:49 am, Andrew Greensted <ajg...@ohm.york.ac.uk> wrote: >> Hi All, >> >> In the process of creating a custom board definition file for a new >> board I've developed I've discovered a few things about the naming and >> location of the .kbd files. >> >> Here's the file location: >> >> ~/EDKLibs/MyProcessorIP/boards/RISATest_Rev1/data/RISATest_Rev1_v2_2_0.xbd >> >> Firstly, it seems the kbd filename must end in _v2_2_0. Any ideas what >> that's all about? >> >> Secondly, the board directory (RISATest_Rev1), must match the kbd >> filename minus the _v2_2_0 part. >> >> I couldn't find anything in the docs explaining these requirements. Has >> anyone else? >> >> Cheers >> Andy > > > > I am assuming that you meant .xbd files, not .kbd files. Am I correct, > or are .kbd files something new? > > > The documentation you want to read for creating .xbd files as well as > the rest of the data files that go with cores is $EDK/doc/psm_rm.pdf, > or the "Platform Specification Format Reference Manual". > > The information on how to create the .xbd files was a bit sparse when > I created them for our cards a few versions of EDK back. It helps > that the files are plain text so that you can look at all of the > examples of other .xbd files in $EDK/board/Xilinx/boards/*. > > The psm_rm.pdf does mention the naming conventions for the directory > and the .xbd file. It is on page 128 of v3.1. > > Regards, > > John McCaskill > www.fastertechnology.com > Hi John, Thanks for the info. Yes I did mean .xbd. The psm_rm.pdf file helps a lot Cheers AndyArticle: 116536
Bhanu Chandra <vbhanu@gmail.com> wrote: ... > Seems like this is not the issue. What happened is that I had created > a .h file within which I was doing all the instantiation. Possible > that it was not including the file? I am getting a little confused > here, XPS does not seem to support include directive of verilog. Has > anyone tried it? I have now included the instantiation also in the > main user_logic file, it now fails to resolve a function. Please > mention if someone has in the past experienced the same problems. Make sure it gets included. The "Device utilization summary" after running XST should read: Selected Device : 3s200pq208-4 ... Number of BRAMs: 1 out of 12 8% ... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 116537
Sounds interesting to me. Would you like to contribute this or make a piece of commercial software out of it? I guess it would by no problem for the -> small companies to spende some Cents on a tool which saves hours of programming time over the months. Currently I am handling conditional synthesis (parameters mostly) with Excel / Access :-) Thanks J., currently working for a "small company"Article: 116538
Andreas Ehliar wrote: > I've been wondering if someone else has noticed that RLOCs > does not seem to be working very well in ISE 8.2 and 9.1? > > Currently I'm experimenting with a project where the RLOCs > are working ok for smaller submodules but when I try to > instantiate these submodules into a larger design in > several places the RLOCs are lost in some way. > > In ISE 8.1 everything is working as expected though. > > /Andreas My guess is you have an RPM that straddles a DSP or BRAM column. There is a bug in the mapper that has been there since 6.3 that messes up the grid mapping when an RPM has elements on both sides of a non-LUT column. The result is if you have a RAM16, SRL16 or other element that requires a LUT memory resource and it is placed on the opposite side of a BRAM or DSP column relative to the RLOC origin, it will fail to place. I think it may have gotten even more broken in 8.2 so that purely LUT RPMs also can't straddle a non-LUT resource.Article: 116539
On Mar 12, 4:40 am, "ALu...@web.de" <ALu...@web.de> wrote: > Hi newsgroup, > > As shown in the VHDL code I am feeding two flip flop chains > with the same input. The chains use complementary clocks (200Mhz). > > In the process "rise_fall" I do some combinational logic > to detect rising and falling of the sampled input. > > Now I want to use one of the combinational signals as a clock > in a process "clksel" to sample the second combinationl signal. > > Speaking in terms of functional simulation the function > of the hardware description is the following: > The signal which gets active first > is used for ClockSel. > > The output ClockSel is then used to feed a DCS module. > > The problem I see in this hardware description is that > the clock in the process "clksel" is a gated clock. > > What is your opinion about the desription ? How can > I modify it to make it synthesizable ? Is there some > need for additional constraints ? > > library ieee; > use ieee.std_logic_1164.all; > > entity ana is > port( Reset : in std_logic; > Clk : in std_logic; > DataIn : in std_logic; > ClockSel : out std_logic > ); > end ana; > > architecture arch_ana of ana is > > signal r_p1, r_p2, r_p3 : std_logic; > signal f_p1, r_p2, r_p3 : std_logic; > > signal trig_rise, trig_fall : std_logic; > > begin > > ------------------------------------ > sync_redge: process(Reset, Clk) > begin > if Reset='1' then > r_p1 <= '0'; > r_p2 <= '0'; > r_p3 <= '0'; > > elsif rising_edge(Clk) then > r_p1 <= DataIn; > r_p2 <= r_p1; > r_p3 <= r_p2; > > end if; > end process sync_redge; > > ------------------------------------ > sync_fedge: process(Reset, Clk) > begin > if Reset='1' then > f_p1 <= '0'; > f_p2 <= '0'; > f_p3 <= '0'; > > elsif falling_edge(Clk) then > f_p1 <= DataIn; > f_p2 <= f_p1; > f_p3 <= f_p2; > > end if; > end process sync_fedge; > > ------------------------------------ > rise_fall: process(r_p2, r_p3, > f_p2, f_p3) > begin > > trig_rise <= ((not r_p3) AND r_p2); > trig_fall <= ((not_f_p3) AND f_p2); > > end process rise_fall; > > ------------------------------------ > -- ????????????????????????????????? > clksel: process(Reset, trig_fall) > begin > if Reset='1' then > ClockSel <= '0'; > > elsif rising_edge(trig_fall) then > ClockSel <= trig_rise; > end if; > end process clksel; > > end arch_ana; Why do you need to make the clksel process asynchronous to Clk? It would seem to me that trig_fall can only change as a result of a negative edge of Clk. So unless you really want a lot of delay from the negative clock edge to the ClockSel signal, I would think you'd just use the falling edge of Clk and the f_p1 and f_p2 signals as clock enables. Or did you do this to avoid a clock delay? Is DataIn asynchronous to Clk?Article: 116540
Let's see how fast Avnet can react. The problem has been brought to their attention. The clock is ticking... Peter Alfke =================== On Mar 12, 6:23 am, John C. Randolph <jcr.nos...@nospam.mac.com> wrote: > On 2007-03-10 16:09:43 -0800, "Peter Alfke" <a...@sbcglobal.net> said: > > > Rest assured that the offensive paragraph will be killed. > > Actually, that just looked like a standard media release clause, but > normally you'd ask a speaker to sign it, not an attendee. > > I signed forms with similar language when I was a presenter at Apple's WWDC. > > -jcrArticle: 116541
I just stated in the comments box that I do not agree. In germany the hand written text should supercede the check box in a contract. Kolja Sulimma On 12 Mrz., 15:32, "Peter Alfke" <a...@sbcglobal.net> wrote: > Let's see how fast Avnet can react. > The problem has been brought to their attention. > The clock is ticking... > Peter AlfkeArticle: 116542
Hi! Can anybody give me a hint on how to initialize an array of registers in Verilog with Xilinx ISE 7.1i? I tried the following code: | reg [9:0] palette [3:0]; | // synthesis attribute INIT of palette is "40'b0000000011000000001101111101111101111000" XST accepts the code (== does not generate error messages or warnings), but seems to discard it later (currently I only read from the array, but later there will be write access, too): | WARNING:Xst:653 - Signal <palette> is used but never assigned. | Tied to value 0000000000. Since all read accesses will result in '0' the registers are optimized away later by XST. I started my project with ISE 8 which supports Verilog "initial" blocks. Using those the following works well: | initial begin | palette[0] = 10'b0000000011; | palette[1] = 10'b0001110101; | palette[2] = 10'b0111110111; | palette[3] = 10'b1101111000; | end But now I have to synthesize the design using ISE 7.1i... Thanks! Till. -- real e-mail: wollenberg (at) web (dot) deArticle: 116543
Hi, I'm working on colorbar generator VHDL code from Xilinx (file name cb_eg1.vhd, from Xapp514, Chapter 16). The format is NTSC. Is there anyone who has modified the code to PAL format? I've inserted the right line numbers and regions for the colorbars. However the V-sync. signal is not as it should be. Regards Peter SoegaardArticle: 116544
If your code uses some CoreGen function that was mis-targetted to a Virtex4 part you might get this. Essentially, SOMEWHERE in your code... probably hidden away in something automatically generated that you didn't even write... SOMETHING is telling ISE to target a DSP48 slice, which doesn't exist in your part.... start stripping out sub- blocks of the design until it goes away is my best suggestion. On Mar 12, 1:56 am, Steve Battazzo <thesteveman_i...@yahoo.co.jp> wrote: > Thanks for the reply! Sorry it took me a while to get back, I haven't > had time to check the newsgroup for a couple days. > I'm using a Digilent Nexys board with a Spartan3 1000k gate chip, no > multiplication, just some DFFs, MUXs, decoders, and simple logic. > WebPack 9.1i on this computer. > > Steve > > > > davide wrote: > > Steve, > > > Can you tell me a little bit more about what device you are targeting and > > the version of WebPACK you are using. Are you using any multiplier blocks > > or doing any multiplication operations and pipelining the output? > > > -David > > > "Steve Battazzo" <thesteveman_i...@yahoo.co.jp> wrote in message > >news:m6KdnZIfoIUuVnLYnZ2dnUVZ_rmdnZ2d@comcast.com... > >> At the XST-synthesize stage, I'm getting this weird warning: > >> "Property use_dsp48" is not applicable for this technology. > >> I don't have anything in my code that I know of that calls for any such > >> thing.. it doesn't affect the program actually running on my board, but > >> I'm curious anyway. > > >> Anyone know what this means? > > >> Thanks, > > >> Steve- Hide quoted text - > > - Show quoted text -Article: 116545
Till Wollenberg <till@deadspam.com> wrote: ... > But now I have to synthesize the design using ISE 7.1i... Tell us why you have to synthesize with 7.1i -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 116546
>I am not sure, but I do not think that the FPGA Editor is not part of >the Web Pack version of the tools if that is what you are using. I >have the ISE Foundation version. FPGA Editor is part of the Web Pack version and I found it. Thanks for the pointer. MarkusArticle: 116547
On 12 mar, 12:58, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > On 2007-03-12, Pablo <pbantu...@gmail.com> wrote: > > > How can I use the Power PC in a non xilinx platform? I cannot use EDK > > from Xilinx. > > It is possible to use the PowerPC without having access to the EDK. I > have done so myself and I know others have done so as well. > > In theory it is just a matter of reading the documentation about the > PowerPC processor that is supplied by Xilinx, instantiate it correctly > and connect memories containing a boot monitor to the OCM bus. > > In practice you really want to have a version of Modelsim (or some > other simulator) that can handle SmartModels so that you are able > to simulate the PPC405 block. Otherwise you are going to have > troubles figuring out why nothing is working. Even so the > SmartModel is a bit quirky to use and if something is not > configured correctly you tend to get X on all outputs from it > if I remember correctly. > > I've been thinking abot posting some code for this but I haven't > gotten around to doing that yet. And truly, if you are going > to do any commercial development on the board you are probably > better off with the EDK. Perhaps you can save some money if > you don't use the EDK and you don't use the PLB bus on the > processor (the OCM and DCR bus are quite easy to interface > to) but if you need for example an external SDRAM or DDR > memory component you will save a lot of development/debugging > time/money by simply using the EDK provided components. > > I'm speaking from experience here, I've spent some time > on using the opencores DDR memory controller in a PowerPC > system as a hobby project and getting it to the point that I > could run programs from it reliably was not very fun. On > the other hand, getting the system to the point that I > could run the monitor off OCM-connected memories was quite > fun though :) Now, if I could just get Linux to boot on > the system I could do some really fun stuff... > > As to the question of erasing the PowerPC, no you can't. The > PowerPC is located on the Virtex II Pro chip and your only > choice is whether to use it or not. > > /Andreas Thanks so much for your help, but I have not understood some answers: - First of all. I have EDK in a lot of versions so I don`t need to buy it again. The problem is that my board doesn`t belong to Xilinx, so I can`t use EDK. I have a Virtex II Pro (from Xilinx) pluged in a Sundance Board (SMT338: http://www.sundance.com/web/files/productpage.asp?STRFilter=SMT338-VP30-6). That is the reason because I don`t use EDK. Correct me please. - Second. I am very grateful if you could tell me some thing to begin learning, because I have no idea of how can I program a simple "hello world", or something in C (if I could with Power PC). Thanks again. PabloArticle: 116548
rbblasco@gmail.com wrote: > Hi all > > I'm absolutely new to FPGAs, in fact my work is much more related with > the SW than with the HW, so I need to solve a problem that ideally I > was not targeted to. > > The issue is this: I have to estimate (roughly) the number of FPGAs > needed to support a typical signal processing algorithm, steps are as > follows, always in single-precision: > > 1.16k complex samples FFT > 2. 16k complex vector multiplication > 3. 16k complex samples IFFT > 4. 16k complex vector multiplication > 5. 16 k complex vector sum > > The idea is to know how many FPGAs will cover this kind of processing > in a given time, to compare with different types of processors. Por > the later, it is really easy just counting number of operations in > GFLOPs, but with hardware devices I am getting a lot of trouble, since > I don't have a clear understanding on what should I count. > > Please, give me a hand! > > Ruben > You left out a key piece of information: how fast do you need to compute these 5 steps? A processor that can do all 5 can fit on a single FPGA provided there is a reasonable amount of time between data sets, and that there is enough memory available to buffer the input (if needed), store intermediate results, and buffer the output. The wide swath ocean altimeter design featured in the gallery on my website ( http://www.andraka.com/wsoa.htm ), for example does everything on your list, in the same order and more in under 250usec for a 4K point data set using very old (original virtex) technology, which has comparatively little on-chip memory and no embedded multipliers. About 2/3rd of the area is dedicated to storage buffers using SRL16s (the large cyan block in the middle rignt, the magenta/green block below it, and the yellow/green blocks at the bottom are all buffers). The FPGA size is small, features are sparse and speed is slow by today's standards. Implementation size depends heavily on the FFT implementation of course. My FFT kernel has the smallest size-performance footprint, so using others will result in a bigger design for a given speed.Article: 116549
The /*synopsys enum state_code*/ constraint is pretty handy to handle the FSM state encoding. Unfortunately XST doesn't seem to be managing it correctly (as opposed to other synthesisers). Not reporting errors but breaking the FSM! Anybody has a workaround? I have a design I want to convert to XST with 10s of files and 10s of FSMs... Many thanks, Jean-Baptiste.
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