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Messages from 118675

Article: 118675
Subject: Re: Xilinx software quality - how low can it go ?!
From: Antti <Antti.Lukats@xilant.com>
Date: 1 May 2007 23:32:43 -0700
Links: << >>  << T >>  << A >>
On 1 Mai, 16:28, steven.elzi...@gmail.com wrote:
> On Apr 30, 2:55 am, Antti <Antti.Luk...@xilant.com> wrote:
> > Hi
>
> > I really dont understand why Xilinx isnt hiring people who can develop
> > and test software?
> > Is the world-wide shortage of engineers really that bad?
>
> > Latest example:
> > MicroBlaze Working Design with EDK 8.1
> > Update to EDK 8.2 -> DDR Memory failing (was working with 8.1)
> > Update to EDK 9.1 -> :
>
> > ./synthesis.sh: line 2: $'\r': command not found
>
> > !?
>
> > If Xilinx really does ANY software testing before release things like
> > that should no happen.
> > With ALL latest major releases the "time to first fatal error" from
> > the new install has been
> > less than 20 minutes. This is not acceptable for software that is to
> > be used to develop
> > commercial products.
>
> > Should i go back to EDK 8.1 for this one design?
>
> > Antti,
> > who really doesnt want to start another fight to get the buggy xilinx
> > sw to work.
>
> The synthesis error you have reported usually comes from having the
> newer bash shell installed which no longer accepts the Windows
> carriage return.  Refer to Xilinx Answer Record 24134:
>
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountry...
>
> Cheers,
> Steve- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -

Hi Steve,

First thank you.

Secondly I can only express my feelings one more time:
"If Xilinx is able to manage the software developemnt and testing they
should either give up or seek help".

.

I (and any other user of Xilinx devices) am not required to know what
is "SHELLOPTS", there should be no need to read all 20.000 Answer
records, only to post-fix another Xilinx software bug.

I know cygwin is a PITA, but there is lots of software that uses
Cygwin and works always out of the Box. Just Xilinx is not able to get
it working without ever repeating problems and postfixes, like AR
24134

Antti


Article: 118676
Subject: Re: Read 64-bit value over PLB
From: Alan Nishioka <alan@nishioka.com>
Date: 1 May 2007 23:35:32 -0700
Links: << >>  << T >>  << A >>
On May 1, 12:37 pm, Manny <mlou...@hotmail.com> wrote:
> My question is straight'n'simple: what's the *most efficient* way of
> reading a 64-bit value from a slave PLB peripheral in software? Is
> there any *weird* behaviour I should be made aware of when I read 32-
> bit value instead?

ppc always reads 64 bits.  It uses the byte enables to mask the upper
or lower 32 bits.

The most efficient way is to read it into the cache.  This reads a
line of four 64 bit words in a burst.

But if you only have one 32 bit word to read, I don't think you can do
much except make it zero wait state.


> In principle, PLB should be able to handle 64-bit transaction but not
> PPC software of course. Is there anyway to map this transaction to a
> consecutive pair of PPC software registers?

I don't think so.


Alan Nishioka
alan@nishioka.com


Article: 118677
Subject: Re: DDR2 with Spartan-3A anybody having success??
From: Antti <Antti.Lukats@xilant.com>
Date: 1 May 2007 23:40:32 -0700
Links: << >>  << T >>  << A >>
On 2 Mai, 06:06, "Alex Gibson" <n...@alxx.org> wrote:
> <rpons...@gmail.com> wrote in message
>
> news:1177963764.891437.228400@c35g2000hsg.googlegroups.com...
>
> > there is one example in sdram directory of s3ask_test design (follow
> > 3A reference design in xilinx web site), but this is only an
> > implementation of the DDR2 testbench ; the one that is generated with
> > mig 1.7. (a led blink if memory fails)
>
> > In mig user guide ug086, there is a brief explanation of the design ;
> > and I am too new to design to use it without tb (i.e. read / write
> > example from fpga with picoblaze would be a must...) ; if you can
> > help, I will apperciate.
>
> > I got 3 starter kit 3A from avnet in less than 1,5 week
>
> Mine took about the same time from Avnet Australia.
>
> The canned examples are rather lacking at the moment.http://www.xilinx.co=
m/products/boards/s3astarter/reference_designs.htm
>
> A couple of microblaze examples would be nice :-)
>
> Shouldn't take to much time to port the 3e examples.
> Getting the time to even look at the board is the problem for me.http://w=
ww.xilinx.com/products/boards/s3estarter/reference_designs.htm
>
> Alex

Hi Alex,

sorry about my mis-understandable statement about board delivery - the
delivery from Avnet was real quick, but it was resent to me, and that
delivery delayed. I did not specify that. So please everyone - Avnet
can deliver quick, and it should also arrive quick.

as of MicroBlaze reference designs - well USUALLY I would also just
make a new one, but in this case th=EDs is the VERY FIRST xilinx low
cost FPGA board with DDR2 memory. SDRAM and DDR are OK, easy to use
usually work. With DDR2 I have different experiences, its not always
working, it causes timing issues also on Virtex-5. Spartan-3A is way
slower than Virtex-5 so I really do not want to try the DDR2 EDK IP
core without the known working reference provided by Xilinx.

This (and any other Microblaze ref design) is missing NOT AVAILABLE.

I have lots of 3rd party made Xilinx boards - now I made a decision to
primarly use Xilinx own boards, in the HOPE for better support.

And result? I have the fresh new Xilinx board, and not that the
support is bad, no its NON EXISTANT.

I do not want to run the "factory test bitstream", this should be done
at the assembly/test site at the board manufacturer.

I want some known WORKING DDR2 memory desing for Xilinx Spartan-3A
Board.
(MIG blinking LED doesnt really count as such)

Antti


Article: 118678
Subject: Re: debounce state diagram FSM
From: Flash Gordon <spam@flash-gordon.me.uk>
Date: Wed, 02 May 2007 08:02:40 +0100
Links: << >>  << T >>  << A >>
Keith Thompson wrote, On 02/05/07 04:45:
> Jim Granville <no.spam@designtools.maps.co.nz> writes:
>> Keith Thompson wrote:
>>> CBFalconer <cbfalconer@yahoo.com> writes:
>>>
>>>> Keith Thompson wrote:
>>>>
>>>>> So repeated requests to redirect this discussion away from
>>>>> comp.lang.c, where it's completely off-topic, have not worked.  Does
>>>>> anybody have any suggestions for what *would* work?
>>>> Set follow-ups.
>>> I did, but it didn't do any good.  I could only set followups in my
>>> own followup; other direct replies to the original message retained
>>> the full cross-posting.
>> Err - not on this one, it seems ?
> 
> No, not on this one.  In my initial message, I redirected followups in
> an attempt to divert the discussion away from comp.lang.c.  In my
> later message, I was trying to find out why that didn't work and what
> might work instead, so I didn't bother redirecting followups.

I also tried redirecting, and explicitly requested that people on other 
parts of the thread exclude comp.lang.c, I was even polite about it. I 
believe the reason it does not work is that a lot of people only care 
about there own group, not other groups to which something might be 
inappropriately cross-posted, so even after reading the requests they 
continue posting to other parts of the thread without restricting 
follow-ups.

I'm beginning to think the solution is to post a couple of requests, and 
after 24 hours plonk everyone who ignores the requests.

Note I've not set followups this time because discussions about 
topicality *are* topical.
-- 
Flash Gordon

Article: 118679
Subject: Re: debounce state diagram FSM
From: Flash Gordon <spam@flash-gordon.me.uk>
Date: Wed, 02 May 2007 08:07:06 +0100
Links: << >>  << T >>  << A >>
John Larkin wrote, On 02/05/07 01:51:
> On Tue, 01 May 2007 17:29:11 -0700, Keith Thompson <kst-u@mib.org>
> wrote:
> 
>> So repeated requests to redirect this discussion away from
>> comp.lang.c, where it's completely off-topic, have not worked.  Does
>> anybody have any suggestions for what *would* work?
> 
> Programming embedded systems, things that interface to the real world,
> are off-topic to c programmers? Why am I not surprised?

I gave the best C answer, which was that it is better solved in HW. I 
also stated that I have done debounce in SW, but I did not get any 
response asking how, so obviously everyone agreed that implementing it 
in HW was better.

Perhaps we should post questions about string theory in your groups, 
after all semi-conductors only work because of the laws of physics in 
the real world, so you must be interested in whether string theory is 
correct or what modifications are required to it for it to be correct 
and want those discussions in your groups.
-- 
Flash Gordon

Article: 118680
Subject: Re: How many Xilinx devkits does one need?
From: Antti <Antti.Lukats@xilant.com>
Date: 2 May 2007 00:08:46 -0700
Links: << >>  << T >>  << A >>
On 1 Mai, 20:28, "Eric Crabill" <eric.crab...@xilinx.com> wrote:
> Hi Antti,
>
> Regarding your specific concerns on the Spartan-3A Starter Kit, there is a
> known issue where the board assembler failed to set the jumpers correctly.
> On the Spartan-3A Starter Kit product page, under the documentation banner,
> there is a "Product Notification" addressing this issue.  You can view it
> directly athttp://www.xilinx.com/bvdocs/ipcenter/customer_notification/S3AKit_Pr...
>
> Hope that helps,
> Eric
>
Thank you Eric,

well, installing jumpers i already did, but seeing the preloaded demos
wasnt my priority.
besides I have seen those demos long before, I dont need additional
proove that they work on my board.
If the my board passed factory testing (as indicated by the label) the
factory tests and demos should run.

The PN as you pointed out only explains that I may have to desolder
some 0402 SMD ferrites and
replace them should I experience "sub optimal" DDR2 performance.
(this is also explained in the Schematic of the S3A board, that made
me scared already! )

Well, as there is no reference design to even test, I would say the
performance is defenetly sub-obtimal
at the present state, so I am still holding back, hoping that:

Xilinx RELEASES S3A DDR2 Reference Design, that has "optimal" (as
opposed to sub-optimal) performance.
Should THAT reference design NOT work on my board, then I will sit
down on the workplace with
stereo microscope and seek those ferrite beads and replace them as
suggested in the PN document.

If Xilinx has NO INTENTION to provide a working DDR2 reference designs
for the Xilinx Spartan-3A board
then I will throw it out of the window, to save further frustration.

Antti


Article: 118681
Subject: How to Black Box my IP using Quartus II
From: futzy.r@gmail.com
Date: 2 May 2007 00:32:27 -0700
Links: << >>  << T >>  << A >>
I want to black-box a sub-module in my design (written in VHDL) that
is targeted for a Altera's Cyclone II FPGA.
I have tried the VQM netlist writer inside Quartus to create a device
netlist that can be instantiated in my design top. Is there a way I
can encrypt this netlist?

Thanks
Anup


Article: 118682
Subject: Re: Where can I find the pass transistor's working curve under 1.2V?
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Wed, 02 May 2007 08:41:40 +0100
Links: << >>  << T >>  << A >>
On 1 May 2007 18:50:32 -0700, 
Weng Tianxiang <wtxwtx@gmail.com> wrote:

>Do you have any idea where I can get a graph of it? I just want the
>graph showing the relationship between input and output.

Why not simulate one in any of the free versions of SPICE?
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 118683
Subject: Re: debounce state diagram FSM
From: Robin <robin.pain@tesco.net>
Date: 2 May 2007 00:58:42 -0700
Links: << >>  << T >>  << A >>
On 2 May, 03:25, Keith Thompson <k...@mib.org> wrote:
> John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> writes:
> > On Tue, 01 May 2007 17:29:11 -0700, Keith Thompson <k...@mib.org>
> > wrote:
>
> >>So repeated requests to redirect this discussion away from
> >>comp.lang.c, where it's completely off-topic, have not worked.  Does
> >>anybody have any suggestions for what *would* work?
>
> > Programming embedded systems, things that interface to the real world,
> > are off-topic to c programmers? Why am I not surprised?
>
> Questions which have nothing to do with programming in C are off-topic
> in comp.lang.c.  (If the original poster had asked for a C solution,
> it might have been different, but I don't think I've seen a single
> line of C source code in this thread.)
>
> I'm getting the impression that once someone posts an inappropriately
> cross-posted discussion, there's just no way to keep it from
> continuing on all the newsgroups to which it was originally posted,
> because most people posting followups just don't pay attention to the
> Newsgroups: header.  Oh, well.
>
> --
> Keith Thompson (The_Other_Keith) k...@mib.org  <http://www.ghoti.net/~kst>
> San Diego Supercomputer Center             <*>  <http://users.sdsc.edu/~kst>
> "We must do something.  This is something.  Therefore, we must do this."
>     -- Antony Jay and Jonathan Lynn, "Yes Minister"

It's worse than that, this is really a DSP question.

The sampled input above will *require* an anti-alias filter - making
itself redundant.

Robin


Article: 118684
Subject: Unused Pin setting on per-pin basis
From: Andrew Greensted <ajg112@ohm.york.ac.uk>
Date: Wed, 02 May 2007 09:11:38 +0100
Links: << >>  << T >>  << A >>
Hi all,

I've got a custom FPGA board with a number of peripherals connected to
the FPGA. I need to keep the connections between the FPGA and unused
peripherals in a sensible state.

Is there a way I can define FPGA pins as inputs with different
pull-up/pull-down/floating states without including dummy signals in my HDL.

bitgen offers the option to set ALL unused pins to
pull-up/pull-down/floating, but I need to set this on a per/pin basis.

Any ideas anyone?

Thanks
Andy

Article: 118685
Subject: Re: Unused Pin setting on per-pin basis
From: Antti <Antti.Lukats@xilant.com>
Date: 2 May 2007 01:26:46 -0700
Links: << >>  << T >>  << A >>
On 2 Mai, 10:11, Andrew Greensted <ajg...@ohm.york.ac.uk> wrote:
> Hi all,
>
> I've got a custom FPGA board with a number of peripherals connected to
> the FPGA. I need to keep the connections between the FPGA and unused
> peripherals in a sensible state.
>
> Is there a way I can define FPGA pins as inputs with different
> pull-up/pull-down/floating states without including dummy signals in my HDL.
>
> bitgen offers the option to set ALL unused pins to
> pull-up/pull-down/floating, but I need to set this on a per/pin basis.
>
> Any ideas anyone?
>
> Thanks
> Andy

no
ASFAIK
its sometimes really annoying..:(

Antti






Article: 118686
Subject: Re: debounce state diagram FSM
From: jasen <jasen@free.net.nz>
Date: 2 May 2007 08:40:09 GMT
Links: << >>  << T >>  << A >>
On 2007-05-01, petrus bitbyter <pieterkraltlaatditweg@enditookhccnet.nl> wrote:
>> This has nothing to do with comp.lang.c. Please remove that newsgroup
>> from your distribution.
>
> FAIK the OP was asking about the design of a finite state machine. Nothing 
> said about the implementation. C is a perfect language to build finite state 
> machines. 

C.L.C is for discussing the C language, anything else (eg: algorithms, a
particular implementation of c, or actual code) is off-topic.  

If the kooks were to hit CLC noone would notice  the newsgroup was when I
stopped reding it 20% off-topic posts, 40% complaints about off-topic posts,
10% questions answered by the FAQ, 25% "read the FAQ", and 5% actual
on-topic posts (which were boring as hell).

C.L.C.moderated is a better group, as long as you're not in a hurry for an
answer, the rules of topicality are ironically more relaxed than in the
non-moderated group.

Bye.
   Jasen

Article: 118687
Subject: Re: debounce state diagram FSM
From: jasen <jasen@free.net.nz>
Date: 2 May 2007 08:46:58 GMT
Links: << >>  << T >>  << A >>
On 2007-05-01, Robin <robin.pain@tesco.net> wrote:
> On 29 Apr, 19:32, Anson.Stugg...@gmail.com wrote:

> This debounce idea is terrible. Straight away you have aliasing
> problems not to mention arbitrary latency.
>
> The simple thing to do is detect an edge by e.g. edge driven interrupt
> and then fire the output state immediately according to the edge
> direction and start your one-shot debounce-duration timer that
> inhibits the interrupt until it times outs.
>
> Now you have instant "analogue" style response and you can reduce the
> duration until bouncing happens and then back it off by a safety
> margin.

depends if he merely wants to de-bounce or if he also wants to de-glitch

Bye.
   Jasen

Article: 118688
Subject: Re: Unused Pin setting on per-pin basis
From: "comp.arch.fpga" <ksulimma@googlemail.com>
Date: 2 May 2007 02:00:45 -0700
Links: << >>  << T >>  << A >>
On 2 Mai, 10:11, Andrew Greensted <ajg...@ohm.york.ac.uk> wrote:

> bitgen offers the option to set ALL unused pins to
> pull-up/pull-down/floating, but I need to set this on a per/pin basis.

What do you need the per pin configuration for? The pullups are
extremely
week. (5uA to 200uA for Virtex-4). I can't imagine a digital
application that
will be disturbed by that.

If you really need it you good create a pre placed hard macro in FPGA
editor
including the pads and instantiate that as a black box.
I think you can even instantiate IO with placement constraints in HDL
without
bringing the signals out to toplevel. But I never tried that.

Kolja Sulimma





Article: 118689
Subject: Re: Xilinx 9.x SW == Total Frustration (so far..)
From: Andreas Ehliar <ehliar@lysator.liu.se>
Date: Wed, 2 May 2007 09:04:46 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2007-05-02, Antti <Antti.Lukats@xilant.com> wrote:
> But, Impact is meant to be used to configure FPGA's,
> not to use "File Exit"... because its all that works.
>
> What todo? Wait SP4? Or maybe there is a secret tactical patch
> available?
> Or some you-dont-find-it-when-you-do-not-know-the-exact-number AR?

Have you tried to use it in batch mode? If all you need it for
is to configure FPGA:s that should be enough. (Assuming the bugs
are GUI related.)

Cheat sheet after impact is started using -batch: (included
because I spent a lot of time yesterday using impact in
batch mode and happened to remember the necessary commands :))

setmode -bs
setcable -port auto
identify
assignfile -p 3 "foo.bit"
program -p 3

Where 3 is the position in the jtag chain of the device you are
programming.

/Andreas

Article: 118690
Subject: Re: Xilinx 9.x SW == Total Frustration (so far..)
From: Andreas Ehliar <ehliar@lysator.liu.se>
Date: Wed, 2 May 2007 09:13:05 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2007-05-02, Antti <Antti.Lukats@xilant.com> wrote:
> But, Impact is meant to be used to configure FPGA's,
> not to use "File Exit"... because its all that works.
>
> What todo? Wait SP4? Or maybe there is a secret tactical patch
> available?
> Or some you-dont-find-it-when-you-do-not-know-the-exact-number AR?

Have you tried to use it in batch mode? If all you need it for
is to configure FPGA:s that should be enough. (Assuming the bugs
are GUI related.)

Cheat sheet after impact is started using -batch: (included
because I spent a lot of time yesterday using impact in
batch mode and happened to remember the necessary commands :))

setmode -bs
setcable -port auto
identify
assignfile -p 3 -file "foo.bit"
program -p 3

Where 3 is the position in the jtag chain of the device you are
programming.

/Andreas

Article: 118691
Subject: Re: DDR2 with Spartan-3A anybody having success??
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Wed, 02 May 2007 21:14:01 +1200
Links: << >>  << T >>  << A >>
Antti wrote:

> as of MicroBlaze reference designs - well USUALLY I would also just
> make a new one, but in this case thÝs is the VERY FIRST xilinx low
> cost FPGA board with DDR2 memory. SDRAM and DDR are OK, easy to use
> usually work. With DDR2 I have different experiences, its not always
> working, it causes timing issues also on Virtex-5. Spartan-3A is way
> slower than Virtex-5 so I really do not want to try the DDR2 EDK IP
> core without the known working reference provided by Xilinx.
> 
> This (and any other Microblaze ref design) is missing NOT AVAILABLE.

Sounds a reasonable expectation, no comment from anyone in Xilinx ?

It does suggest they have tried, and been unable to get this to
actual work themselves ?

Do they have ANY DDR2 templates that allow a bandwidth/memory test ?

-jg


Article: 118692
Subject: Re: Unused Pin setting on per-pin basis
From: Andrew Greensted <ajg112@ohm.york.ac.uk>
Date: Wed, 02 May 2007 10:15:35 +0100
Links: << >>  << T >>  << A >>
comp.arch.fpga wrote:
 > What do you need the per pin configuration for? The pullups are
> extremely
> week. (5uA to 200uA for Virtex-4). I can't imagine a digital
> application that
> will be disturbed by that.

The board uses a with a Spartan-3E. The data sheet suggest the pull down
is 34K5 (Table 77 - ds312). I guess that's not too strong.

However, I'd prefer the option to control the pull resistors on a
per-pin basis. It just seems to me a 'better' way of doing things.

Thanks for the suggestions
Andy

Article: 118693
Subject: Re: Problem cascading 2 DCMs
From: MNiegl <Michael.Niegl@cern.ch>
Date: 2 May 2007 02:32:31 -0700
Links: << >>  << T >>  << A >>
On May 1, 10:03 pm, austin <aus...@xilinx.com> wrote:
> Michael,
>
> Thanks.  I am trying to keep track of DCM issues, so that we can either
> make the documentation better, or the hardware better (in future chips).
>
> Austin

I just ran it just as successfully with the auto-cal enabled so the
issue doesn't seem to be related to that. Seems more like a slight
jitter problem when the DCM comes out of config without another reset.

Cheers,
Michael


Article: 118694
Subject: prevent ROM inferration
From: Johannes Hausensteiner <johannes.hausensteiner@pcl.at>
Date: Wed, 02 May 2007 11:45:20 +0200
Links: << >>  << T >>  << A >>
I have a state machine design with big case statments (VHDL). When
I compile with Precision RTL it infers block ROM, which exceeds the
actual number of EBR blocks in my FPGA. I am using a Lattice LFECP10
chip. How can I tell Precision not to infer ROM but implement in
logic?

Thanks,

Johannes

Article: 118695
Subject: Area constraint - trust Low Level Synthesis?
From: Borge <borge.strand@gmail.com>
Date: 2 May 2007 02:50:16 -0700
Links: << >>  << T >>  << A >>
My FPGA is getting a bit crowded. I have a huge distributed FIR in my
Spartan3/400. When synthesising the design I get conflicting (?) area
constraint messages from Low Level Synthesis and Final Report.

In the first message it looks like my desing doesn't fit, but in the
second one it looks OK. Which report should I trust? The part that
says I'm using 123% of 3584 slices or the one that says I'm using 3366
of 3584?

The design seems to be working just fine when doing a functional test.
But it's a tough job to verify a huge FIR filter and attached
dithering.

Thanks for your help interpreting this stuff!


B=F8rge



Low Level Synthesis says:

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block implementation,
actual ratio is 123.
Optimizing block <implementation> to meet ratio 100 (+ 5) of 3584
slices :
WARNING:Xst:2254 - Area constraint could not be met for block
<implementation>, final ratio is 123.


But Final Report says:

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:       6,123 out of   7,168   85%
  Number of 4 input LUTs:           4,939 out of   7,168   68%
Logic Distribution:
  Number of occupied Slices:                        3,366 out of
3,584   93%
    Number of Slices containing only related logic:   3,366 out of
3,366  100%
    Number of Slices containing unrelated logic:          0 out of
3,366    0%
      *See NOTES below for an explanation of the effects of unrelated
logic
Total Number of 4 input LUTs:          5,793 out of   7,168   80%


Article: 118696
Subject: Re: DDR2 with Spartan-3A anybody having success??
From: Antti <Antti.Lukats@xilant.com>
Date: 2 May 2007 03:23:11 -0700
Links: << >>  << T >>  << A >>
On 2 Mai, 11:14, Jim Granville <no.s...@designtools.maps.co.nz> wrote:
> Antti wrote:
> > as of MicroBlaze reference designs - well USUALLY I would also just
> > make a new one, but in this case th=EDs is the VERY FIRST xilinx low
> > cost FPGA board with DDR2 memory. SDRAM and DDR are OK, easy to use
> > usually work. With DDR2 I have different experiences, its not always
> > working, it causes timing issues also on Virtex-5. Spartan-3A is way
> > slower than Virtex-5 so I really do not want to try the DDR2 EDK IP
> > core without the known working reference provided by Xilinx.
>
> > This (and any other Microblaze ref design) is missing NOT AVAILABLE.
>
> Sounds a reasonable expectation, no comment from anyone in Xilinx ?
>
> It does suggest they have tried, and been unable to get this to
> actual work themselves ?
>
> Do they have ANY DDR2 templates that allow a bandwidth/memory test ?
>
> -jg

Hi Jim,

well, the only available DDR2 thingie is the default MIG coregen
autogenerated self checking test design, that should display fail-pass
on single user LED.

the only thing what this thing is good, is to deliver a result:
"the DDR2 memory is not necessary fully dead"... for anything more
reliable evaluation the LED status is not good IMHO.

this design does really not allow any "bandwidth" evaluation, and its
user interface is also awkward enough so that no-body wishes to mess
around with unless really forced to do that. The MIG core can not be
used without special statemachines in any design.

As of do they have or not, well at X-Fest there was demo of some
display things, rotate the knob and look Xilinx logo to rotate, I
assume those demos use DDR2 memory (as it is the only external RAM on
this board).

So I assume Xilinx _HAS_ useable demos and reference designs
demonstrating working DDR2 on Xilinx Spartan-3A kit.
The only issue is that NONE of those demos is currently available :(

Antti


Article: 118697
Subject: Xilinx 9.x SW == Total Frustration (so far..)
From: Antti <Antti.Lukats@xilant.com>
Date: 2 May 2007 03:44:40 -0700
Links: << >>  << T >>  << A >>
Its really hard to see how some software manages to get worse and
worse every major release!

Installed - ISE 9.1+SP3, EKD 9.1+SP1
Applied hotfix for EDK as described in AR24143

This is LATEST RELEASE, ALL available service packs installed.

Impact-> program... (trying to download bit to FPGA, all used to
work...)

A dialog popups, but status bar doesnt proceed at all.. fully stalled.
Only thing possible is "cancel" button so I click on CANCEL

and success!

operation cancelled and dialog box is closing.

Right click on the FPGA icon to try again..
Guess what... the right cliks brings up a single item menu:

"operation in progress please wait"

for heavens sake the process was stalled and I cancelled it.
Its no longer in progress.. it has been terminated !

Uh, File->Exit still WORKS!

But, Impact is meant to be used to configure FPGA's,
not to use "File Exit"... because its all that works.

What todo? Wait SP4? Or maybe there is a secret tactical patch
available?
Or some you-dont-find-it-when-you-do-not-know-the-exact-number AR?

Antti


Article: 118698
Subject: Re: Where can I find the pass transistor's working curve under 1.2V?
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: 2 May 2007 03:54:52 -0700
Links: << >>  << T >>  << A >>
On May 2, 12:41 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On 1 May 2007 18:50:32 -0700,
>
> Weng Tianxiang <wtx...@gmail.com> wrote:
> >Do you have any idea where I can get a graph of it? I just want the
> >graph showing the relationship between input and output.
>
> Why not simulate one in any of the free versions of SPICE?
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

Hi Jonathan,
What I need is a graph of pass transistor's working curving that must
be available in some books or articles. I have no Spice experiences
and even don't know what proper parameters should be.

Weng


Article: 118699
Subject: Re: Where can I find the pass transistor's working curve under 1.2V?
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Wed, 02 May 2007 12:24:24 +0100
Links: << >>  << T >>  << A >>
On 2 May 2007 03:54:52 -0700, 
Weng Tianxiang <wtxwtx@gmail.com> wrote:

>What I need is a graph of pass transistor's working curving that must
>be available in some books or articles.

Weng, 

sorry, it's been a while since I looked in detail at this
kind of stuff.  There is some nice information on the use
of pass switches for digital applications in the technical 
notes for QuickSwitch devices:

http://www.idt.com/products/files/7591/quickswitch_basics.pdf
http://www.idt.com/products/files/7528/TN_07.pdf

I'm sure this is not everything you need, but perhaps it will put
you on the right track.  Of course, the exact behaviour will depend
strongly on the details of the pass transistor itself - gate 
threshold, etc.

Note that QuickSwitch devices use single NMOS pass transistors.
For basic information on CMOS pass structures, try

http://www.fairchildsemi.com/ds/CD/CD4066BC.pdf

although that part is fairly ancient history now.

> I have no Spice experiences
> and even don't know what proper parameters should be.

If you are concerned about the detailed analog behaviour
of pass transistors, I suggest you *should* get some
SPICE experience, double-quick!

hth
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.



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