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John, The LVDS standard specifies that the transmitter has a 100 ohm resistive termination to absorb reflections. AustinArticle: 119701
I was able to solve the problem with the shell command rm -rf ~/.mw Deleting the .mw subdirectory in my home directory, which older Quartus versions had left there, caused the segmentation violation problem that I had with Quartus 7.1 to disappear. Just in case this helps anyone else ... Markus -- Markus Kuhn, Computer Laboratory, University of Cambridge http://www.cl.cam.ac.uk/~mgk25/ || CB3 0FD, Great BritainArticle: 119702
Hello everybody,
I m trying out implementing interfacing the DDR
memory with EDK with PowerPC acting acting as the IOP. The design flow
is working fine. I m new to EDK. Does anybody has any idea of what
specs can I refer to for s/w interfacing. I am primarily interested in
s/w interfaces for accesing DDR memory like reading and writing data
at a particular address and also writing on-board LEDs and reading DIP
switches. Any help would be greatly appreciated.
Thanks,
Koustav
Article: 119703"austin" <austin@xilinx.com> wrote in message news:f34sfg$62n1@cnn.xilinx.com... > John [Larkin], > > The LVDS standard specifies that the transmitter has a 100 ohm resistive > termination to absorb reflections. > > Austin Some LVDS transmitters have no (design) impedance. This is what I [John_H] was referring to in another post. Those transmitters that are implemented as current sources require that the transmitter have the differential impedance required to absorb the reflections from the LVDS line and receiver. The transmitter data should always be referenced to make sure the impedance is integrated into the transmitter, is required externally, or if the driver needs to be "transformed" to an equivalent source such as the Xilinx BLVDS. - John_HArticle: 119704
Antti wrote: > Hi Jim, > > you maybe right, the OLPC minimum order quantity is 3 MILLION pieces, > eg minimum order value of round 450 Mio USD, > so I guess it does pay off to go ASIC at those volumes ;) > > I wonder a bit that the 100 USD target price goal have not met - as I > heard > there is serious project to develop a mobile phone with sub 10 USD > manufacturing costs ! Yes, but often these boasts compare BOM, against final selling price. So a $10BOM cellphone is certainly just possible, but the end user price will not be that. India made some comments about targeting $15 laptops, but again I think they cheat a little with BOM vs final price. > so if a mobile phone manufacturing cost can be pushed below 10 USD, > then it is surprising > that a laptop cant be pushed below 100 Silicon is getting ever cheaper, but the challenge is the display, and battery. Also storage ? - if you remove the HDD, and pop in external SD card, the 'Press release' price can drop The design you show here, looks on the complex side (too many parts), but it is a prototype - how many layers is the PCB ? The final goal has to be a stacked CPU+Memory, in order to slash PCB size/complexity. Another pass at this, could pull the Cyclone+other chips, into something like the Atmel AT91CAP series. I'd also watch Intel, over the next couple of years they are moving focus to include this area. -jgArticle: 119705
On May 22, 12:15 pm, mh <moazzamhuss...@gmail.com> wrote: > Hi > I want to debug a custom board with no interface for data exchange. > The requirement is PC based autometic test pattern generation and real > time data exchange from FPGA based hardware. > > I chanced to see an article in Xcell Journal of 2nd quarter 2005, > titled: "Using the JTAG Interface as a General-Purpose Communication > Port"--- but couldn't find any thing from the link given in the > article. > > How can I get GNAT tool as described in that article. > > Or > > Any other suggestion to use JTAG of Xilinx FPGA as general purpose I/ > O. > > regards > MH If it's enough to monitor and control fpga pins by JTAG you can try Scanseer tool -- http://www.scanseer.com. -- SKArticle: 119706
MikeJ wrote: > on www.fpgaarcade.com you can get the latest version of the T65 core from > Opencores. > > I did a lot of debuging work on the original and still maintain it as the > original author has vanished. It is used in a number of the arcade game > projects with great success. Thanks, I've tried it and looks good:: With Quartus 7.1, compiled for a Cyclone I, T65 uses 797 LEs and the Free-6502 core uses 1089 LEs (both with an overhead of 38 LEs for some memory mapping, timer and one port to some LEDs). That's nice, because with some small Cyclone II, e.g. the EP2C8, I could instantiate 10 cores of T65 (7 with Free-6502, but I guess there would be some more overhead for arbitraters etc. needed). With a 50 MHz clock it doesn't warn that timings are not met, but the timing analyses says 22.522 ns "worst case tco". Does this mean, that it doesn't work stable with 50 MHz, but with 44 MHz, only (which, btw, would be more than fast enough for my project) ? -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 119707
"MikeJ" <mikej@fpgaarcade.nospam.com> wrote in message news:Xqj5i.554$ZA.538@newsb.telia.net... > on www.fpgaarcade.com you can get the latest version of the T65 core from > Opencores. > > I did a lot of debugging work on the original and still maintain it as the > original author has vanished. Has Daniel Walner been bumped off then?Article: 119708
austin wrote: > John, > > 18 MHz is the lower limit for the Spartan 3 DLL, and the Spartan 3 DFS > could go even lower than 18 MHz -- down to 9 MHz (to multiply and > provide a clock out that is 2X the clock in). > > 25 MHz is well below the low frequency mode of the DLL/DCM, so one > bitstream fits all (one setting will lock for any input in the range of > 18 to 25 MHz). > > If the frequency changes while it is running, you may have to reset the > DCM for it to lock. The DCM tracks up to a point, but delay line > overflow or underflow may happen which then requires a reset to restart. In which case, what is the rate frequency that breaks the lock? Is it related to the system clock or not? Cheers PeteS > > Austin > > John Larkin wrote: >> On Wed, 23 May 2007 15:00:27 -0700, John Larkin >> <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >> >>> If we design an S3-based system using an internal clock doubler, the >>> design software wants to know our input frequency. In our case, we >>> want to double the incoming 20 MHz clock to 40 MHz for internal use. >>> >>> In other applications, the incoming clock may range from, say, 18 to >>> 25 MHz, and we'd like to use the same FPGA design without recompiling. >>> Looking at the Xapps and datasheets, it's implied that the clock >>> doubler will double an incoming clock over the specified range (18 to >>> 167 MHz in) without otherwise being "told" the nominal input >>> frequency. Is that right? >>> >>> Thanks, >>> >>> John >> And I guess there are two parts to the question: how do the DFS and >> the DLL blocks operate in this regard? If we use the DFS, we can go >> below 18 MHz as the input, which would be nice. >> >> John >>Article: 119709
I think I have a problem with my Cyclone II FPGA and wanted to do a boundary scan check on the device to see if it is working ok. I looked for options to perform a boundary scan check using the Quartus programmer tool and couldn't find anything useful. I have used this feature on the Xilinx ISE tools and wanted to know if this can be done on the Altera FPGAs. Any suggestions will help. Thanks AnupArticle: 119710
Hello, I own a Spartan 3E Starter Kit, which I plan to use for crowd- entertainment purposes. Since the 3-bit VGA output is way too limiting for my project, I am planning to add a 12-bit VGA port to my Starter Kit. To do so, my idea was to buy the Breadboard accessory board from DigilentInc. I don't have much knowledge of high-speed signal propagation so my question is: Will the VGA signal be noticeably distorted by the breadboard? The signal's highest frequency would be 25MHz. The plan is to use a projector to display the pretty colours. I understand using wire wrap would be a better solution, but I'd like to avoid that if possible. Cheers! -checoArticle: 119711
On Thu, 24 May 2007 12:54:13 -0700, "John_H" <newsgroup@johnhandwork.com> wrote: >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:0ppb531bd38oj99t3dne4fei8n4lrotm00@4ax.com... >> >> National's CMOS structure is different, >> >> http://www.national.com/appinfo/lvds/files/lvds_ch1.pdf >> >> more of a real current source. I'd guess that the Maxim is the oddball >> here. The National and Fairchild transmitters I've played with will go >> rail-to-rail if not terminated. I haven't tried an unterminated Xilinx >> lvds driver; their receivers are pretty good r-r comparators. >> >> John > >The FPGA structures appear to be what are important to this conversation. >There are transmitters that are true current sources both with and without >internal 100 ohm parallel terminations. There are transmitters that present >voltage drivers with (series) source impedances that roughly match the >current-source approach. > >For anyone designing with LVDS, appropriate reading of the data sheet >information on the transmitter is important. For a proper LVDS connection, >the transmitter needs to appear to be a 100 ohm differential source. Everywhere I look, I see unterminated transmitters: http://zone.ni.com/devzone/cda/tut/p/id/4441 http://www.interfacebus.com/Design_Connector_RS644.html http://www.fairchildsemi.com/ms/MS/MS-547.pdf http://www.analog.com/UploadedFiles/Application_Notes/42118600205599850975382134073431740717454123180480718AN586.pdf http://www.ams.aeroflex.com/ProductFiles/Presentations/LVDSOverview9-04.pdf http://spacewire.esa.int/content/TechPapers/documents/SpaceWire%20Standard%20%20ISWS%202003.pdf This makes sense: a 3.5 mA current source (transmitter) drops the proper 350 mV across the 100 ohm receive termination. If the transmitter also terminated in 100 ohms, you'd net half that swing. That's consistant with my observation that unterminated transmitters slew rail-to-rail on both pins. >Different manufacturers are happy to deviate slightly from the originally >proposed driver structure to present something with equivalent >characteristics when properly configured whether this means plug&play, an >external parallel termination, or a 3-resistor network to "look" like the >equivalent source. Without the 100 ohm equivalent transmit impedance, any >reflections from the receiver or other impedance mismatches will reflect >back toward the receiver rather than be absorbed at the source. But if the receiver terminates properly, there will be no reflections. JohnArticle: 119712
Madid, don't get angry. Your question smelled like a typical homework assignment, and that's not what this newsgroup is meant to solve. I take your word for it, that it was NOT homework. Recently we have been flooded with trivial questions. I had to explain that current flowing through a resistor causes a voltage drop. Ohm's law should really be High-School stuff... Many of us will remain suspicious, and we may sometimes react "rudely". That's the price to pay when you ask such trivial questions in this environment. But we can also learn: Not every trivial question is homework... repeat: Not every trivial question is homework... Not every trivial question is homework... Peter Alfke On May 23, 11:00 pm, NA <madid87-MAK...@yahoo.com> wrote: > On Thu, 24 May 2007 02:38:49 +0200, Kryten > > <kryten_droid_obfustica...@ntlworld.com> wrote: > > Please do your own homework, thank you. > > This is not a homework and I NEVER asked "you" to write this for me. All I > asked is what is wrong like people ask in 90% other posts. > So you're reply is very rude, but you already know that. > > Anyway I found my problem. That piece of code was in a process sensitive > to clock (50MHz) and it would execute many times instead of one. If you > sll something "many" times you get zeros.Article: 119713
Frank Buss wrote: > With a 50 MHz clock it doesn't warn that timings are not met, but the > timing analyses says 22.522 ns "worst case tco". Does this mean, that it > doesn't work stable with 50 MHz, but with 44 MHz, only (which, btw, would > be more than fast enough for my project) ? Tco is the clock-to-out delay from a clock input on a register to the change on the FPGA output pin. Actually in most cases tco really isn't useful - particularly with multiple clock domains in your design. The 'stability' of your design is governed primarily by fMax, although other constraints do come into play. And you _definitely_ need to take notice of these other constraints when interfacing the FPGA to external devices. An example might be interfacing to an external memory chip - you'll have definite and variable delays on your address, data and control lines coming out of the FPGA and need to consider this when matching against your external memory setup, hold and cycles times. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 119714
checo wrote: > I own a Spartan 3E Starter Kit, which I plan to use for crowd- > entertainment purposes. Since the 3-bit VGA output is way too limiting > for my project, I am planning to add a 12-bit VGA port to my Starter > Kit. Since MikeJ must be napping... ;) <http://home.freeuk.com/fpgaarcade/displaytest.htm> Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 119715
Hi John, Sorry for the trouble. I also wanted to be part of this discussion as i used to be part of this group for the last two years. This group actually helped me to learn a lot in the FPGA based HW modeling. Sorry for the wrongly formated message i sent. The sentance structure may be some times wrong as i am not that strong in english. But last time what happend is; i was little bit excited to see my old collegue to write something on this group. It remind me about the old times when we both were actively participated in these discussions. Thats what happend. Sorry for that. Anyway my actual intention is only to be a part of all these discussions. Sorry for every thing else. Thanks for your suggestion. regards Sumesh V SArticle: 119716
Hello all, am finally getting to the point where I'd like to test VHDL from C. This is under windows. Ideally, I'd like to have a little console app (made in VC++) that feeds data to the simulator and checks the results. I know there are a lot of details with this to figure out but as things scale up having the smaller VHDL pieces fully checked with the "golden code" is important so spending some effort now will pay off. Writing tests in VHDL itself isn't going to cut it. I looked around briefly on xilinx's site and via google, didn't come up with much. This could be done with files, having the C code generate a file with a bunch of test vectors, then a VHDL testbench reading the file line by line and driving the simulator, and writing results to another file, that the C code can then parse and check. Yuck. I'm pretty new to this, there must be all sorts of established techniques for verifying big designs. Any pointers appreciated. Thanks JesseArticle: 119717
I'm a longtime Xilinx user, and I've recently switched over to the dark side
:)
Anyway, I'm new to Quartus-II Web Edition, and I'm trying to port a
project from my Xess XSA-3S1000 board to a Altera Cyclone-II
Starter Kit.
I've run into a problem where I have bidi I/Os which need a PULLUP.
The Xilinx Spartan-3's I/Os supported a PULLUP constraint,
specified in Xilinx's *.UCF file. I searched Altera's website,
but I can't find how to specify a pullup on the Cyclone-II's I/Os?
Can someone give me a quick pointer?
...
Also, is there a way to directly import a $readmemh file into Quartus-II
ROM-initialization file (*.mif) ? So far, I've been running a
Verilog-program
to convert the $readmemh files into *.mif files. It works, but it's an
extra-step I'd like to eliminate.
...
So far, I like Quartus-II's speed. Synthesizing my design is almost
2X fast in Quartus II 7.1, as it was in Xilinx Webpack 9.1i.03.
On top of that, Quartus-II's Verilog-parser is uniformly better across
the board. (Well, except for the `macro preprocessor having problems
with multiple macro-arguments that span 2 or more textlines.)
Xilinx's XST synthesis gets tripped up by obvious Verilog-2001 constructs,
like:
reg [7:0] memory [0:255];
always @* mux_out = memory[ addr ];
And Xilinx's XST doesn't like nested procedural for-loops:
always @*
integer i,j;
for ( i = 0; i < MAX_I; i = i + 1 )
for ( j = i; j < MAX_I; j = j + 1 ) // <-- XST error, 'j' not recognized
as constant!
Article: 119718<jjlindula@hotmail.com> wrote in message news:1180019992.519179.25720@q66g2000hsg.googlegroups.com... > Hello, I'm about to purchase a new computer and I wanted to get some > opinions on what I should get. I mostly work with Quartus II on my job > and wanted to know what would be a good system to run the software. > I've been hearing more about dual-core and quad core systems which do > you think gives better performance running Quartus? Last, should I get > 4GB of memory or 2GB? I usually program the larger fpga devices and > compilation time takes about 30 minutes and my simulations take about > an hour. My current system is a dual processor with 2GB of memory. If > anyone can comment on what would be the best computer system I'd > greatly appreciate it. Intel's Core-2 based quad-core CPUs (Q6600, QX6700, Xeon E53xx) deliver diminishing returns beyond the dual-core models. Also, unless you're running Linux, Win XP x64, or Win/Vista 64, the most Windows will use (out of 4GB of physical RAM) is ~3.2GB, depending on what peripherals you have installed. When I upgraded from an ATI Radeon X600 (128MB) to a Geforce 7900GS (256MB), my "usable RAM" dropped from 3.6GB to 3.2GB. But I can run certain critical applications (Civilizations 4, Company of Heroes, The Sims 2) much better now, so it was a trade-off. > > thanks, > joe >Article: 119719
On 24 May 2007 07:35:52 -0700, Peter Alfke <alfke@sbcglobal.net> wrote: >Also, in order to guarantee the integrity of the ROM content, you >should not change the addresses during the set-up time window before >the clock, while CE is active. (WE inactive is not sufficient to >protect against all address set-up time violations). This is not >intuitively obvious. Hi Peter, do you have an XAPP or similar that describes that issue better? I had an X2P design a few years back that would sometimes corrupt a few bits of its BRAM ROMs when there were clock glitches (during DCM initial lock). Regards, AllanArticle: 119720
On 24 May, 21:16, Alan Myler <amy...@eircom.net> wrote: > Niv (KP) wrote: > > I need to write some timing constraints for an ProAsic device. The > > Designer tool doesn't seem to cater for what I need; as follows: > > > FPGA1 (Xilinx) outputs data on clk rising edge & FPGA2 (my Actel) > > captures data on the clk falling edge (Same clock with very low skew > > to both devices) > > Similarly Actel outputs data on clk falling edge & Xilinx capture on > > rising edge. > > I have the Xilinx input & output delays and the clock period is 30 ns. > > The clock M/S ratio is 40/60 though, so the total allowed time from > > one device clocking out to the other device clocking in is therefore > > 12 ns (40% of 30ns as worst case). PCB trace is assumed ~1ns. > > > So how do I apply the constraints to my Actel chip; I've never used an > > SDC file, so some tips or pointers to examples would be useful. > > > TIA, Niv > > You need the "set_output_delay" constraint I think. Designer "help" menu > will tell you how to use it. > > Alternatively use the Timing Analyser GUI in Designer to set the > constraints. > > Alan- Hide quoted text - > > - Show quoted text - I find the timing analyser GUI (or "Smartime") confusing. I know exactly what I want to say, but I just can't understand how to apply my requirements using the Actel GUI. I've even asked the Actel FAE and he couldn't tell me how to do it, so what chance do I have! I think a script is a far better method anyway, as it's fully repeatable without having to remember what boxes were/were not ticked etc. Niv.Article: 119721
On 24 Mai, 16:35, Peter Alfke <a...@sbcglobal.net> wrote: > You can define the BRAM content through configuration, and you can > then use the BRAM as a ROM, just by never writing new information into > it. > But remember: > Reading from a BRAM is a synchronous operation. You must supply a > clock, and the Data output changes only after the rising edge of the > clock. > Also, in order to guarantee the integrity of the ROM content, you > should not change the addresses during the set-up time window before > the clock, while CE is active. (WE inactive is not sufficient to > protect against all address set-up time violations). This is not > intuitively obvious. > Peter Alfke, Xilinx > ======================= > On May 24, 7:07 am, Lancer <peppe...@gmail.com> wrote: > Hi Peter, isnt that address setup time requirement only there for Virtex-4 because of silicon errata? or can the memory corruption occour on other Xilinx FPGA's as well? AnttiArticle: 119722
On May 24, 4:57 pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On 23 May 2007 22:57:24 -0700, sudhakar...@gmail.com wrote: > > >Hi to all > > >I am currently working on DDR2 controller for Burst Lenth 8. > >My own code is giving good results when i verified with memory model > >from MICRON. > >Now my problem is memory on the board is not sending 4 DQS clock > >pulses. it seems to be sending for burst lenth 4. > > What are you writing to the DDR's mode registers? > > - Brian Hi Brian thanks for ur response s_ddram_ba <= '0'& s_new_bank_numb ; -- active,read,write,precharge s_ddram_ba <= "10"; --emr2 s_ddram_ba <= "11" ; --emr3 s_ddram_ba <= "01" ; -- emr,ocd_exit,ocd default s_ddram_ba <= "00"; -- mr ,precharge all s_ddram_address <=s_new_row_addr ; -- active s_ddram_address <= "00" & '0' & s_new_col_addr; -- read or write s_ddram_address <= "0000000000000"; -- emr2 ,emr3 s_ddram_address <= "0010001000000"; -- emr_dll enable , emr ocd exit s_ddram_address <= "0010100110010"; -- mrdll reset s_ddram_address <= "0010000000000"; -- precharge all s_ddram_address <= "0010000110010"; -- mrdll normal operation(mrdll with out reset) s_ddram_address <= "0011111000000"; -- emr ocd default as mensioned above i am giving driving the addresses while initializing. and when I simulated with MICRON memory model the following is displyed. 238323000.0 ps INFO: Precharge bank 0 238323000.0 ps INFO: Precharge bank 1------precharge all 238323000.0 ps INFO: Precharge bank 2 238323000.0 ps INFO: Precharge bank 3 238443000.0 ps INFO: Load Mode 2 ---emr2 238533000.0 ps INFO: Load Mode 3 ---emr3 238623000.0 ps INFO: Load Mode 1 --emr with dll enable 238623000.0 ps INFO: Load Mode 1 DLL Enable = Enabled 238623000.0 ps INFO: Load Mode 1 Output Drive Strength = Full 238623000.0 ps INFO: Load Mode 1 ODT Rtt = 150 Ohm 238623000.0 ps INFO: Load Mode 1 Additive Latency = 0 238623000.0 ps INFO: Load Mode 1 OCD Program = OCD Exit 238623000.0 ps INFO: Load Mode 1 DQS_N Enable = Disabled 238623000.0 ps INFO: Load Mode 1 RDQS Enable = Disabled 238623000.0 ps INFO: Load Mode 1 Output Enable = Enabled 238713000.0 ps INFO: Load Mode 0 ----- mr with dll reset 238713000.0 ps INFO: Load Mode 0 Burst Length = 8 238713000.0 ps INFO: Load Mode 0 Burst Order = Sequential 238713000.0 ps INFO: Load Mode 0 CAS Latency = 4 238713000.0 ps INFO: Load Mode 0 Test Mode = Normal 238713000.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL 238713000.0 ps INFO: Load Mode 0 Write Recovery = 3 238713000.0 ps INFO: Load Mode 0 Power Down Mode = Fast Exit 240723000.0 ps INFO: Precharge bank 0 240723000.0 ps INFO: Precharge bank 1 ---precharge all 240723000.0 ps INFO: Precharge bank 2 240723000.0 ps INFO: Precharge bank 3 240723000.0 ps INFO: Precharge bank 0 240843000.0 ps INFO: Refresh ------two refresh commands 241635000.0 ps INFO: Refresh 242427000.0 ps INFO: Load Mode 0 242427000.0 ps INFO: Load Mode 0 Burst Length = 8 -----mr with out reset ( normal operation ) 242427000.0 ps INFO: Load Mode 0 Burst Order = Sequential 242427000.0 ps INFO: Load Mode 0 CAS Latency = 4 242427000.0 ps INFO: Load Mode 0 Test Mode = Normal 242427000.0 ps INFO: Load Mode 0 DLL Reset = Normal 242427000.0 ps INFO: Load Mode 0 Write Recovery = 3 242427000.0 ps INFO: Load Mode 0 Power Down Mode = Fast Exit 242517000.0 ps INFO: Load Mode 1 242517000.0 ps INFO: Load Mode 1 DLL Enable = Enabled --- emr with ocd default 242517000.0 ps INFO: Load Mode 1 Output Drive Strength = Full 242517000.0 ps INFO: Load Mode 1 ODT Rtt = 150 Ohm 242517000.0 ps INFO: Load Mode 1 Additive Latency = 0 242517000.0 ps INFO: Load Mode 1 OCD Program = OCD Default 242517000.0 ps INFO: Load Mode 1 DQS_N Enable = Disabled 242517000.0 ps INFO: Load Mode 1 RDQS Enable = Disabled 242517000.0 ps INFO: Load Mode 1 Output Enable = Enabled 242607000.0 ps INFO: Load Mode 1 242607000.0 ps INFO: Load Mode 1 DLL Enable = Enabled 242607000.0 ps INFO: Load Mode 1 Output Drive Strength = Full -----emr with ocd exit 242607000.0 ps INFO: Load Mode 1 ODT Rtt = 150 Ohm 242607000.0 ps INFO: Load Mode 1 Additive Latency = 0 242607000.0 ps INFO: Load Mode 1 OCD Program = OCD Exit 242607000.0 ps INFO: Load Mode 1 DQS_N Enable = Disabled 242607000.0 ps INFO: Load Mode 1 RDQS Enable = Disabled 242607000.0 ps INFO: Load Mode 1 Output Enable = Enabled 242607000.0 ps INFO: Initialization Sequence is complete ----initialization is successfulll 244977000.0 ps INFO: Refresh 245241000.0 ps INFO: Activate bank 0 row 0000 245271000.0 ps INFO: Read bank 0 col 000, auto precharge 0 245271000.0 ps INFO: Read bank 0 col 000, auto precharge 0 245271000.0 ps INFO: Read bank 0 col 000, auto precharge 0 245271000.0 ps INFO: Read bank 0 col 000, auto precharge 0 _--------------------------------------------------frequency of operation is 198 MHZ or 132 MHZ what i am observing only two sine pulses on DQS while reading actually i need 4 clock pulses to latch 8 dqs bits if any IDEA with the above results we observed please HELP me I need it desperately.............. thanks and regards sudhakarArticle: 119723
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:u4pb535aii2c97o28bpi2812ljapqmh9pb@4ax.com... > On Thu, 24 May 2007 07:23:01 -0700, austin <austin@xilinx.com> wrote: > > > Does an LVDS transmitter have an impedance? The ones I've played with > seem to behave like current sources; unloaded, the diff outputs swing > (slowly!) almost rail-to-rail. That said, presenting the transmitter > with an equivalent 100 ohm net diff load will normalize the swing to > standard levels and speed things up a bit as compared to letting them > see a 173 or whatever diff load. > > John > Hi John, Have a look at the link I posted yesterday. This one:- http://www.maxim-ic.com/appnotes.cfm/an_pk/291 It shows the output structure for LVDS. The (12mA) current source has high impedance, so the output impedance is determined by the resistors show. I think the LVDS transmitters you mention must have some other type of structure. Can you post what they were? HTH, Syms.Article: 119724
Hi to all
i am implementing my own DDR 2 @400 controller
my code for BANK AND ADREES lines is while initializing
s_ddram_ba <= '0'& s_new_bank_numb ; --
active,read,write,precharge
s_ddram_ba <= "10";
--emr2
s_ddram_ba <= "11" ;
--emr3
s_ddram_ba <= "01" ; --
emr,ocd_exit,ocd default
s_ddram_ba <= "00";
--mr ,precharge all
s_ddram_address
<=s_new_row_addr ; --active
s_ddram_address <= "00" & '0' &
s_new_col_addr; -- read or write--- no
auto precharge
s_ddram_address <=
"0000000000000"; --emr2 ,emr3
s_ddram_address <= "0010001000000"; --
emr_dll enable , emr ocd exit
s_ddram_address <= "0010100110010";
-- mrdll reset
s_ddram_address <= "0010000000000"; --
precharge all
s_ddram_address <= "0010000110010"; --
mrdll normal operation(mrdll
with out reset)
s_ddram_address <=
"0011111000000"; -- emr ocd default
as mensioned above i am giving driving the
addresses while
initializing and when I simulated with MICRON memory model the
following is messages are
displyed.
after 238 us ie CKE is LOW ( now CKE is made high)
and
after 400 ns waiting
238323000.0 ps INFO: Precharge bank 0
238323000.0 ps INFO: Precharge bank 1------precharge all
238323000.0 ps INFO: Precharge bank 2
238323000.0 ps INFO: Precharge bank 3
238443000.0 ps INFO: Load Mode 2 ---emr2
238533000.0 ps INFO: Load Mode 3 ---emr3
238623000.0 ps INFO: Load Mode
1 --emr with dll enable
238623000.0 ps INFO: Load Mode 1 DLL Enable = Enabled
238623000.0 ps INFO: Load Mode 1 Output Drive Strength = Full
238623000.0 ps INFO: Load Mode 1 ODT Rtt = 150 Ohm
238623000.0 ps INFO: Load Mode 1 Additive Latency = 0
238623000.0 ps INFO: Load Mode 1 OCD Program = OCD Exit
238623000.0 ps INFO: Load Mode 1 DQS_N Enable = Disabled
238623000.0 ps INFO: Load Mode 1 RDQS Enable = Disabled
238623000.0 ps INFO: Load Mode 1 Output Enable = Enabled
238713000.0 ps INFO: Load Mode
0 ----- mr with dll reset
238713000.0 ps INFO: Load Mode 0 Burst Length = 8
238713000.0 ps INFO: Load Mode 0 Burst Order = Sequential
238713000.0 ps INFO: Load Mode 0 CAS Latency = 4
238713000.0 ps INFO: Load Mode 0 Test Mode = Normal
238713000.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
238713000.0 ps INFO: Load Mode 0 Write Recovery = 3
238713000.0 ps INFO: Load Mode 0 Power Down Mode = Fast Exit
240723000.0 ps INFO: Precharge bank 0
240723000.0 ps INFO: Precharge bank
1 ---precharge all
240723000.0 ps INFO: Precharge bank 2
240723000.0 ps INFO: Precharge bank 3
240723000.0 ps INFO: Precharge bank 0
240843000.0 ps INFO: Refresh
------two refresh commands
241635000.0 ps INFO: Refresh
242427000.0 ps INFO: Load Mode 0
242427000.0 ps INFO: Load Mode 0 Burst Length =
8 -----mr with out reset ( normal operation )
242427000.0 ps INFO: Load Mode 0 Burst Order = Sequential
242427000.0 ps INFO: Load Mode 0 CAS Latency = 4
242427000.0 ps INFO: Load Mode 0 Test Mode = Normal
242427000.0 ps INFO: Load Mode 0 DLL Reset = Normal
242427000.0 ps INFO: Load Mode 0 Write Recovery = 3
242427000.0 ps INFO: Load Mode 0 Power Down Mode = Fast Exit
242517000.0 ps INFO: Load Mode 1
242517000.0 ps INFO: Load Mode 1 DLL Enable =
Enabled --- emr with ocd default
242517000.0 ps INFO: Load Mode 1 Output Drive Strength = Full
242517000.0 ps INFO: Load Mode 1 ODT Rtt = 150 Ohm
242517000.0 ps INFO: Load Mode 1 Additive Latency = 0
242517000.0 ps INFO: Load Mode 1 OCD Program = OCD Default
242517000.0 ps INFO: Load Mode 1 DQS_N Enable = Disabled
242517000.0 ps INFO: Load Mode 1 RDQS Enable = Disabled
242517000.0 ps INFO: Load Mode 1 Output Enable = Enabled
242607000.0 ps INFO: Load Mode 1
242607000.0 ps INFO: Load Mode 1 DLL Enable = Enabled
242607000.0 ps INFO: Load Mode 1 Output Drive Strength =
Full -----emr with ocd exit
242607000.0 ps INFO: Load Mode 1 ODT Rtt = 150 Ohm
242607000.0 ps INFO: Load Mode 1 Additive Latency = 0
242607000.0 ps INFO: Load Mode 1 OCD Program = OCD Exit
242607000.0 ps INFO: Load Mode 1 DQS_N Enable = Disabled
242607000.0 ps INFO: Load Mode 1 RDQS Enable = Disabled
242607000.0 ps INFO: Load Mode 1 Output Enable = Enabled
242607000.0 ps INFO: Initialization Sequence is
complete ----initialization is successfulll
244977000.0 ps INFO: Refresh
245241000.0 ps INFO: Activate bank 0 row 0000
245271000.0 ps INFO: Read bank 0 col 000, auto precharge 0
245271000.0 ps INFO: Read bank 0 col 000, auto precharge 0
245271000.0 ps INFO: Read bank 0 col 000, auto precharge 0
245271000.0 ps INFO: Read bank 0 col 000, auto precharge 0
_--------------------------------------------------frequency of
operation is 198 MHZ or 132 MHZ
what i am observing only two sine pulses on DQS while reading
actually i need 4 clock pulses to latch 8 dqs bits
if any IDEA with the above results we observed please HELP me I need
it desperately..............
thanks and regards
sudhakar
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