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Messages from 119450

Article: 119450
Subject: Re: video soltion provider
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Sat, 19 May 2007 12:42:54 -0700
Links: << >>  << T >>  << A >>
> I need video system with following main specifications.

> 1) Input : standard video formats

I suppose the most standard video format is NTSC, although
this is a standard that is being replaced. Still the most
inexpensive. For Industrial applications where the timing
needs to be controled, camera link is still the standard,
although that is being replaced by GigEthernet. USB webcams
and Firewire cameras.

So a lot of choices.

> 2) compression: MPEG4/MPEG2 etc.

Can be done on FPGAs.

> 3) Output: RS232

Very low bandwidth.

> 4) Decoder: Soft decoder in PC

Not my expertise.

> Is there any company who offers customized solutions in this area.
> Thanks

Brad Smallridge
AiVision




Article: 119451
Subject: Re: releasing some FPGA tools-ip as open-source
From: Tommy Thorn <tommy.thorn@gmail.com>
Date: 19 May 2007 14:34:52 -0700
Links: << >>  << T >>  << A >>
On May 19, 8:57 am, Antti <Antti.Luk...@googlemail.com> wrote:
> I will peek more into the "treasure trove" and upload the findings as
> my time permits.

Keep us posted.

> right now i need to port the systemACE player to this tiny module
>
> http://www.dev-kit.org/

So small it's hard to hold, heh. There could hardly be any less
information on your(?) web site. Eg. what's the microcontroller, how
many IO ports, etc.

Cheers,
Tommy


Article: 119452
Subject: Re: Visio logic symbols
From: Neil Steiner <neil.steiner@vt.edu>
Date: Sat, 19 May 2007 20:54:47 -0400
Links: << >>  << T >>  << A >>
> Does anyone know of a location from which to download simple logic
> symbol shapes for Visio (and gate, or gate, etc)?

Under Visio 2003 Professional, go to File -> Shapes -> Electrical 
Engineering -> Analog and Digital Logic (US Units).  Not sure about 
other versions of Visio, but I believe basic gates are included in just 
about all of them.

Article: 119453
Subject: Re: VHDL newbie: building sequential circuits with basic gates
From: "KJ" <kkjennings@sbcglobal.net>
Date: Sat, 19 May 2007 21:33:08 -0400
Links: << >>  << T >>  << A >>

"Colin Paul Gloster" <Colin_Paul_Gloster@ACM.org> wrote in message 
news:f2hh0s$na5$1@newsserver.cilea.it...
> In news:hWW2i.1605$4Y.801@newssvr19.news.prodigy.net timestamped Thu,
> 17 May 2007 07:22:50 -0400, "KJ" <kkjennings@sbcglobal.net> posted:
> "[..]
>
> [..]
> 1. Simulation allows for zero propogation delays through logic
> 2. The logic type most commonly used (i.e. std_logic) allows signals to be
> 'unknown'.
>
> Neither of these two things model the real world behaviour of anything at
> all....and yet they are both powerful aids for designing logic properly 
> and
> are 'good' things from a design perspective.
>
> [..]"
>
>
> Hi,
>
> How can zero delays or std_logic be useful?
>
> Regards,
> Colin Paul Gloster

As to how zero delays can be useful, I'd say that from the perspective of 
designing logic to implement a particular function the delay used is usually 
irrelevant so zero delay is just as useful as 1 ns, 1 ps, or any other 
delay.  If there was some 'default' non-zero delay built into the design 
language or the simulator then no doubt that default time will just get in 
the way of somebody trying to create some new design at some point because 
they are trying to design something that needs to run at or near a speed 
that is comparable to this 'default' time.  The definition of 'delta time' 
which is infintesimally small and simply represents extra churns by the 
simulation engine that are still completed in 'zero time' permanently gets 
around this issue.  The fact that zero delay is not physically possible in 
the real world just never gets in the way of designing whatever it is that 
you're designing.

std_logic (and std_ulogic) are useful because of the meta-logical values 
like 'Z', 'U', and 'X' even though in the real world, logical signals will 
never be 'U' or 'X', they will always be at a voltage/current level that 
corresponds to a logical '0' or '1' or tri-stated.  The 'unknowns' are great 
because when you're testing your design in simulation those unknown values 
will propogate through the logic and allow for very rapid determination of 
logic holes in the design.  Using a type such as 'boolean' or 'bit' to do 
your design would result in these signals getting assigned default values 
that may or may not correspond to what a real device would do and yet by 
virtue of whatever value happened to get assigned, this may cause downstream 
logic to appear to behave properly in simulation but fail in the real world. 
This is the types of thing that the 'unknowns' flush out quite quickly

From a modelling perspective, when you're trying to create a behavioural 
model of some existing thing the opposite can usually apply.  'Zero' delays 
and 'unknowns' for logic don't have much value.  Since the original poster 
was querying about constructing storage elements from basic logic gates, 
this would fall into the 'modelling side' rather than the 'design side' of 
things so I put my 2 cents in with that in mind and added the caution about 
not trying to use that advice if you're doing design.

Kevin Jennings




Article: 119454
Subject: Re: How to insert tab in Write() function in VHDL
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: 19 May 2007 18:58:35 -0700
Links: << >>  << T >>  << A >>
On May 19, 7:09 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Sat, 19 May 2007 12:06:25 +0100,
>
> <symon_bre...@hotmail.com> wrote:
> >>> I want to know which one is tabulator (tab).
>
> >> ht
> >or vt
>
> I know what VT did on an ASR33 Teletype, but
> I'm not at all sure what it's supposed to do
> these days ...
>
> Tabs of any kind are extremely bad news anyway,
> because their appearance is so strongly dependent
> on the editor or viewer that you use to do the
> rendering.  I hate 'em.  Compute how many spaces
> you need and insert the spaces explicitly.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

Hi Jonathan,
This time I don't agree with your opinion.

What I do is to print out all related waveforms I am interested in and
using tab is to make me easier to manually check if the waveforms are
right so that a software can be used later to check the waveforms
without 1 clock after another to manually check waveforms.

'ht' works for tab in VHDL.

Salvain,
Thank you.

Weng


Article: 119455
Subject: Re: releasing some FPGA tools-ip as open-source
From: Eric Smith <eric@brouhaha.com>
Date: 19 May 2007 21:26:34 -0700
Links: << >>  << T >>  << A >>
Antti wrote:
> released
> 1) JTAG TAP+BSCAN softcore, can use as BSCAN in fabric to use
> chipscope-mdm when FPGA jtag pins not accessible
> 2) SystemACE tools: dump, compress, player

Thanks!  Those will both be very useful.

Eric

Article: 119456
Subject: Re: releasing some FPGA tools-ip as open-source
From: Antti <Antti.Lukats@googlemail.com>
Date: 20 May 2007 01:27:17 -0700
Links: << >>  << T >>  << A >>
Tommy Thorn schrieb:
> On May 19, 8:57 am, Antti <Antti.Luk...@googlemail.com> wrote:
> > I will peek more into the "treasure trove" and upload the findings as
> > my time permits.
>
> Keep us posted.
>
> > right now i need to port the systemACE player to this tiny module
> >
> > http://www.dev-kit.org/
>
> So small it's hard to hold, heh. There could hardly be any less
> information on your(?) web site. Eg. what's the microcontroller, how
> many IO ports, etc.
>
> Cheers,
> Tommy

Hi Tommy

you are right, its hard to provide less info :(
sorry - I am working hard for the product development so some things
are badly behind

feature list:
http://wiki.dev-kit.org/index.php/DevKitAtTiny45

but basically saying that the module is based on Atmel AVR ATtiny45
should already be sufficient, the feature list is mostly copy of atmel
datasheet.

from 6 I/Os 1 is not bonded out, it is used as sd-card clock and LED,
all other 5 pins are bonded and can be used as user IO,  reset is
disabled by fuse setting so the 8 pin MCU in using all 6 non-power
pins as user io.

from 4KB flash memory 1KByte is used by the sd-card self updater, so 3
kbyte is left over for user application.
ATtiny85 version would have 7Kbyte for user appplication, but even
3kbyte is normally sufficient for small microcontroller.

I have worked a lot with FPGA configuration solution (like my MMC card
CPLD ip core for FPGA config published at opencores..) so this module
will also be used for FPGA configuration, as it can stream data from
micro-SD making it real nice and low cost FPGA configurator device
(with updateable config algorithm)

Antti


Article: 119457
Subject: Re: EDK 8.1i to EDK 9.1i UCF file errors
From: Joseph Samson <jsamson@the-company-name.com>
Date: Sun, 20 May 2007 17:26:44 GMT
Links: << >>  << T >>  << A >>
Nju Njoroge wrote:
> Hello,
> 
> In our *working* EDK 8.1i project, we locked a DCM in the following
> manner in the UCF file (located in <proj_dir>/data/system.ucf):
  [snip]...

comment out the DCM LOC in your .ucf file, then run place and route. 
Open the design in FPGA Editor, find the DCM and look at the instance 
name. Now uncomment the DCM LOC and substitute the instance name that 
ISE 9.1i assigned. Rerun the place and route.

---
Joe Samson
Pixel Velocity

Article: 119458
Subject: Signal Assignment bugs in Quartus-II ... AGAIN!
From: edick@idcomm.com
Date: 20 May 2007 10:48:30 -0700
Links: << >>  << T >>  << A >>
I've repeatedly reported this blatant and repeatedly acknowledged bug
in Quartus-II's schematic editor, yet it appears it's still there in
all its splendor in v7.1.

When I assign a bus named <NAME[K..0]> the software arbitrarily
appends another signal group <NAMEK..NAME0> and binds them to
arbitrary pins and misassigns my signals NAME[K] .. NAME[0] to other
pin numbers, which, among other things, produces conflicts of
assignment, not to mention that it completely fouls up my signal
assignments.

Has anybody figured out how to get ONLY the CORRECT pin assignments to
be used in the design?


Article: 119459
Subject: Signal Assignment bugs in Quartus-II ... AGAIN!
From: edick@idcomm.com
Date: 20 May 2007 10:49:03 -0700
Links: << >>  << T >>  << A >>
I've repeatedly reported this blatant and repeatedly acknowledged bug
in Quartus-II's schematic editor, yet it appears it's still there in
all its splendor in v7.1.

When I assign a bus named <NAME[K..0]> the software arbitrarily
appends another signal group <NAMEK..NAME0> and binds them to
arbitrary pins and misassigns my signals NAME[K] .. NAME[0] to other
pin numbers, which, among other things, produces conflicts of
assignment, not to mention that it completely fouls up my signal
assignments.

Has anybody figured out how to get ONLY the CORRECT pin assignments to
be used in the design?


Article: 119460
Subject: Re: VHDL newbie: building sequential circuits with basic gates
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: 20 May 2007 18:13:55 GMT
Links: << >>  << T >>  << A >>
In news:rzN3i.3708$4Y.70@newssvr19.news.prodigy.net timestamped Sat,
19 May 2007 21:33:08 -0400, "KJ" <kkjennings@sbcglobal.net> posted:
"[..]

As to how zero delays can be useful, I'd say that from the perspective of
designing logic to implement a particular function the delay used is usually
irrelevant so zero delay is just as useful as 1 ns, 1 ps, or any other
delay. [..]"

Thank you for the insightful answer re zero delays.


"std_logic (and std_ulogic) are useful because of the meta-logical values
like 'Z', 'U', and 'X' even though in the real world, logical signals will
never be 'U' or 'X', they will always be at a voltage/current level that
corresponds to a logical '0' or '1' or tri-stated.  The 'unknowns' are great
because when you're testing your design in simulation those unknown values
will propogate through the logic and allow for very rapid determination of
logic holes in the design.  Using a type such as 'boolean' or 'bit' to do
your design would result in these signals getting assigned default values
[..]

[..]"

This is more an explanation of how std_logic is better than Boolean or
bit instead of an explanation of how std_logic could be considered to
be useful, as all of those advantages apply to std_ulogic as well and
std_ulogic seems to be better, which you stated in
news:eLUEh.2278$jx3.1392@newssvr25.news.prodigy.net 
in February 2007.

Regards,
Colin Paul Gloster

Article: 119461
Subject: Re: Single Chip MSX computer full schematic and VHDL sources
From: spartan3wiz <magnus.wedmark@gmail.com>
Date: 20 May 2007 11:29:07 -0700
Links: << >>  << T >>  << A >>
On May 18, 6:47 pm, Antti <Antti.Luk...@googlemail.com> wrote:
> Hi
>
> http://code.google.com/p/fpga-retro/downloads/list
>
> there is the distribution archive for the one chip MSX project
> would be fun to convert it for some xilinx board, :)
>
> I have been hunting for those VHDL code for ages, all links ended
> dead somewhere, but with heavy searching the archive was found too.
>
> Antti

Thanks f=F6r sharing Antti!! Have you begun converting it to the XIlinx
platform? How much work is it?
I just love trying out/collecting new platforms for my Starter-Kit.
After a look in the archive its originally for the Altera FPGA's but
the standard T80
Is this the same product as the One Chip MSX at: http://www.bazix.nl/onechi=
pmsx.html
If so that means that the product builds on open-source, is this OK
with the creators of f.e. T80-core? If I were to build/construct a
similar old-style platform but would be using these basic building
blocks that are downloadable, would this be OK? Can anyone explain the
license issues with this type of hardware-constructs?


Article: 119462
Subject: Re: Single Chip MSX computer full schematic and VHDL sources
From: nico@puntnl.niks (Nico Coesel)
Date: Sun, 20 May 2007 19:25:38 GMT
Links: << >>  << T >>  << A >>
Antti <Antti.Lukats@googlemail.com> wrote:

>Hi
>
>http://code.google.com/p/fpga-retro/downloads/list
>
>there is the distribution archive for the one chip MSX project
>would be fun to convert it for some xilinx board, :)
>
>I have been hunting for those VHDL code for ages, all links ended
>dead somewhere, but with heavy searching the archive was found too.
>
>Antti

Cool! Is it the MSX-I or MSX-II? I believe I have the MSX-II video
chip in VHDL somewhere... Never bothered to do something with it
though.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Article: 119463
Subject: Re: Single Chip MSX computer full schematic and VHDL sources
From: spartan3wiz <magnus.wedmark@gmail.com>
Date: 20 May 2007 13:14:15 -0700
Links: << >>  << T >>  << A >>
On 20 Maj, 20:29, spartan3wiz <magnus.wedm...@gmail.com> wrote:
> On May 18, 6:47 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > Hi
>
> >http://code.google.com/p/fpga-retro/downloads/list
>
> > there is the distribution archive for the one chip MSX project
> > would be fun to convert it for some xilinx board, :)
>
> > I have been hunting for those VHDL code for ages, all links ended
> > dead somewhere, but with heavy searching the archive was found too.
>
> > Antti
>
> Thanks f=F6r sharing Antti!! Have you begun converting it to the XIlinx
> platform? How much work is it?
> I just love trying out/collecting new platforms for my Starter-Kit.
> After a look in the archive its originally for the Altera FPGA's but
> the standard T80
> Is this the same product as the One Chip MSX at:http://www.bazix.nl/onech=
ipmsx.html
> If so that means that the product builds on open-source, is this OK
> with the creators of f.e. T80-core? If I were to build/construct a
> similar old-style platform but would be using these basic building
> blocks that are downloadable, would this be OK? Can anyone explain the
> license issues with this type of hardware-constructs?

After doing a quick fix-up (ugly code changes made), it builds to only
54% of my Spartan3-200K. Nice!
What I've done so far is to change some syntax for array 'range and
'high that seem to be non-standard but seem to work OK. I've also
commented out the altera-specific RAM-instanciations and PLL-usages.
These would of course only need to be mapped against BlockRAM and
DCM's, is that correct? I need to continue working on a VHDL
laboration but it would be nice to see the computer starting up.
Please post/CVS changes somewhere if somebody else is better than me
on porting from Quartus to ISE. Good luck!


Article: 119464
Subject: Re: Signal Assignment bugs in Quartus-II ... AGAIN!
From: "Icky Thwacket" <it@it.it>
Date: Sun, 20 May 2007 21:22:51 +0100
Links: << >>  << T >>  << A >>

<edick@idcomm.com> wrote in message 
news:1179683343.527144.240710@y18g2000prd.googlegroups.com...
> I've repeatedly reported this blatant and repeatedly acknowledged bug
> in Quartus-II's schematic editor, yet it appears it's still there in
> all its splendor in v7.1.
>
> When I assign a bus named <NAME[K..0]> the software arbitrarily
> appends another signal group <NAMEK..NAME0> and binds them to
> arbitrary pins and misassigns my signals NAME[K] .. NAME[0] to other
> pin numbers, which, among other things, produces conflicts of
> assignment, not to mention that it completely fouls up my signal
> assignments.
>
> Has anybody figured out how to get ONLY the CORRECT pin assignments to
> be used in the design?
>

Its not a bug, you clearly do not fully understand the rules for bus naming.

FRED[7..0] includes the members FRED[7] down to FRED[0] and also the members 
FRED7 down to FRED0.

FRED[7] is exactly the same as FRED7 etc.

If you have already independently named a node FRED7 for instance, it will 
become part of the FRED[7..0] bus - with the bus conflicts/pin renaming you 
describe.

If you want really confusing fun try naming a bus like FRED372[7..0]

Icky 



Article: 119465
Subject: Re: VHDL newbie: building sequential circuits with basic gates
From: "KJ" <kkjennings@sbcglobal.net>
Date: Sun, 20 May 2007 17:19:47 -0400
Links: << >>  << T >>  << A >>

> "std_logic (and std_ulogic) are useful because of the meta-logical values
> like 'Z', 'U', and 'X' even though in the real world, logical signals will
> never be 'U' or 'X', they will always be at a voltage/current level that
> corresponds to a logical '0' or '1' or tri-stated.  The 'unknowns' are 
> great
> because when you're testing your design in simulation those unknown values
> will propogate through the logic and allow for very rapid determination of
> logic holes in the design.  Using a type such as 'boolean' or 'bit' to do
> your design would result in these signals getting assigned default values
> [..]
>
> [..]"
>
> This is more an explanation of how std_logic is better than Boolean or
> bit instead of an explanation of how std_logic could be considered to
> be useful, as all of those advantages apply to std_ulogic as well and
> std_ulogic seems to be better, which you stated in
> news:eLUEh.2278$jx3.1392@newssvr25.news.prodigy.net
> in February 2007.
>
I guess I'm not sure what you're getting at.  It sounds like you accept my 
explanation of how std_logic is better than boolean or bit in the particular 
context that I've described but are not accepting that as being evidence of 
std_logic being 'useful'.

std_logic and std_ulogic share all of the same advantages and disadvantages 
as they relate to the particular point of propagating 'unknown' logic 
levels.  I didn't distinguish between the two here since the essential 
element was that the original poster had questions related to modelling and 
by necessity was going to be creating combinatorial feedback paths in order 
to create those models just like how it is done in an actual part.  The 
question seemed to be about how their are 'issues' in doing this and all I 
was doing was clarifying those issues as they related to the particular 
context of modelling storage elements as the poster was instructed to do.

The earlier discussion about std_ulogic having advantages over std_logic 
that you referenced was in a totally different context, that of design. 
While all of those advantages and disadvantages also apply to most 
situations when modelling device behaviour, one particular situation where 
they have a huge disadvantage is when modelling a combinatorial feedback 
path as the original poster was trying to do.

Another example of such a difference between when a particular type is good 
to use or not would be between the use of type 'unsigned' or type 'natural' 
when creating a counter (or adder).  In the hands of the more skilled 
designer, type 'natural' is usually preferred; in the hands of the less 
skilled the use of type 'natural' can cause problems because signals of type 
natural will always magically initialize to 0 in simulation.  In a real 
device that might not happen to guarantee such behaviour and for which the 
less skilled designer has forgotten to design in a path to reset the counter 
they can run into issues when trying to get their stuff working on a real 
board.  Had that less skilled designer instead used an 'unsigned' type for 
the counter they would have cleared up the design issues during simulation 
because the forgotten reset path would have caused them to have 'unknowns' 
that need to be cleared up.  Here the difference in context is not the 
design itself, it's not design versus modelling.it is simply the skill of 
the designer.  So which is the 'better' choice?  You could say it's 
'unsigned' but there is a simulation performance penalty to be paid in using 
'unsigned' over 'natural'.  So is that performance penalty a 'good' thing if 
you have a skilled designer?  Maybe not.

The bottom line is each data type is 'useful' and probably in some sense 
'better' than any other data type in a particular context, but may fall flat 
when used in a different context.

Kevin Jennings 



Article: 119466
Subject: Re: How to insert tab in Write() function in VHDL
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Sun, 20 May 2007 13:51:23 -0800
Links: << >>  << T >>  << A >>
Weng Tianxiang wrote:
> Hi,
> I want to insert tab in write() function in VHDL.

(snip)

> 	type character is (
> 		nul, soh, stx, etx, eot, enq, ack, bel,
> 		bs,  ht,  lf,  vt,  ff,  cr,  so,  si,
> 		dle, dc1, dc2, dc3, dc4, nak, syn, etb,
> 		can, em,  sub, esc, fsp, gsp, rsp, usp,
> 
> 		' ', '!', '"', '#', '$', '%', '&', ''',
> 		'(', ')', '*', '+', ',', '-', '.', '/',
> 		'0', '1', '2', '3', '4', '5', '6', '7',
> 		'8', '9', ':', ';', '<', '=', '>', '?',

> I want to know which one is tabulator (tab).

ht is horizontal tab, vt is vertical tab.  There are terminals
that know what to do with one or both of those.

-- glen


Article: 119467
Subject: Re: Signal Assignment bugs in Quartus-II ... AGAIN!
From: Mark McDougall <markm@vl.com.au>
Date: Mon, 21 May 2007 10:30:06 +1000
Links: << >>  << T >>  << A >>
edick@idcomm.com wrote:

> Has anybody figured out how to get ONLY the CORRECT pin assignments to
> be used in the design?

Use a HDL?

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 119468
Subject: Re: Single Chip MSX computer full schematic and VHDL sources
From: Antti <Antti.Lukats@googlemail.com>
Date: 21 May 2007 00:14:05 -0700
Links: << >>  << T >>  << A >>
On 20 Mai, 22:14, spartan3wiz <magnus.wedm...@gmail.com> wrote:
> On 20 Maj, 20:29, spartan3wiz <magnus.wedm...@gmail.com> wrote:
> > On May 18, 6:47 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > Hi
>
> > >http://code.google.com/p/fpga-retro/downloads/list
>
> > > there is the distribution archive for the one chip MSX project
> > > would be fun to convert it for some xilinx board, :)
>
> > > I have been hunting for those VHDL code for ages, all links ended
> > > dead somewhere, but with heavy searching the archive was found too.
>
> > > Antti
>
> > Thanks f=F6r sharing Antti!! Have you begun converting it to the XIlinx
> > platform? How much work is it?
> > I just love trying out/collecting new platforms for my Starter-Kit.
> > After a look in the archive its originally for the Altera FPGA's but
> > the standard T80
> > Is this the same product as the One Chip MSX at:http://www.bazix.nl/one=
chipmsx.html
> > If so that means that the product builds on open-source, is this OK
> > with the creators of f.e. T80-core? If I were to build/construct a
> > similar old-style platform but would be using these basic building
> > blocks that are downloadable, would this be OK? Can anyone explain the
> > license issues with this type of hardware-constructs?
>
> After doing a quick fix-up (ugly code changes made), it builds to only
> 54% of my Spartan3-200K. Nice!
> What I've done so far is to change some syntax for array 'range and
> 'high that seem to be non-standard but seem to work OK. I've also
> commented out the altera-specific RAM-instanciations and PLL-usages.
> These would of course only need to be mapped against BlockRAM and
> DCM's, is that correct? I need to continue working on a VHDL
> laboration but it would be nice to see the computer starting up.
> Please post/CVS changes somewhere if somebody else is better than me
> on porting from Quartus to ISE. Good luck!- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -

some answers
1) yes this is the stuff referenced from bazix.nl
2) yes, it is based on opensource IP's, there archive as "found" had
no separate license restrictions applied... so I dont see any issues
using the code base

3) if you or anyone wants to contribute, you are welcome to join the
project(s) at code.google.com  there are all projects tools including
code repository (SVN) already available, i think all that is needed is
googlemail account (if needed I can send invite)

Antti






Article: 119469
Subject: Re: VHDL newbie: building sequential circuits with basic gates
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: 21 May 2007 07:16:46 GMT
Links: << >>  << T >>  << A >>
In news:XX24i.1173$u56.485@newssvr22.news.prodigy.net timestamped Sun,
20 May 2007 17:19:47 -0400, "KJ" <kkjennings@sbcglobal.net> posted:
"[..]
I guess I'm not sure what you're getting at.  It sounds like you accept my
explanation of how std_logic is better than boolean or bit in the particular
context that I've described but are not accepting that as being evidence of
std_logic being 'useful'."

Yes.

"std_logic and std_ulogic share all of the same advantages and disadvantages
as they relate to the particular point of propagating 'unknown' logic
levels.  I didn't distinguish between the two here since the essential
element was that the original poster had questions related to modelling and
by necessity was going to be creating combinatorial feedback paths in order
to create those models just like how it is done in an actual part.  The
question seemed to be about how their are 'issues' in doing this and all I
was doing was clarifying those issues as they related to the particular
context of modelling storage elements as the poster was instructed to do.

The earlier discussion about std_ulogic having advantages over std_logic
that you referenced was in a totally different context, that of design."


Ah, I had not realized that std_ulogic is better than std_logic for
design but not modelling.



"While all of those advantages and disadvantages also apply to most
situations when modelling device behaviour, one particular situation where
they have a huge disadvantage is when modelling a combinatorial feedback
path as the original poster was trying to do."

Just to clarify: does std_ulogic have a huge disadvantage in contrast
to std_logic when modelling combinatorial feedback?



"[..]  In the hands of the more skilled
designer, type 'natural' is usually preferred; in the hands of the less
skilled the use of type 'natural' can cause problems because signals of type
natural will always magically initialize to 0 in simulation.  In a real
device that might not happen to guarantee such behaviour and for which the
less skilled designer has forgotten to design in a path to reset the counter
they can run into issues when trying to get their stuff working on a real
board.  Had that less skilled designer instead used an 'unsigned' type for
the counter they would have cleared up the design issues during simulation
because the forgotten reset path would have caused them to have 'unknowns'
that need to be cleared up.  Here the difference in context is not the
design itself, it's not design versus modelling.it is simply the skill of
the designer."

I understand and may agree with this point but I disagree with the
particular example as being an issue of skill... I would classify this
as more of an issue of whether the designers know what their tools do.

"[..]

The bottom line is each data type is 'useful' and probably in some sense
'better' than any other data type in a particular context, but may fall flat
when used in a different context."

Understood.

Thanks,
Colin Paul Gloster

Article: 119470
Subject: AccelDSP Systemgenerator ML403
From: eric <erixx@gmx.net>
Date: Mon, 21 May 2007 09:27:16 +0200
Links: << >>  << T >>  << A >>
Hello,
i need help with my ml403.
I would like to get a my ML403 Board from Xilinx run with 
Systemgeneratior. That i can make a Ethernet connection between Matlab 
and the Board.
Where do i find informations about that? From Xilinx is only the ML402 
directly supported.

Thanks a lot!


Eric

Article: 119471
Subject: UART Receiver Parity Check
From: Anson.Stuggart@gmail.com
Date: 21 May 2007 01:19:18 -0700
Links: << >>  << T >>  << A >>
Hello,

I'm trying to learn VHDL and here I'm adding a parity bit to Ben
Cohen's UART Receiver. RxReg(9) is incoming parity bit from
transmitter side. A 0 output at Parity_err means no parity error
detected and otherwise. The receiver has to match the incoming parity
bit with its own parity bit which is calculated using XOR of its data
byte, RxReg(8 downto 0). My statement below is giving me a full byte
delay because my control statements for the parity check. I think it's
because of the process statement, but that's all I can think of now.

can someone let me know how to fix this?

Thanks,
AS
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-------------------------------------------------------------------------------
--
--   Project     :  ATEP
--   File name   :  uartrx.vhd
--   Title       :  UART Receiver
--   Description :  UART receiver  selection
--
-------------------------------------------------------------------------------
--   Revisions   :
--          Date                Author          Revision
Comments
-- Sat Oct 30 10:05:49 1994     cohen   Rev A           Creation
-------------------------------------------------------------------------------
entity UartRx_Nty is
  port (Clk16xT       : in      std_logic; -- 16 of these clocks per
bit
        ResetF        : in      std_logic;
        Serial_InT    : in      std_logic;
        DataRdyT      : out     boolean;
        DataOuT       : out     std_logic_Vector(7 downto 0);
        Parity_err    : out     std_logic; -- Parity Error Output
        BitClkT       : out     std_logic); -- same speed clock as Tx
end UartRx_Nty;


architecture UartRx_Beh of UartRx_Nty is
  subtype Int0to15_Typ is integer range 0 to 15;
  constant RxInit_c : std_logic_Vector(10 downto 0) := "11111111111";
  signal RxReg_s   : std_logic_Vector(10 downto 0); -- the receive
register
  signal Count16_s : Int0to15_Typ;            --  for divide by 16
  signal RxMT_s    : boolean;            --   Receive register empty
  signal RxIn_s      : std_logic;                --   registered
serial input
  signal Parity_Reg : std_logic;

begin  --  UartRx_Beh
 
-----------------------------------------------------------------------------
  --  Process:   Xmit_Lbl
  --  Purpose:   Models the receive portion of a UART.
  --             Operation is as follows:
  --             . All operations occur on rising edge of Clk16xT.
  --             . Clk16xT runs 16x the bit clock rate
  --             . If ResetF = '0' then
  --                 RxReg_s is reset to "11111111111".
  --                 Count_s   is reset to 0.
  --             . If (RxMT_s and RxIn_s = '0') then
  --                 Start of new byte
  --             . If Count16_s = 7  and not RxMT_s then --   mid
clock
  --                 Sample here where bit most stable
  --                 RxReg_s <= RxIn_s & RxReg_s(9 downto 1);
  --             . Entire byte received when
  --                 not RxMT_s and RxReg_s(9) = '1' and RxReg_s(0) =
'0'
  --
 
-----------------------------------------------------------------------------
  Rx_Lbl : process

  begin  --  process Rx_Lbl
     wait until Clk16xT'event and Clk16xT = '1';
     --   Clock serial input into RxIn_s
     RxIn_s <= Serial_InT;

     --   reset
     if (ResetF = '0') then
       Count16_s <= 0;                   --   reset divide by 16
counter
       RxMT_s <= true;                    --   no message starting;
idle
       RxReg_s <= RxInit_c;

     --   new bit start
     elsif (RxMT_s and RxIn_s = '0') then
       Count16_s <= 0;                   --   reset divide by 16
counter
       RxMT_s <= false;                    --   new message starting
       RxReg_s <= RxInit_c;

     --   If in a receive transaction mode
     --   if @ mid bit clock then clock data into register
     elsif Count16_s = 7  and not RxMT_s then --   mid clock
       RxReg_s <= RxIn_s & RxReg_s(10 downto 1);
       Count16_s <= Count16_s + 1;

     --   if @ 16X clock rollover
     elsif Count16_s = 15 then
         Count16_s <= 0;

     --   Normal count16 counter increment
     else
       Count16_s <= Count16_s + 1;
     end if;

-------------------------------------------------------------Parity
Check Control
Statement---------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
     --   Check if a data word is received
     if not RxMT_s and RxReg_s(10) = '1' and RxReg_s(0) = '0' then
       Parity_reg = ((RxReg_s(1) xor RxReg_s(2)) xor (RxReg_s(3) xor
RxReg_s(4))) xor ((RxReg_s(5) xor RxReg_s(6)) xor (RxReg_s(7) xor
RxReg_s(8)))

     if Parity_reg /= RxReg_s(9) then
                    Parity_err <= '1';
           else
                    Parity_err <= '0';
           end if;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
       DataRdyT <= true;
       RxMT_s <= true;
     else
       DataRdyT <= false;
     end if;
  end process Rx_Lbl;

-------------------------------------------------------------------------------
--  Concurrent signal assignment for BitClkT and DataOut
-------------------------------------------------------------------------------

  BitClkT <=      '1' when Count16_s = 10
             else '0';

  DataOuT <= RxReg_s(8 downto 1);

end UartRx_Beh;


Article: 119472
Subject: Filtering the FPGA reset signal
From: Eli Bendersky <eliben@gmail.com>
Date: 21 May 2007 01:46:23 -0700
Links: << >>  << T >>  << A >>
Hello,

On my board, the FPGA receives its reset_n signal from a voltage
supervisor IC (such as MAX635x or LM370x).

Is there a point to further filter (digitally) this signal upon entry
into the FPGA ? Does this improve or reduce the resiliency of the
design to errors / glitches / noises ?

In favor of filtering: glitches on the line between the voltage
supervisor and the FPGA will be filtered.

Against filtering: (1) enforces synchronous reset, while I might want
it to be asynchronous. (2) ignores a valid reset signal from the
voltage supervisor when the supplies "go nuts" for the filtering time,
which may lead to undesired results.

What are your thoughts ?

Thanks in advance


Article: 119473
Subject: Timing not met but working on board
From: "J.Ram" <jrgodara@gmail.com>
Date: 21 May 2007 01:52:54 -0700
Links: << >>  << T >>  << A >>
Hi all,
I developed a design in which i need a master clock of 90Mhz, so
during synthesis max. freq obtained is 56Mhz and  timing is met for
global clock of 50Mhz, but timing are not met for 90Mhz.
but design is working on board for 90Mhz clcock.
In design all lower level module are working above 100 Mhz, but in top
module after integarting sub blocks it works around 56 Mhz in
synthesis and working at 90Mhz on board.
so please tell me what is wrong with this design.
Regards
J.Ram


Article: 119474
Subject: Re: Single Chip MSX computer full schematic and VHDL sources
From: Antti <Antti.Lukats@googlemail.com>
Date: 21 May 2007 01:59:22 -0700
Links: << >>  << T >>  << A >>
On 20 Mai, 22:14, spartan3wiz <magnus.wedm...@gmail.com> wrote:
> On 20 Maj, 20:29, spartan3wiz <magnus.wedm...@gmail.com> wrote:
>
>
>
>
>
> > On May 18, 6:47 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
> > > Hi
>
> > >http://code.google.com/p/fpga-retro/downloads/list
>
> > > there is the distribution archive for the one chip MSX project
> > > would be fun to convert it for some xilinx board, :)
>
> > > I have been hunting for those VHDL code for ages, all links ended
> > > dead somewhere, but with heavy searching the archive was found too.
>
> > > Antti
>
> > Thanks f=F6r sharing Antti!! Have you begun converting it to the XIlinx
> > platform? How much work is it?
> > I just love trying out/collecting new platforms for my Starter-Kit.
> > After a look in the archive its originally for the Altera FPGA's but
> > the standard T80
> > Is this the same product as the One Chip MSX at:http://www.bazix.nl/one=
chipmsx.html
> > If so that means that the product builds on open-source, is this OK
> > with the creators of f.e. T80-core? If I were to build/construct a
> > similar old-style platform but would be using these basic building
> > blocks that are downloadable, would this be OK? Can anyone explain the
> > license issues with this type of hardware-constructs?
>
> After doing a quick fix-up (ugly code changes made), it builds to only
> 54% of my Spartan3-200K. Nice!
> What I've done so far is to change some syntax for array 'range and
> 'high that seem to be non-standard but seem to work OK. I've also
> commented out the altera-specific RAM-instanciations and PLL-usages.
> These would of course only need to be mapped against BlockRAM and
> DCM's, is that correct? I need to continue working on a VHDL
> laboration but it would be nice to see the computer starting up.
> Please post/CVS changes somewhere if somebody else is better than me
> on porting from Quartus to ISE. Good luck!- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -

hum, what synthesis tool you use?
ISE 9.1 with speed goal give me (for s3-4000)

   Number of MULT18X18s                     21 out of 96     21%
   Number of RAMB16s                        24 out of 96     25%
   Number of Slices                       8193 out of 27648  29%
   Number of SLICEMs                    512 out of 13824   3%

8193 slices is not 54% of XC3S200 ??

Antti




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