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Messages from 119525

Article: 119525
Subject: Re: DDR Controller Blue
From: Zara <me_zara@dea.spamcon.org>
Date: Tue, 22 May 2007 09:43:55 +0200
Links: << >>  << T >>  << A >>
On 21 May 2007 20:49:02 -0700, Digital Mike <michaelmkliu@gmail.com>
wrote:

>Dear all,
>
>I am working on a DDR controller that stores captured video frames
>from which a VGA controller retrieves data. It (DDR controller) works
>fine for the first few frames but seems dead afterward. I wonder if
>anyone experienced similar problem. What I did (for initial testing
>purpose) is to capture and store a frame into the DDR then retrieve
>the same frame (a 640x480 pixels area) over and over again.
>

I don't really know how DDR manages refreshing, have you taken care of
it?

Zara

Article: 119526
Subject: Re: DDR Controller Blue
From: francescopoderico@googlemail.com
Date: 22 May 2007 02:00:30 -0700
Links: << >>  << T >>  << A >>
On 22 May, 03:49, Digital Mike <michaelmk...@gmail.com> wrote:
> Dear all,
>
> I am working on a DDR controller that stores captured video frames
> from which a VGA controller retrieves data. It (DDR controller) works
> fine for the first few frames but seems dead afterward. I wonder if
> anyone experienced similar problem. What I did (for initial testing
> purpose) is to capture and store a frame into the DDR then retrieve
> the same frame (a 640x480 pixels area) over and over again.
>
> Comments?
>
> -M

Hi Mike,
I've got some experience with DDR2 controller.
If you send me your code I can have a look.

Francesco


Article: 119527
Subject: using FPGA JTAG as GPIO
From: mh <moazzamhussain@gmail.com>
Date: 22 May 2007 02:15:03 -0700
Links: << >>  << T >>  << A >>
Hi
I want to debug a custom board with no interface for data exchange.
The requirement is PC based autometic test pattern generation and real
time data exchange from FPGA based hardware.

I chanced to see an article in Xcell Journal of  2nd quarter 2005,
titled: "Using the JTAG Interface as a General-Purpose Communication
Port"--- but couldn't find any thing from the link given in the
article.

How can I get GNAT tool as described in that article.

Or

Any other suggestion to use JTAG of Xilinx FPGA as general purpose I/
O.


regards
MH


Article: 119528
Subject: Re: How to insert tab in Write() function in VHDL
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 22 May 2007 10:18:22 +0100
Links: << >>  << T >>  << A >>
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message 
news:gvu253htpodsk3cs4vj186nqqrimoe9ni7@4ax.com...
> On 19 May 2007 18:58:35 -0700, Weng Tianxiang wrote:
>
>>What I do is to print out all related waveforms I am interested in and
>>using tab is to make me easier to manually check if the waveforms are
>>right so that a software can be used later to check the waveforms
>>without 1 clock after another to manually check waveforms.
>
> Ah - you are using tabs to create a tab-separated file for
> Excel or some similar software?  If so, then I'm sorry - yes -
> that's OK.
>
...but I'd recommend CSV as a better solution for that application.
HTH, Syms. 



Article: 119529
Subject: Re: using FPGA JTAG as GPIO
From: Antti <Antti.Lukats@googlemail.com>
Date: 22 May 2007 02:48:58 -0700
Links: << >>  << T >>  << A >>
On 22 Mai, 11:15, mh <moazzamhuss...@gmail.com> wrote:
> Hi
> I want to debug a custom board with no interface for data exchange.
> The requirement is PC based autometic test pattern generation and real
> time data exchange from FPGA based hardware.
>
> I chanced to see an article in Xcell Journal of  2nd quarter 2005,
> titled: "Using the JTAG Interface as a General-Purpose Communication
> Port"--- but couldn't find any thing from the link given in the
> article.
>
> How can I get GNAT tool as described in that article.
>
> Or
>
> Any other suggestion to use JTAG of Xilinx FPGA as general purpose I/
> O.
>
> regards
> MH

just connect your logic to BSCAN and implement anything you need.

BSCAN "redirects" USERx JTAG instructions for custom implementation in
the FPGA fabric.
just look in IP cores that use this, like the OPB_MDM, etc..

Antti





Article: 119530
Subject: Re: DDR Controller Blue
From: Digital Mike <michaelmkliu@gmail.com>
Date: 22 May 2007 04:55:46 -0700
Links: << >>  << T >>  << A >>
On 5=A4=EB22=A4=E9, =A4U=A4=C83=AE=C943=A4=C0, Zara <me_z...@dea.spamcon.or=
g> wrote:
> On 21 May 2007 20:49:02 -0700, Digital Mike <michaelmk...@gmail.com>
> wrote:
>
> >Dear all,
>
> >I am working on a DDR controller that stores captured video frames
> >from which a VGA controller retrieves data. It (DDR controller) works
> >fine for the first few frames but seems dead afterward. I wonder if
> >anyone experienced similar problem. What I did (for initial testing
> >purpose) is to capture and store a frame into the DDR then retrieve
> >the same frame (a 640x480 pixels area) over and over again.
>
> I don't really know how DDR manages refreshing, have you taken care of
> it?
>
> Zara

Zara,

Yes the controller is configured to auto-refresh DDR at the required
intervals.

-M


Article: 119531
Subject: Re: DDR 2 Memory controller own implementattion
From: sudhakarmvs@gmail.com
Date: 22 May 2007 05:11:40 -0700
Links: << >>  << T >>  << A >>
On May 17, 12:19 pm, sudhakar...@gmail.com wrote:
> Hi to all  ............
>
> Now i am in to developing  DDR2 memory contoller with STRATIX II EP2S
> 180 .
> Is there mega core which can support burst length 8 ?I found only
> burst lenth 4 controllers. So i have written and no problem with code.
> I am using DDIO bidirectional mega function  for data path to send and
> receive data on both edges . But problem is  so many set up and Hold
> time violations with this mega function .
> Has any body developed own memory controller for BURST LENTH 8 .
> please help me regarding this ..........
>
> thanks and regrads
> sudhakar

Hi thanks for your kind response .
I sorted out that problem some how .


Thanks and Regards
sudhakar


Article: 119532
Subject: Re: Xilinx doesn't detect setup/hold violations on synchronous reset
From: John Adair <g1@enterpoint.co.uk>
Date: 22 May 2007 05:26:26 -0700
Links: << >>  << T >>  << A >>
On 22 May, 02:40, Frai <maybetooparan...@gmail.com> wrote:
> Hi John.
>
> I knew that. That's one of the reasons why I'm using synchronous
> reset. As far as I know Xilinx is enabled by default to trace
> synchronous inputs, including set/reset.

Is your reset source synchronous? If not it won't go into anything
other than setup and hold analysis even if it is used synchronously.

John Adair
Enterpoint Ltd.


Article: 119533
Subject: Re: DDR Controller Blue
From: sudhakarmvs@gmail.com
Date: 22 May 2007 05:41:00 -0700
Links: << >>  << T >>  << A >>
On May 22, 2:00 pm, francescopoder...@googlemail.com wrote:
> On 22 May, 03:49, Digital Mike <michaelmk...@gmail.com> wrote:
>
> > Dear all,
>
> > I am working on a DDR controller that stores captured video frames
> > from which a VGA controller retrieves data. It (DDR controller) works
> > fine for the first few frames but seems dead afterward. I wonder if
> > anyone experienced similar problem. What I did (for initial testing
> > purpose) is to capture and store a frame into the DDR then retrieve
> > the same frame (a 640x480 pixels area) over and over again.
>
> > Comments?
>
> > -M
>
> Hi Mike,
> I've got some experience with DDR2 controller.
> If you send me your code I can have a look.
>
> Francesco

Hi
Francesco
I am currently working on DDR2 controller for BL 8.
My own code is giving good results when i  verified with memory model
from MICRON.
Now my problem is memory on the board  is not sending 4 DQS   clock
pulses. it seems to be sending for burst lenth 4.

For ur IDEA  some results  i observed

If i  won't   Initialize properly  it is not responding at all . no
DQS nothing is comming .
if i initialize it properly its giving DQS signal of two sine clock
pulses.
If i write with 101010101 .... of each location i am getting two sine
clock pulses on DQ pin while reading .
if i write with all ZERO's i am getting ZERO' on DQ pin.

so i think inialization is happenig properly. some problem persistence
still some where .
If u have any IDEA please help me regarding  this.
with regards......
sudhakar


Article: 119534
Subject: PLB behaviors strangely during burst transactions
From: luciorech <luciorech@gmail.com>
Date: 22 May 2007 06:02:41 -0700
Links: << >>  << T >>  << A >>
Hi,

I'm using PLB to read and write 64bit data through burst transactions.
I can read and write data correctly, but watching the signals through
chipscope I can see a strange behavior: the PLB_MWrDAck and
PLB_MRdDAck don't occur in consecutive clock cycles. For instance,
during a 16 words burst read, instead of taking 16 clock cycles to
read all data after the bus has been granted to my peripheral, it
takes about 190 clock cycles. Did anyone have the same problem??

Thanks,

Lucio Rech


Article: 119535
Subject: Re: SelectIO banking rules
From: John_H <newsgroup@johnhandwork.com>
Date: Tue, 22 May 2007 13:05:16 GMT
Links: << >>  << T >>  << A >>
What a pretty list....

What device is this for?
I suggested going to the data sheet to see what inputs can be powered by 
alternate VCCIOs.  I can't go to the data sheet for you without knowing 
which device - at least which family - you're using.


LilacSkin wrote:
> That's my BANK 4:
> I don't find the problem !
> 
> Pin Name        	Direction  	IO Standard
> IO_L49N_4       	BIDIR      	LVTTL
> IO_L67N_4       	BIDIR      	LVTTL
> IO_L07N_4       	OUTPUT   LVTTL
> IO_L19N_4       	OUTPUT   LVTTL
> IO_L37N_4       	INPUT      	LVTTL
> IO_L43N_4       	BIDIR      	LVTTL
> IO_L46N_4       	BIDIR      	LVTTL
> IO_L49P_4       	BIDIR      	LVTTL
> IO_L67P_4       	BIDIR      	LVTTL
> IO_L05_4/No_Pair	INPUT      	LVTTL
> IO_L07P_4/VREF_4	OUTPUT   LVTTL
> IO_L19P_4       	OUTPUT   LVTTL
> IO_L37P_4       	OUTPUT   LVTTL
> IO_L43P_4       	BIDIR      	LVTTL
> IO_L46P_4       	BIDIR      	LVTTL
> IO_L55N_4       	BIDIR      	LVTTL
> IO_L73N_4       	BIDIR      	LVTTL
> IO_L08N_4       	OUTPUT   LVTTL
> IO_L25N_4       	OUTPUT   LVTTL
> IO_L38N_4       	INPUT      	LVTTL
> IO_L47N_4       	BIDIR      	LVTTL
> IO_L55P_4       	TRISTATE LVTTL
> IO_L73P_4       	BIDIR      	LVTTL
> IO_L08P_4       	OUTPUT   LVTTL
> IO_L25P_4       	INPUT      	LVTTL
> IO_L26N_4       	OUTPUT   LVTTL
> IO_L38P_4       	INPUT      	LVTTL
> IO_L47P_4       	BIDIR      	LVTTL
> IO_L56N_4       	BIDIR      	LVTTL
> IO_L68N_4       	BIDIR      	LVTTL
> IO_L74N_4/GCLK3S	INPUT      	LVCMOS25
> IO_L20N_4       	OUTPUT   LVTTL
> IO_L39N_4       	INPUT      	LVTTL
> IO_L26P_4       	INPUT      	LVTTL
> IO_L44N_4       	BIDIR      	LVTTL
> IO_L50_4/No_Pair	BIDIR      	LVTTL
> IO_L56P_4       	BIDIR      	LVTTL
> IO_L68P_4       	BIDIR      	LVTTL
> IO_L74P_4/GCLK2P	INPUT      	LVCMOS25
> IO_L09N_4       	OUTPUT   LVTTL
> IO_L20P_4       	OUTPUT   LVTTL
> IO_L27N_4       	OUTPUT   LVTTL
> IO_L39P_4       	OUTPUT   LVTTL
> IO_L44P_4       	BIDIR      	LVTTL
> IO_L53_4/No_Pair	BIDIR      	LVTTL
> IO_L69N_4       	BIDIR      	LVTTL
> IO_L75N_4/GCLK1S	BIDIR      	LVTTL
> IO_L06N_4/VRP_4 	OUTPUT   LVTTL
> IO_L09P_4/VREF_4	OUTPUT   LVTTL
> IO_L21N_4       	OUTPUT   LVTTL
> IO_L27P_4/VREF_4	INPUT      	LVTTL
> IO_L45N_4       	BIDIR      	LVTTL
> IO_L48P_4       	BIDIR      	LVTTL
> IO_L48N_4       	BIDIR      	LVTTL
> IO_L57N_4       	BIDIR      	LVTTL
> IO_L57P_4/VREF_4	BIDIR      	LVTTL
> IO_L69P_4/VREF_4	BIDIR      	LVTTL
> IO_L75P_4/GCLK0P	INPUT      	LVTTL
> IO_L06P_4/VRN_4 	OUTPUT   LVTTL
> IO_L21P_4       	OUTPUT   LVTTL
> IO_L45P_4/VREF_4	BIDIR      	LVTTL
> IO_L54P_4       	BIDIR      	LVTTL
> IO_L54N_4       	BIDIR      	LVTTL

Article: 119536
Subject: Re: SelectIO banking rules
From: Jim Wu <jimwu88NOOOSPAM@yahoo.com>
Date: 22 May 2007 06:16:58 -0700
Links: << >>  << T >>  << A >>
On May 21, 10:49 am, LilacSkin <lpaul...@iseb.fr> wrote:
> Hi,
>
> Can I drive a LCVMOS25 (input) and a LVTTL (input/output) in the same
> bank even if there is VCCIO problems ?
>
> Thanks!

It depends which device you are using. For some device, this is
allowed. For some devices, you can't do this. This is usually well
documented in the device user guide.

ADEPT (http://home.comcast.net/~jimwu88/tools/adept/) can do some DRC
on your pinout.

Cheers,
Jim


Article: 119537
Subject: Re: VHDL newbie: building sequential circuits with basic gates
From: Andy <jonesandy@comcast.net>
Date: 22 May 2007 06:17:01 -0700
Links: << >>  << T >>  << A >>
On May 21, 1:50 pm, Jim Lewis <j...@synthworks.com> wrote:
> Andy,
>
>
>
> > Here's how I do it with natural types:
>
> > signal count : natural range 0 to 2**numbits - 1;
>
> > ...
>
> > if count - 1 < 0 then
> >   do_end_of_count_stuff_here;
> > else
> >   count <= count - 1;
> > end if;
>
> > The important thing to remember is integer expressions are independent
> > on the "width" of the operands, and are always 32 bit signed. The
> > reduction (and bounds checking) is done only upon assignment to a
> > constrained subtype of integer. Thus even though count cannot be less
> > than zero, count - 1, as an integer expression can be. DO NOT TRY THIS
> > WITH UNSIGNED!
>
> > This also works for 2**n-1 bit rollovers in up counters.
>
> > The synthesis tools recognize the common expression and share the
> > adder between them, adding an extra bit for the sign only in the
> > comparison, not in storage. More specifically, the synthesis tools
> > discard all the extra bits from the 32 bit expression except for the
> > result and the sign.
>
> > Andy
>
> Which tools have you verified that the synthesis tools give
> you a good implementation?
>
> Cheers,
> Jim

Symplify, XST, and even the old Synopsys FC2 would handle it
appropriately. I'm pretty sure Precision and Quartus handle it as
well.

Oh yeah, I meant to say it works with n-bit rollovers (if count + 1 >
2**n-1 then...) for up counters... Mike knew what I meant!

Andy


Article: 119538
Subject: Re: Xilinx doesn't detect setup/hold violations on synchronous reset
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 22 May 2007 14:20:52 +0100
Links: << >>  << T >>  << A >>
"Frai" <maybetooparanoid@gmail.com> wrote in message 
news:1179791977.569426.311460@a26g2000pre.googlegroups.com...
>
> Is my approach wrong? Why does Xilinx ISE not detect setup/hold
> violations?
>
> Thanks in advance.
>
Where are you expecting it to fail? Between the DCM and the FF? You can use 
the timing analyser tool to see what paths the tool is checking.
As to your approach, probably will work fine, but you might consider using 
LOCKED to asynchronously reset the FD you instantiated, and then 
synchronously release reset. However, I think the CLK0 from the DCM is still 
going throughout the DCM locking phase so your circuit should be fine too.
HTH, Syms. 



Article: 119539
Subject: Re: FPGA -> SATA?
From: Sata Know How <kuehn@interelectronix.com>
Date: Tue, 22 May 2007 15:37:47 +0200
Links: << >>  << T >>  << A >>
On 2006-08-25 20:41:38 +0200, "Martin E." <x@y.com> said:

> I am looking for a way to read/write to a SATA drive from an FPGA.  
> I've looked around.  Nothing seems to fit the bill.  Any ideas worth 
> considering?
> 
> Thanks,
> 
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Martin
> 
> To send private email:
>     email = x@y.com
> where:
>      x  =  "martineu"
>      y  =  "pacbell.net"

Hi Martin,

if you need some help please let me know. We are SATAIO member and very 
specialized in SATA.

I hope we can help.
-- 
Christian Kuehn

www.interelectronix.com

Professional SATA Solutions


Article: 119540
Subject: PLB behaviours strangely during burst transactions
From: luciorech <luciorech@gmail.com>
Date: 22 May 2007 07:03:26 -0700
Links: << >>  << T >>  << A >>
Hi,

I'm using PLB to read and write 64bit data through burst transactions.
I can read and write data correctly, but watching the signals through
chipscope I can see a strange behavior: the PLB_MWrDAck and
PLB_MRdDAck don't occur in consecutive clock cycles. For instance,
during a 16 words burst read, instead of taking 16 clock cycles to
read all data after the bus has been granted to my peripheral, it
takes about 190 clock cycles. Did anyone have the same problem??

Thanks,

Lucio Rech


Article: 119541
Subject: Problem with DDR2 controller
From: sudhakarmvs@gmail.com
Date: 22 May 2007 07:29:20 -0700
Links: << >>  << T >>  << A >>
Hi to all

I am currently working on DDR2 controller for Burst Lenth  8.
My own code is giving good results when i  verified with memory model
from MICRON.
Now my problem is memory on the board  is not sending 4 DQS   clock
pulses. it seems to be sending for burst lenth 4.

some results  i observed ........on C.R.O


If i  won't   Initialize properly  it is not responding at all . no
DQS nothing is comming .
if i initialize it properly its giving DQS signal of two sine clock
pulses.
If i write with 101010101 .... of each location i am getting two sine
clock pulses on DQ pin while reading .
if i write with all ZERO's i am getting ZERO' on DQ pin.


so i think inialization is happenig properly. some problem
persistence
still some where .
If any body has idea have any IDEA please help me regarding  this.
with regards......
sudhakar


Article: 119542
Subject: Re: Does FPGA need CPU for processing a packet/frame
From: NewToFPGA <hetzme@yahoo.com>
Date: 22 May 2007 09:21:13 -0700
Links: << >>  << T >>  << A >>
Does Operating System need to provide an FPGA a device driver?

If no application needs the additional services from an FPGA, all we
do is initialize and start an FPGA... right? Anything else that need
to be done?


Article: 119543
Subject: Re: PLB behaviours strangely during burst transactions
From: Alan Nishioka <alan@nishioka.com>
Date: 22 May 2007 09:28:43 -0700
Links: << >>  << T >>  << A >>
On May 22, 7:03 am, luciorech <lucior...@gmail.com> wrote:
> I'm using PLB to read and write 64bit data through burst transactions.
> I can read and write data correctly, but watching the signals through
> chipscope I can see a strange behavior: the PLB_MWrDAck and
> PLB_MRdDAck don't occur in consecutive clock cycles. For instance,
> during a 16 words burst read, instead of taking 16 clock cycles to
> read all data after the bus has been granted to my peripheral, it
> takes about 190 clock cycles. Did anyone have the same problem??

PLB burst can indeed read/write in consecutive clock cycles.
Perhaps your peripheral can't supply data fast enough?
Assuming Xilinx ppc, the cache only reads/write 4 cycles (8 words) at
a time.

Alan Nishioka


Article: 119544
Subject: Re: Xilinx doesn't detect setup/hold violations on synchronous reset
From: Frai <maybetooparanoid@gmail.com>
Date: 22 May 2007 10:04:21 -0700
Links: << >>  << T >>  << A >>
I'm using a clock with 10 ns period. The delay of the path between
"locked_a_reg" and the synchronous reset of some FFs happens to be
very close to 10 ns. Therefore, the clock signal from the DCM
"dsp_clk_a" arrives at the FF almost at the same time as the reset
signal is released, throwing a SETUP violation in Modelsim. In the
real world, the FFs would just recover from this, but Modelsim doesn't
seem to handle this, and it stays with many unknown values at FFs that
prevent me from simulating my design.

I've done quite much research on this topic with no success. I would
appreciate any information about why Xilinx doesn't detect such a
violation.

Regards.


Article: 119545
Subject: Problems to simulate (behavioural) in XPS
From: ferorcue <le_marq@hotmail.com>
Date: 22 May 2007 10:04:37 -0700
Links: << >>  << T >>  << A >>
Hi friends,


I am working with Solaris and with all the systems that i generate
with XPS have the same problem.

I have a Problem with LIBGEN. If I execute
XPS->Software->generate libreries and BSPs,  gmake ist not compiling
the libraries and the directory ./ppc405/include possesses only the
file xparameters.h and the directory ./ppc405/lib is empty
***************************************************************************
XPS INFO:
Configuring make for target include using:
gmake -s include "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-
ar"
"COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g"

gmake: Command not found.
gmake: Command not found.
gmake: Command not found.
gmake: Command not found.`
gmake: Command not found.
gmake: Command not found.
Configuring make for target libs using:
gmake -s libs "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-ar"
"COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g"
gmake: Command not found.
gmake: Command not found.
gmake: Command not found.
gmake: Command not found.
gmake: Command not found.
gmake: Command not found.
Libraries generated in
/home/ferorcue/my_work/project/xps/xps_lin_v1_e/ppc405_0/lib/
directory
Running execs_generate for OS'es, Drivers and Libraries ...
LibGen Done.
powerpc-eabi-gcc -O2 TestApp_Memory/src/TestApp_Memory.c  -o
TestApp_Memory/executable.elf \
	    -Wl,-T -Wl,TestApp_Memory/src/TestApp_Memory_LinkScr.ld  -g    -
I./ppc405_0/include/  -L./ppc405_0/lib/  \

TestApp_Memory/src/TestApp_Memory.c:39:19:
 xutil.h: No such file or directory
make: *** [TestApp_Memory/executable.elf] Error 1

***************************************************************************

To solve this problem I use windows with the same system and I execute
XPS->Software->generate libreries and BSPs. The files of  /lib and /
include are created



***************************************************************************
XPS INFO:

Configuring make for target include using:
make -s include "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-ar"
"COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g"
Configuring make for target libs using:
make -s libs "COMPILER=powerpc-eabi-gcc" "ARCHIVER=powerpc-eabi-ar"
"COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g"
Compiling common
powerpc-eabi-ar: creating ../../../lib/libxil.a
Compiling bsp
Compiling plb_arbiter
Compiling opbarb
Compiling uartlite
Compiling cpu_ppc405
Libraries generated in
\\storage\ferorcue\my_work\project\xps\xps_lin_v1_e\ppc405_0\lib\
directory
Running execs_generate for OS'es, Drivers and Libraries ...
LibGen Done.
Created mapping for /xygdrive -> /cygdrive
Done!

***************************************************************************

After that I can execute >Generate libraries and HDL files
And >launch HDL simulator

In modelsim I  compile the design by running the EDK compile script,
Later I change the modelsim.ini to use the smartmodels.
And I click s to simulate

s => load the design for simulation. (ModelSim 'vsim'
# *** command with 'system') After loading the design,
# *** set up signal displays (optional) and run the simulation.
# *** (ModelSim 'run' command)


This is the error that I get :

***************************************************************************
XPS INFO:


s
# vsim -t ps system_conf
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vsim-3865) Due to PLI being present, full design access is
being specified.
# Loading /opt/modeltech/6.2a/linux/libswiftpli.sl
# Loading /opt/modeltech/6.2a/linux/../std.standard
# Loading /opt/modeltech/6.2a/linux/../ieee.std_logic_1164(body)
# Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/
unisim/.vcomponents
# Loading /opt/modeltech/6.2a/linux/../std.textio(body)
# Loading /opt/modeltech/6.2a/linux/../ieee.vital_timing(body)
# Loading /opt/modeltech/6.2a/linux/../ieee.vital_primitives(body)
# Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/
unisim/.vpkg(body)
# Loading work.system_conf#1
# Loading work.system(structure)#1
# Loading work.ppc405_0_wrapper(structure)#1
# Loading ppc405_virtex4_v1_01_a.ppc405_virtex4(structure)#1
# Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/
unisim/.ppc405_adv(ppc405_adv_v)
# Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/
unisim/.ppc405_adv_swift_bus(ppc405_adv_swift_bus_v)
# Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/
unisim/.ppc405_adv_swift(smartmodel)
# Loading /opt/modeltech/6.2a/linux/libsm.sl
# ** Note (SmartModel):
#    Copyright (c) 1984-2007 Synopsys Inc. ALL RIGHTS RESERVED
# ** Note (SmartModel):
#    Platform Type: x86_linux (32-bit).
# ** Note (SmartModel):
#    You can use the Browser tool to configure the SmartModel
#    Library and access information about SmartModels:
#       $LMC_HOME/bin/sl_browser
#
#    SmartModel product documentation is available here:
#       $LMC_HOME/doc/smartmodel/manuals/intro.pdf
#       http://www.synopsys.com/products/lm/doc/smartmodel.html
#
# Notice: timing checks disabled with +notimingcheck at compile-time
# Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/
unisim/.fpga_startup_virtex4(fpga_startup_virtex4_v)
# Loading work.jtagppc_0_wrapper(structure)
# Loading jtagppc_cntlr_v2_00_a.jtagppc_cntlr(structure)
# Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/
unisim/.jtagppc(jtagppc_v)
# Loading work.reset_block_wrapper(structure)#1
# Loading /opt/modeltech/6.2a/linux/../ieee.std_logic_arith(body)
# Loading proc_sys_reset_v1_00_a.proc_sys_reset(imp)#1
# Loading proc_sys_reset_v1_00_a.upcnt_n(imp)#1
# Loading proc_sys_reset_v1_00_a.lpf(imp)#1
# Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/
unisim/.srl16(srl16_v)
# Loading proc_sys_reset_v1_00_a.sequence(imp)#1
# Loading proc_sys_reset_v1_00_a.upcnt_n(imp)#2
# Loading work.plb_wrapper(structure)#1
# Loading plb_v34_v1_02_a.plb_v34(simulation)#1
# Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/
unisim/.fds(fds_v)#1
# Loading plb_v34_v1_02_a.plb_addrpath(implementation)#1
# Loading proc_common_v1_00_b.mux_onehot(imp)#1
# Loading proc_common_v1_00_b.mux_onehot(imp)#2
# Loading proc_common_v1_00_b.mux_onehot(imp)#3
# Loading proc_common_v1_00_b.mux_onehot(imp)#4
# Loading proc_common_v1_00_b.mux_onehot(imp)#5
# Loading proc_common_v1_00_b.mux_onehot(imp)#6
# Loading plb_v34_v1_02_a.plb_wr_datapath(simulation)#1
# Loading proc_common_v1_00_b.mux_onehot(imp)#7
# Loading plb_v34_v1_02_a.plb_rd_datapath(simulation)#1
# Loading plb_v34_v1_02_a.plb_slave_ors(implementation)#1
# Loading /opt/modeltech/6.2a/linux/../ieee.std_logic_unsigned(body)
# Loading proc_common_v1_00_b.or_gate(imp)#1
# Loading proc_common_v1_00_b.or_gate(imp)#2
# Loading proc_common_v1_00_b.or_gate(imp)#3
# Loading proc_common_v1_00_b.or_gate(imp)#4
# Loading proc_common_v1_00_b.proc_common_pkg(body)
# Loading /opt/modeltech/6.2a/linux/../synopsys.attributes
# Loading /opt/modeltech/6.2a/linux/../ieee.std_logic_misc(body)
# Loading plb_v34_v1_02_a.plb_arbiter_logic(implementation)#1
# Loading plb_v34_v1_02_a.plb_priority_encoder(simulation)#1
# Loading plb_v34_v1_02_a.priority_encoder(simulation)
# Loading plb_v34_v1_02_a.qual_request(simulation)
# Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/
unisim/.muxcy(muxcy_v)
# Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/
unisim/.lut4(lut4_v)
# Loading plb_v34_v1_02_a.pending_priority(simulation)#1
# Loading plb_v34_v1_02_a.qual_priority(qual_priority)
# Loading plb_v34_v1_02_a.pend_request(simulation)#1
# Loading plb_v34_v1_02_a.arb_addr_sel(simulation)#1
# Loading plb_v34_v1_02_a.arb_control_sm(simulation)#1
# Loading plb_v34_v1_02_a.gen_qual_req(simulation)#1
# Loading plb_v34_v1_02_a.muxed_signals(implementation)#1
# Loading proc_common_v1_00_b.or_bits(implementation)
# Loading plb_v34_v1_02_a.arb_registers(simulation)#1
# Loading plb_v34_v1_02_a.bus_control(simulation)
# Loading plb_v34_v1_02_a.watchdog_timer(simulation)#1
# Loading proc_common_v1_00_b.down_counter(simulation)#1
# Loading plb_v34_v1_02_a.plb_interrupt(plb_interrupt)#1
# Loading /home/ferorcue/simlib/EDK8.2_mti_se_linux/ISE_Lib/
unisim/.fdre(fdre_v)#1
# Loading plb_v34_v1_02_a.bus_lock_sm(implementation)
# Loading work.opb_wrapper(structure)#1
# Loading /opt/modeltech/6.2a/linux/../ieee.std_logic_signed(body)
# Loading proc_utils_v1_00_a.conv_funs_pkg(body)
# Loading opb_arbiter_v1_02_e.opb_arb_pkg(body)
# Loading opb_v20_v1_10_c.opb_v20(imp)#1
# Loading opb_arbiter_v1_02_e.or_gate(imp)#1
# ** Fatal: (vsim-3348) Port size (1) does not match actual size (32)
for port '/system/opb/opb/opb_abus_i/y'.
#    Time: 0 ps  Iteration: 0  Instance: /system/opb/opb/opb_abus_i
File: /opt/xilinx/EDK8.2/hw/XilinxProcessorIPLib/pcores/
opb_arbiter_v1_02_e/hdl/vhdl/or_gate.vhd Line: 125
# FATAL ERROR while loading design
# Error loading design




Do you know why "gmake" is not working?

Windows uses "make" and it compiles the libraries, but later It should
work. Why I have a problem with a ip core from Xilinx
(opb_arbiter_v1_02_e).

Do you think, that if I get the "gmake" working in Solaris it will
compile the libraries in a different way and the simulation will work?

Thank you for your consideration


Article: 119546
Subject: Re: How to include pcores librarys from XilinxProcessorIPLib (EDK)
From: "L. Schreiber" <l.s.rockfan@web.de>
Date: Tue, 22 May 2007 19:07:41 +0200
Links: << >>  << T >>  << A >>
Brian Drummond schrieb:
> On Tue, 15 May 2007 19:00:05 +0200, "L. Schreiber" <l.s.rockfan@web.de>
> wrote:
> 
>> First of all. Thanks for the bus macro advise.
>>
>>
>> The second problem still remains. After creating a system with base 
>> system builder wizard from EDK's XPS and generating its netlist(s), I 
>> wanted to join the vhdl-files from the hdl-directory to a new ISE 
>> project. Unfortunatelly ISE doesn't know anything about the imported 
>> library modules that the "system" modules refere to. These library 
>> modules can be found inside a subdirectory of the EDK installation 
>> directory (.../edk/hw/XilinxProcessorIPLib/pcores).
>>
>> How can ISE be made known, where it should look up those "mysterious" 
>> ;-) unknown vhdl-modules?
>>
>> Can I set something like a PATH variable for such librarys?
> 
> "Macro Search Path" under "Translate Properties".
> (Right click on "Implement Design" and select "Properties" then the
> "Translate" tab, or right click on "Translate" and select Properties.)
> 
> - Brian
> 

Hello,

okay, this doesn't seem to work for the repos modules inside the 
EDK/hw/XilinxProcessorIPLib/pcores. The error occoures before implement 
design state (translate) in synthesize stage (syntax checking).

XST tells me ERROR: HDLParsers:3317 - file_name.vhd Line xx. Library 
lib_name cannot be found. For example library proc_sys_reset_v1_00_a.

I think answer record #14027 says, I should add every missing library 
(from EDK-directory) manually into my ISE project. I 've already tried 
this. It has worked quite good until I tried to add a source file from 
another library, which had the same name as one module included before.

I got stuck again.

Any advice?

Article: 119547
Subject: "black_box"-ing of components in toplevel
From: "L. Schreiber" <l.s.rockfan@web.de>
Date: Tue, 22 May 2007 19:14:25 +0200
Links: << >>  << T >>  << A >>
Hi again,

What does the setting of the attribute box_type to "black_box" for my 
toplevel components effect (concerning modular design flow)?

Syntax checking in ISE projnav searchs for the components' modules 
anyway, whether black boxed or not.

greetings

Article: 119548
Subject: System-synchronous interface clocking between FPGA's
From: "bwilson79@gmail.com" <bwilson79@gmail.com>
Date: 22 May 2007 10:25:09 -0700
Links: << >>  << T >>  << A >>
This may seem like an elementary question/application, but I'll bring
it up nonetheless in hopes of getting a thorough understanding...

In our design, there are 80MHz system-synchronous interfaces between
two FPGA's.  There is a common clock source on the board with matched
trace lengths to each of the FPGA's.  The clocks then go into DCM's
and the DCM 1x output clock is used to clock the IOB registers and
also used as internal feedback to the DCM.  Can we [almost] guarantee
that the clocks coming out of the DCM's on the separate FPGA's are
near phase-aligned, assuming matched trace lengths coming in?  These
are V4-LX160 parts.  I was looking over the V4 user guide and couldn't
find a fitting clocking application example.  It seems it can never be
fully guaranteed, since the DCM's deskew compensation on each of the
FPGA's will certainly differ, not to mention small process
variations.  Since we have a 12.5ns period, I think we should have
room in our timing budget to absorb these small phase differences.  I
will ensure that all the inputs and outputs utilize the IOB registers.

If anyone could reassure me that this design is relatively common and
safe, and provide me with some information regarding the DCM output
clock relationships on the separate devices, I will feel much better.
I've definitely worked with these types of designs in the past, but
never fully understood why things just work.


Article: 119549
Subject: ISE Service pack
From: sudarshan.onkar@gmail.com
Date: 22 May 2007 10:25:18 -0700
Links: << >>  << T >>  << A >>
For some reason i am not able to download ISE service pack for 9.1i
version.
Can any body upload it ?




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