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Messages from 119100

Article: 119100
Subject: Re: JTAG_SIM_VIRTEX5
From: Duth <premduth@gmail.com>
Date: 11 May 2007 11:43:53 -0700
Links: << >>  << T >>  << A >>
Looks like I made a typo. It should say:

 component JTAG_SIM_VIRTEX5
     generic(
         PART_NAME : string
         );

     port(
         TDO       : out std_ulogic;

         TCK       : in  std_ulogic;
         TDI       : in  std_ulogic;
         TMS       : in  std_ulogic
       );
  end component;

before the begin in the testbench. Sorry about that.

 - Duth

On May 11, 10:51 am, Duth <premd...@gmail.com> wrote:
> Hi Self,
>
> This is a known issue in the unisim_vcomp file thatXilinxis going to
> fix soon. Due to the fact that this is only forsimulation, this
> component was left out. If you put the following component declaration
> in the testbench, you can avoid this error:
>
>         JTAG_SIM_VIRTEX5_inst : JTAG_SIM_VIRTEX5
>         generic map (PART_NAME => "LX30") -- Specify target V5 device.
> Possible values are: "LX30", "LX50", "LX85", "LX110", "LX220",
> "LX330"
>         port map (
>                 TDO => TDO,         -- JTAG data output (1-bit)
>                 TCK => TCK,         -- Clock input (1-bit)
>                 TDI => TDI,         -- JTAG data input (1-bit)
>                 TMS => TMS          -- JTAG command input (1-bit)
>                 );
>
> Hope this helps
> Duth
>
> On May 10, 3:00 pm, self <pete.dud...@comcast.net> wrote:
>
> > Guys
>
> > I am trying to simulate the BSCAN_VIRTEX5 component. TheXilinx
> >simulationguide, sim.pdf, says that you can instantiate a
> > JTAG_SIM_VIRTEX5 in your testbench to control the BSCAN component.
>
> > So far I have been unable to get either theISEsimulatoror the Aldecsimulatorto resolve the JTAG_SIM_VIRTEX5 component. I get this
> > message in theISEsimulator: "Undefined symbol 'JTAG_SIM_VIRTEX5".
>
> > Can anyone tell me what library I need to include in my testbench to
> > resolve the JTAG_SIM_VIRTEX5 component?
>
> > For reference I include my testbench VHDL.
>
> > Thanks
>
> >    Pete
>
> > ---------------------------------------------------------------------------
>
> > LIBRARY ieee;
> > USE ieee.std_logic_1164.ALL;
> > USE ieee.std_logic_arith.all;
> > library UNISIM;
> > use UNISIM.VComponents.all;
> > use UNISIM.VPKG.all;
>
> > ENTITY jtag_interface_tb_vhd IS
> > END jtag_interface_tb_vhd;
>
> > ARCHITECTURE behavior OF jtag_interface_tb_vhd IS
>
> >         signal tdo, tck, tdi, tms : std_logic;
>
> >         COMPONENT jtag_interface PORT(
> >                         data_in : IN std_logic_vector(31 downto 0);
> >                         clk_out : OUT std_logic;
> >                         addr_out : OUT std_logic_vector(31 downto 0);
> >                         data_out : OUT std_logic_vector(31 downto 0);
> >                         we : OUT std_logic);
> >         END COMPONENT;
>
> >         SIGNAL data_in :  std_logic_vector(31 downto 0) := (others=>'0');
> >         SIGNAL clk_out :  std_logic;
> >         SIGNAL addr_out :  std_logic_vector(31 downto 0);
> >         SIGNAL data_out :  std_logic_vector(31 downto 0);
> >         SIGNAL we :  std_logic;
>
> >         constant tck_period : time := 1us;
>
> > BEGIN
>
> >         JTAG_SIM_VIRTEX5_inst : JTAG_SIM_VIRTEX5
> >         generic map (PART_NAME => "LX30") -- Specify target V5 device.
> > Possible values are: "LX30", "LX50", "LX85", "LX110", "LX220",
> > "LX330"
> >         port map (
> >                 TDO => TDO,         -- JTAG data output (1-bit)
> >                 TCK => TCK,         -- Clock input (1-bit)
> >                 TDI => TDI,         -- JTAG data input (1-bit)
> >                 TMS => TMS          -- JTAG command input (1-bit)
> >                 );
>
> >         -- Instantiate the Unit Under Test (UUT)
> >         uut: jtag_interface PORT MAP(
> >                 clk_out => clk_out,
> >                 addr_out => addr_out,
> >                 data_out => data_out,
> >                 data_in => data_in,
> >                 we => we);
>
> >         tck_proc:process
> >         begin
> >                 tck <= '0';
> >                 wait for tck_period/2;
> >                 tck <= '1';
> >                 wait for tck_period/2;
> >         end process;
>
> >         stim_proc: process
> >         begin
> >                 -- force into reset state.
> >                 tms <= '1';
> >                 tdi <= '0';
> >                 wait for tck_period*10;
> >                 wait;
> >         end process;
>
> > END



Article: 119101
Subject: Re: Xilinx software quality - how low can it go ?!
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Fri, 11 May 2007 18:50:15 +0000 (UTC)
Links: << >>  << T >>  << A >>
Bob <bob3635x@yahoo.com> wrote:
...
> I think a better choice would be to open source iMPACT.  I doubt if
> it contains any strategic IP.  There are six computers in the office
> suite where I work, including Win-XP, Linux, and FreeBSD on x86_64;
> and Win-XP and Linux on x86_32.  ISE runs fine on all of them. iMPACT
> runs on precisely one (Win-XP on x86_32).  It fails on all the others
> for various reasons.  It also fails to work on VMware.  These sorts
> of driver and OS compatibility issues are something the OSS community
> is quite good at fixing.

Look with google for 
"XILINX USB/Parallel JTAG cables on Linux without windrvr"
for an open source replacement for the windriver nightmare.

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 119102
Subject: how to choose the perfect fpga support
From: kha_vhdl <abaidik@gmail.com>
Date: 11 May 2007 13:09:52 -0700
Links: << >>  << T >>  << A >>
hi every body,
i want to implement a vhdl program into an fpga support ( the program
is compressing video ),
i want know what are the basics that i should know to choose the
perfect fpga( for example Sparta,3 or Virtex 4 into Xlinx) and thank
you for your answer


Article: 119103
Subject: =?windows-1252?Q?Re=3A_power_consumption_of_integrated_?=
From: austin <austin@xilinx.com>
Date: Fri, 11 May 2007 13:29:28 -0700
Links: << >>  << T >>  << A >>
C * F * V^2 = P

There is no "1/2", as you get power when you charge, and also when you
discharge a node.

E=1/2 CFV^2 is appropriate for energy stored in a capacitor, not for the
power dissipated when nodes are switching (Charging AND Dis-charging).

Austin

Article: 119104
Subject: =?windows-1252?Q?Re=3A_power_consumption_of_integrated_?=
From: Del Cecchi <cecchinospam@us.ibm.com>
Date: Fri, 11 May 2007 15:43:18 -0500
Links: << >>  << T >>  << A >>
austin wrote:
> C * F * V^2 = P
> 
> There is no "1/2", as you get power when you charge, and also when you
> discharge a node.
> 
> E=1/2 CFV^2 is appropriate for energy stored in a capacitor, not for the
> power dissipated when nodes are switching (Charging AND Dis-charging).
> 
> Austin

true for clocks but data lines usually only transition one direction per 
  cycle at most.  so conventionally SF=2 for clocks in power calculators.

-- 
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions, 
strategies or opinions.”

Article: 119105
Subject: Re: power consumption of integrated circuit in 0.13µm CMOS technology
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Fri, 11 May 2007 13:52:11 -0700
Links: << >>  << T >>  << A >>
On Fri, 11 May 2007 14:30:20 +0200, "Geronimo Stempovski"
<geronimo.stempovski@arcor.de> wrote:

>Hi all,
>
>currently I am investigating a data sorting algorithm on hardware. The 
>algorithm was implemented in VHDL and is currently running on a Xilinx 
>Virtex-II Pro XC2VP70 - FF1704 FPGA. Power consumption is a crucial aspect 
>in the target application. Therefore I made an analysis with the Xilinx 
>Virtex-II Pro Web Power Tool (www.xilinx.com) and obtained satisfying 
>results.
>
>Now I'd like to make an estimation what this circuit would consume on a 
>comparable ASIC 0.13µm CMOS technology (the FPGA is also based on a 0.13µm 
>CMOS technology). The target clock frequency is 180 MHz, activity ratio is 
>15%. Is there any rule of thumb or calculation rule?
>
>Any help is highly appreciated !!!!
>
>Regards    Gero 
>

There are several design houses that specialize in flipping fpga
designs to asics. I bet one of them would give you a quick estimate.
Google "fpga asic conversion service" or something like that.

John


Article: 119106
Subject: =?iso-8859-1?q?Re:_power_consumption_of_integrated_circuit_in_0=2E13=B5m_CMOS_technology?=
From: Peter Alfke <peter@xilinx.com>
Date: 11 May 2007 13:53:13 -0700
Links: << >>  << T >>  << A >>
If you want to retain the 1/2, then I suggest you use T (for
transition) instead of F (for frequency), in order to avoid the
ambiguity.
A factor of 2 might actually mean something  :-)
Peter Alfke

On May 11, 1:43 pm, Del Cecchi <cecchinos...@us.ibm.com> wrote:
> austin wrote:
> > C * F * V^2 = P
>
> > There is no "1/2", as you get power when you charge, and also when you
> > discharge a node.
>
> > E=1/2 CFV^2 is appropriate for energy stored in a capacitor, not for the
> > power dissipated when nodes are switching (Charging AND Dis-charging).
>
> > Austin
>
> true for clocks but data lines usually only transition one direction per
>   cycle at most.  so conventionally SF=2 for clocks in power calculators.
>
> --
> Del Cecchi
> "This post is my own and doesn't necessarily represent IBM's positions,
> strategies or opinions."



Article: 119107
Subject: Re: how to choose the perfect fpga support
From: Peter Alfke <peter@xilinx.com>
Date: 11 May 2007 14:02:23 -0700
Links: << >>  << T >>  << A >>
On May 11, 1:09 pm, kha_vhdl <abai...@gmail.com> wrote:
> hi every body,
> i want to implement a vhdl program into an fpga support ( the program
> is compressing video ),
> i want know what are the basics that i should know to choose the
> perfect fpga( for example Sparta,3 or Virtex 4 into Xlinx) and thank
> you for your answer

Will you ever learn to ask a meaningful question, supported by
meaningful parameters?
Don't you have a teacher that can explain the basics?
Six weeks ago you asked a similar dumb question, and I answered then:

It is very frustrating to try to answer such an -excuse the harsh
word-
stupid request.
I have all the sympathy in the world for mangled english syntax,
grammar, spelling, and poor choice of words. (English is my second
language, too).
But I have no sympathy for questions that are inherently meaningless
and impossible to answer in any language on this planet.
If you are smart enough to operate a computer, you should also be
smart enough to put meaningful information into a request. Do us a
favor: Think before you type !
This newsgroup is not a baby-sitting operation.
Peter Alfke


Article: 119108
Subject: =?ISO-8859-1?Q?Re=3A_power_consumption_of_integrated_c?=
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Sat, 12 May 2007 09:54:54 +1200
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> If you want to retain the 1/2, then I suggest you use T (for
> transition) instead of F (for frequency), in order to avoid the
> ambiguity.
> A factor of 2 might actually mean something  :-)
> Peter Alfke

Correct, but the 'C' portion of this is usually modelled,
not physical, and called "power dissipation capacitance"
so as long as the formula is stated, the 1/2 does not matter.

eg Philips skip the 1/2, and give the formula.
Their Cpd also varies slightly with Vcc, so we have
2.0pF @1.8V and 2.7pF @3.3V for 74AUP1G175.


Article: 119109
Subject: Re: how to choose the perfect fpga support
From: fpga_toys@yahoo.com
Date: 11 May 2007 15:31:56 -0700
Links: << >>  << T >>  << A >>
On May 11, 2:09 pm, kha_vhdl <abai...@gmail.com> wrote:
> i want know what are the basics that i should know to choose the
> perfect fpga( for example Sparta,3 or Virtex 4 into Xlinx) and thank
> you for your answer

Well, obviously you thought you were a potential Xilinx customer, by
asking the question specifically in terms of Xilinx product line.
>From Xilinx's sharp abusive reprimand, you should now understand the
basics about being a Xilinx customer -- if you are not a $100B company
with a $100M engineering budget willing to purchase $1B of Xilinx
product a year, you really don't count enough that Xilinx will be
socially respectful and polite.

Xilinx management and I have had this discussion before about CAF
abuses, and, well ... they seem unable to fix their personel issues.

I'd suggest taking a look at the Xilinx APNotes and then take a much
more careful look at your design requirements, the excellent Altera
product line, and see if you can get a respectful reply to your
questions in terms of which Altera product would be more suitable for
your project.

Why would anyone WANT do business with such an abusive company like
Xilinx?

John


Article: 119110
Subject: Re: how to choose the perfect fpga support
From: "MM" <mbmsv@yahoo.com>
Date: Fri, 11 May 2007 18:54:24 -0400
Links: << >>  << T >>  << A >>
This is ridiculous! Peter was as polite as one could only be with this sort 
of questions! I guess in today's overly politically correct world he could 
simply say nothing so that not to provoke comments like this, but it 
wouldn't change the fact that the OP's question was absolutely meaningless! 
Xilinx has problems but Peter is not one of them, he is in fact one of the 
greatest assets Xilinx has!

/Mikhail


<fpga_toys@yahoo.com> wrote in message 
news:1178922716.701468.78740@n59g2000hsh.googlegroups.com...
> On May 11, 2:09 pm, kha_vhdl <abai...@gmail.com> wrote:
>> i want know what are the basics that i should know to choose the
>> perfect fpga( for example Sparta,3 or Virtex 4 into Xlinx) and thank
>> you for your answer
>
> Well, obviously you thought you were a potential Xilinx customer, by
> asking the question specifically in terms of Xilinx product line.
>>From Xilinx's sharp abusive reprimand, you should now understand the
> basics about being a Xilinx customer -- if you are not a $100B company
> with a $100M engineering budget willing to purchase $1B of Xilinx
> product a year, you really don't count enough that Xilinx will be
> socially respectful and polite.
>
> Xilinx management and I have had this discussion before about CAF
> abuses, and, well ... they seem unable to fix their personel issues.
>
> I'd suggest taking a look at the Xilinx APNotes and then take a much
> more careful look at your design requirements, the excellent Altera
> product line, and see if you can get a respectful reply to your
> questions in terms of which Altera product would be more suitable for
> your project.
>
> Why would anyone WANT do business with such an abusive company like
> Xilinx?
>
> John
> 



Article: 119111
Subject: Re: how to choose the perfect fpga support
From: Peter Alfke <peter@xilinx.com>
Date: 11 May 2007 15:56:35 -0700
Links: << >>  << T >>  << A >>
My nasty response had nothing to do with Xilinx policy, or to our
attitude to customers large or small. People that know me appreciate
that I love to help with either tutorial or also very specific
explanations.
But it irks me when a few students abuse this newsgroup by typing ill-
defined questions that obviously cannot be answered directly. And it
irks me double when the same student does it again.
This is a high-powered newsgroup where experienced engineers try to
give helpful answers. This forum should not be abused by really dumb
questions.
Even a student must know that parameters like frequency, data width,
standard etc are crucial, and should be included in the question.
Don't be shy, but be specific !
That was the reason for my outburst...
Peter Alfke

On May 11, 3:31 pm, fpga_t...@yahoo.com wrote:
> On May 11, 2:09 pm, kha_vhdl <abai...@gmail.com> wrote:
>
> > i want know what are the basics that i should know to choose the
> > perfect fpga( for example Sparta,3 or Virtex 4 into Xlinx) and thank
> > you for your answer
>
> Well, obviously you thought you were a potential Xilinx customer, by
> asking the question specifically in terms of Xilinx product line.>From Xilinx's sharp abusive reprimand, you should now understand the
>
> basics about being a Xilinx customer -- if you are not a $100B company
> with a $100M engineering budget willing to purchase $1B of Xilinx
> product a year, you really don't count enough that Xilinx will be
> socially respectful and polite.
>
> Xilinx management and I have had this discussion before about CAF
> abuses, and, well ... they seem unable to fix their personel issues.
>
> I'd suggest taking a look at the Xilinx APNotes and then take a much
> more careful look at your design requirements, the excellent Altera
> product line, and see if you can get a respectful reply to your
> questions in terms of which Altera product would be more suitable for
> your project.
>
> Why would anyone WANT do business with such an abusive company like
> Xilinx?
>
> John



Article: 119112
Subject: Re: how to choose the perfect fpga support
From: Eric Smith <eric@brouhaha.com>
Date: 11 May 2007 16:54:01 -0700
Links: << >>  << T >>  << A >>
kha_vhdl <abaidik@gmail.com> writes:
> i want know what are the basics that i should know to choose the
> perfect fpga( for example Sparta,3 or Virtex 4 into Xlinx) and thank
> you for your answer

Add the family number, pin count, the number of CLBs, three times the
number of multipliers, half the number of block RAMs, and the last
four digits of the telephone number of the local vendor sales office,
then divide by 42 for a figure of merit.  Pick the FPGA with the
highest figure of merit, unless there is a full moon, in which case
you should use the third-highest (or wait a few days).

Eric

Article: 119113
Subject: Re: how to choose the perfect fpga support
From: austin <austin@xilinx.com>
Date: Fri, 11 May 2007 17:36:58 -0700
Links: << >>  << T >>  << A >>
Mikhail,

Relax.  A certain person has a vendetta against myself, Peter, and Xilinx.

We are unsure why.

It is best I not say anything more.

However, once he joins a thread, it is automatically placed on "ignore" 
as no further useful dialog can be held.



Peter and I remain willing and able to answer all questions, and we try 
to be as helpful as possible.

Our challenge is to understand why the technology is hard to understand 
(for some), and discover how to ease its adoption for people who have 
never studied programmable logic.

Please post he question in a form that details what the requirements 
are, and we ill be happy to respond.  As for this thread, any further 
Xilinx contribution is no longer possible.

Austin

Article: 119114
Subject: Re: how to choose the perfect fpga support
From: fpga_toys@yahoo.com
Date: 11 May 2007 22:26:40 -0700
Links: << >>  << T >>  << A >>
On May 11, 6:36 pm, austin <aus...@xilinx.com> wrote:
> Relax.  A certain person has a vendetta against myself, Peter, and Xilinx.
>
> We are unsure why.

But Austin, no vendetta at all. I've been really clear ... be nasty to
other posters, and you set the tone for the replys. If Peter wants to
be nasty as he intends to on purpose, then so can others ... accept
it, you have certainly repeatedly asked for it.

Be nice ... others will too ... especially me.

Have fun! :)

John


Article: 119115
Subject: Re: how to choose the perfect fpga support
From: fpga_toys@yahoo.com
Date: 11 May 2007 22:40:11 -0700
Links: << >>  << T >>  << A >>
On May 11, 4:56 pm, Peter Alfke <p...@xilinx.com> wrote:
> My nasty response had nothing to do with Xilinx policy, or to our
> attitude to customers large or small. People that know me appreciate

Your nasty reponse was not necessary, correct, or even justified.

If you can not take it in return, then stop trashing powerless newbie
students just because you can.

John



Article: 119116
Subject: Re: how to choose the perfect fpga support
From: kha_vhdl <abaidik@gmail.com>
Date: 11 May 2007 22:40:18 -0700
Links: << >>  << T >>  << A >>
On 12 mai, 07:26, fpga_t...@yahoo.com wrote:
> On May 11, 6:36 pm, austin <aus...@xilinx.com> wrote:
>
> > Relax.  A certain person has a vendetta against myself, Peter, and Xilinx.
>
> > We are unsure why.
>
> But Austin, no vendetta at all. I've been really clear ... be nasty to
> other posters, and you set the tone for the replys. If Peter wants to
> be nasty as he intends to on purpose, then so can others ... accept
> it, you have certainly repeatedly asked for it.
>
> Be nice ... others will too ... especially me.
>
> Have fun! :)
>
> John

hi i m sorry , but you should know that i m beginner , i m not
professional so it is normal that for now i m asking stupid questions


Article: 119117
Subject: Re: how to choose the perfect fpga support
From: fpga_toys@yahoo.com
Date: 11 May 2007 22:50:05 -0700
Links: << >>  << T >>  << A >>
On May 11, 11:40 pm, kha_vhdl <abai...@gmail.com> wrote:
> hi i m sorry , but you should know that i m beginner , i m not
> professional so it is normal that for now i m asking stupid questions

Peter was correct that you should do your homework a little more
before asking very general questions. See a tutor, or spend some more
time on researching the problem resources and definitions.

His insults however, do not belong on this list. he doesn't own it.
control it, or set policy for it.

The differences between the various Altera and Xilinx FPGA families is
the resources they provide. To answer your questions, you first need
to do a basic design and count the resources critical for your design.
With that, you can assign some figures of merit to the various product
families, and with a decision table get a solution for your projects
design constraints. You will have to do that for your design and
project, as each of us will have different designs should we be faced
with implementing your problem.

Altera and Xilinx Application Notes and data sheets have many useful
descriptions and examples,  about similar design objectives.

Have fun ...
John


Article: 119118
Subject: Re: how to choose the perfect fpga support
From: fpga_toys@yahoo.com
Date: 11 May 2007 23:51:22 -0700
Links: << >>  << T >>  << A >>
On May 11, 4:54 pm, "MM" <m...@yahoo.com> wrote:
> This is ridiculous! Peter was as polite as one could only be with this sort
> of questions! I guess in today's overly politically correct world he could
> simply say nothing so that not to provoke comments like this, but it
> wouldn't change the fact that the OP's question was absolutely meaningless!
> Xilinx has problems but Peter is not one of them, he is in fact one of the
> greatest assets Xilinx has!
>
Hi Mikhail,

There are lots of ways to direct a newbie's poor choice of questions
without publicly insulting and humiliating them. Frankly, as a key
Xilinx asset on this list, Xilinx cann't help but drive business to
Altera with Peter's insults ... or drive readership from this list.
How many posters will AVOID this list at all costs rather than catch
Peter in a foul abusive mood?

If this is Xilinx's idea of great customer relations, then we should
make the most of it, and have a lot of fun with it too.

I was told last fall, that it was Xilinx policy that their staff
remain respectful and helpful, and they would make sure "it can not
happen again". Then Peter twice, rips into the OP, being in his own
words "nasty" just because it irked him. Peter's response is not in
any way remorse, just a flat statement that it's somehow his right
because the OP rubbed him the wrong way ... and obviously you too ...
but that doesn't give anybody the right to behave that way. Even my
response in kind it not acceptable, but if you and others want to play
that way, then I'll have some fun with it too ... till everyone is
tired of the BS disrespect, and starts being nice.

I have for a couple years warned Austin and Peter that they need to be
nice, or they will set the tone of the replies they get.  This
certainly applies to Xilinx, when the postings are repeatedly from
company resources which they have both the right and obligation to
make sure are free of intimidation, harrassment, and abusive postings.

I don't like it ... and I can not see a better way to frame Peter's
bullying than to present it clearly as it is ... VERY POOR XILINX
CUSTOMER RELATIONS.


Article: 119119
Subject: Re: how to choose the perfect fpga support
From: Frank Buss <fb@frank-buss.de>
Date: Sat, 12 May 2007 09:45:52 +0200
Links: << >>  << T >>  << A >>
fpga_toys@yahoo.com wrote:

> There are lots of ways to direct a newbie's poor choice of questions
> without publicly insulting and humiliating them. 

kha_vhdl asked this question multiple times before and asking for more
details, e.g. what video format, was answered by him that he don't know it.
This sounds a bit like a troll or a schoolboy, who wants to do a cool
project, which is ok, but without some more information about the project,
e.g. "I want to design a PCI card, which compresses video streams to the
H.263 format" the best answer is http://www.google.com/search?q=video+fpga
and Peter's answer is justifiable.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 119120
Subject: Re: how to choose the perfect fpga support
From: Robert Ganter <hb9dnn@gmx.net>
Date: Sat, 12 May 2007 11:43:55 +0200
Links: << >>  << T >>  << A >>
fpga_toys@yahoo.com wrote on 12.05.2007 08:51:

> There are lots of ways to direct a newbie's poor choice of questions
> without publicly insulting and humiliating them.

I've been reading this list for quite a while and fully understand
Peters outburst.
First of all I do not understand his presence here as an official part
of his job at Xilinx but as his personal decision to do so. The usual
way to answer Xilinx specific problems and questions is via their
webcase system. I really appreciate his (and others FPGA manufacturers
employees) presence here as many questions are discussed here (see e.g.
ISE, OSS discussion). Even if they would only read here most of the time
it is good to know they are here and Your question/problem/suggestion is
very probably noticed.
I recently had a question as well and it was answered politely here and
from a Xilinx FAE. Well, the problem could not be solved but I found out
this way that:
- it is better to simulate a design than to "verify" ("" means:
understand how my VHDL-"ish" code was interpreted...) generating an RTL
schematic
- schematic generation of ISE is extremely sensitive (and got worse from
8.2 to 9.1) to badly written VHDL code. Although it might be convenient
for a VHDL beginner like me, it often leads You in the wrong direction.
I asked here and at Xilinx, *after* days of searching for a answer
myself if the problem was at my code or at ISE.
Bottomline of this is that I learned a lot (*I* had to work it out) and
certainly will ask here again if I get stuck somewhere.

It seems to be en vogue for certain students, however, to ask others to
do their homework. Honestly, we all cheated somehow during our study
time to minimize workload. But I wouldn't have had the chuzpe to just
copy-paste the homework description into a posting and even expect a
polite answer. It is, at least, annoying if a new gmail account pops up
every other day asking the same stupid question which was answered
(politely) a few days ago.

> Frankly, as a key
> Xilinx asset on this list, Xilinx cann't help but drive business to
> Altera with Peter's insults ... or drive readership from this list.
> How many posters will AVOID this list at all costs rather than catch
> Peter in a foul abusive mood?

Also frankly, this is ridiculous. I never saw an insulting answer from
Peter (actually from noone here) to reasonably formulated questions for
a well defined problem. It is this "make solution" attitude which pisses
everybody off who tries to share his experience with others.

> If this is Xilinx's idea of great customer relations, then we should
> make the most of it, and have a lot of fun with it too.

I am certainly just a marginal customer for Xilinx (having designed in 5
(!) Virtex-4 FPGAs for a prototype board I developed for a customer) but
I never had the impression they would not want to make business with me.
Lead times are an annoying but this is not Xilinx specific. I even had
to redesign another board because a simple stupid ultra low RDSon MOSFET
had a lead time of 44 weeks when we wanted to start series production
(and we were talking about much more than five transistors there..).

Although I somehow doubt those specific individuals will read (let alone
understand) it, it might be helpful to regularly post a very short group
policy posting here. I remember times when these rules were considered
common sense but this was before WWW (1989).



Just my 0.02$

Robert




Article: 119121
Subject: Re: driving Spartan-3 input from 74LS TTL
From: Eric Smith <eric@brouhaha.com>
Date: 12 May 2007 02:54:25 -0700
Links: << >>  << T >>  << A >>
I asked about driving a 3.3V FPGA input (e.g., Spartan-3) from
a 74LS14 TTL output.

Peter Alfke wrote:
> Pick 300 to 1000 Ohm, any value will be ok. Consider the input a 10 pF
> load and put the resistor close to it.. Then 1kilohm means a 10 ns
> time constant...

I have found that I can get 74LVC244AD 3.3V octal buffers with 5V-tolerant
inputs and 6 ns max prop. delay for less than the cost of 330 ohm 16-pin
SMT resistor networks!

    part               Digikey quantity 100 price

    NXP 74LVC244AD		$0.26
    Bourns 4816P-T01-331LF      $0.71
    CTS 767-163-R330P           $0.37 (not stocked)

Amazing.  I guess those bleeding-edge fabs they use to make resistor
networks must be really expensive!  Maybe they could lower the cost
by outsourcing production to TSMC  :-)

Eric

Article: 119122
Subject: Re: how to choose the perfect fpga support
From: MNiegl <Michael.Niegl@cern.ch>
Date: 12 May 2007 02:55:30 -0700
Links: << >>  << T >>  << A >>
I just also want to say that I think John's objections are absolutely
ridiculous. First of all, the question of the thread starter is
utterly stupid and unanswerable. Second, Peter is certainly not
posting here as a representative of Xilinx, we should rather be
grateful (I know I am) that several chaps from Xilinx or other
companies are here to provide us with information and help we
otherwise would never be able to get. And there have been several
times when I got pissed off with some Xilinx stuff, but customer
support never was one of them. All of the FAEs I have interfered with
until now have always extremely helpful, friendly and went out of
there way to make sure my problem would get solved or at least an
alternative solution found.


And I know for sure that in the future I won't be too scared to post
here because I know how to actually phrase a question and I won't be
super-trivial and/or idiotic things.

Cheers,
Michael


Article: 119123
Subject: Power Consumption Estimation for PCI card, any advice?
From: "commone" <dechenxu@yahoo.com.cn>
Date: Sat, 12 May 2007 05:37:03 -0500
Links: << >>  << T >>  << A >>
Hi, everybody 
I am designing a PCI video capture card. The main ICs are: Cyclone II
(EP2C35F672c6), ADV7181, ADV7123, PCI9054, 128M SDRAM etc. Now I am making
a power consumption estimation for this board. I have finished the power
requirements estimation for ICs. And I have several questions: 
First, is the estimation I have made reasonable? (Pls see the table below)

FPGA  SDRAM ADV7181 ADV7123 PCI9054 MAX3221CDBE4 
840mW 782mW 547.1mW 97.54mW  920mW    3.6mW 
Others(resistors,leds...)   Total 
              ?            3190.24+? 
Secondly, I made some calculations for the pull-up and termination
resistors and LEDS. I find each resistor consumes several mWs, even less
than 1 mW and each LED consumes about 20 or 30 mWs when on. Is that
reasonable? 
Finally, I want to receive some good advices on the proportion of the
non-IC devices’ power consumption usually accounts for. And how much power
supply margin should I offer for the whole board? 
Looking forward your help. Thank u very much. 
Regrds 
Leon:| 



Article: 119124
Subject: PowerPC_DDR
From: Vangelis <>
Date: Sat, 12 May 2007 04:05:32 -0700
Links: << >>  << T >>  << A >>
I am trying to interface a PowerPC in a Virtex-II Pro device with an external DDR memory on the board. I am using the following fucntions to read an write to the memory:

//write num. 300 to position 0 in //the DDR XGpio_mSetDataReg(0, 1, 300); //read position 0 in the DDR = ReadFromGPInput(0);

I have enabled burst mode, but these two functions take significan time to write and read the DDR. Are there any other functions which I can use in order to speed up the process?



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