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Everyone knows: The smoke is what makes the part work. If you let the smoke out, the part doesn't work anymore. QED DO NOT let the smoke out. You can not put the smoke back in. AustinArticle: 119301
<michel.talon@gmail.com> wrote in message news:1179318713.590015.313450@k79g2000hse.googlegroups.com... > First, thank for all your answers, > in facts, I'm designing an emulator for an hardware microcontroler. So > I've to embed microcontroler sources ( originaly coded for hardware IC > design ) in my virtex FPGA. > One of the goal of the project is to preserve microcontroleur > functionality and mechanisms ( to obtain a real emulation ), this why > I can't use a clock to delay my signal. > This signal must be delayed by about 50ns. I know this is a large time > without use of clock, and that's all my problem.. Sounds like you are on a totally wrong path if you are trying to emulate datasheet timing this way... What is it so special about this signal that it can't be clocked out? /MikhailArticle: 119302
I am currently working on a NASA program focused on the development of Radiation-Hardened Electronics for Space Environments (RHESE). One portion of the sub-project I am working in support of is aimed at developing reconfigurable modular spare electronic parts for avionics systems. An ultimate goal of this sub-project is to reduce the total number of spare parts that must be flown on a mission by having spares that are reconfigurable such that, for example, they could function as a DSP or microprocessor or microcontroller at any given time (just one specific application at any given time). (And one obvious question here is -- exactly what specific functionality is desired from the microprocessor, microcontroller, or DSP that this part will implement? - that does not seem to be entirely clear yet on this project - when I pose those questions, I don't get answers. That's a bit frustrating (to me anyhow), but for now, that is just how it is!) I've been tasked with evaluation of potential development platforms for these modular spares. This is a bit "out of the box" for me -- my background is primarily in system software development -- I'm not a hardware designer -- but, this has been very interesting and I'm trying to learn and do my best at it. After spending some time trying to spin-up on reconfigurable hardware / systems through books (a colleague lent me a copy of The_Design_Warrior's_Guide_to_FPGAs_ by Clive "Max" Maxfield which has been a very good tutorial / reference - I recommend it!) papers, and google searches, my current thoughts are towards a "dual path" development plan: Path 1: Use a cutting edge platform in the genre of what Clive "Max" Maxfield refers to as a "Field Programmable Node Array (FPNA)" in the above mentioned book in an attempt to get the most flexible end product from the standpoint of reconfigurability, power consumption, board/device size, and a novel approach to provision of radiation tolerance. Current plan here is to use a platform and associated development toolset provided by a small start-up company -- so relatively high risk, but good potential benefits if it all comes together well. Path 2: Target a Xilinx FPGA-based platform of some type - from what looking through information / references on the Xilinx web site, I'm thinking of possibly using a combination of Xilinx's ISE and EDK development tools to develop a reconfigurable platform which uses: 1) MicroBlaze soft core to implement microprocessor functionality 2) PicoBlaze soft core to implement microcontroller functionality 3) ??? some soft core provided through the above development tools (or from some other source?) to implement DSP functionality My rationale for including "path 2" in the mix is since "path 1" will likely be based on technology provided by a small start-up (and doing research on such technologies / small firms has made it very clear how quickly they can come and go!), I'd like a fall-back path in case the vehicle for path 1 fades away. I mean no disrespect to start-ups, but relying on technology provided by such small firms is risky -- new ideas and technologies don't always "fly" for a multitude of reasons -- even if they're great ideas / technologies! I'm leaning towards the use of Xilinx FPGAs for "path 2" since the area where I'm working already has a platform which includes some Xilinx Virtex II 6000's that could support some initial prototyping work towards a Xilinx FPGA- based platform. Since this is a current asset of this group, it seems like a good place to start. Also, since "path 1" will require a lot more time and effort for in- house design / development to implement the desired functionalities, I am thinking that "path 2" may provide for a good initial demonstration of capabilities (in general, since at current there do not seem to be specifics with regard to the desired capabilities!), with the hopes that "path 1" can be pursued over a longer period of time with a greater degree of focus on the _specific_ capabilities and characteristics that are ultimately decided upon. So I have some questions / concerns, on which I hope some folks with more knowledge of this arena can help give me insight: * Am I going down reasonable paths to pursue the end goals here? I have a little wellspring of doubt about all my thoughts since hardware specs / design is not something in which I have experience (plus it's just kinda my nature to doubt and worry!!! ;) :) ). I'd appreciate any insight, positive or negative, on this point. * I was going to try to contact a Xilinx field engineer to ask about the viability of a Xilinx-FPGA based platform, and if that is viable, to get recommendations on appropriate platforms / development boards / development tools / IP cores to work towards the desired end-goal functionality; however, from looking through the Xilinx web site (which provides a lot of excellent reference information -- it's almost overwhelming to a newby in this arena like me!) I'm not sure that's the kind of support a Xilinx field engineer would normally provide. Does Xilinx provide this kind of pre-sales advice / support, or is there a better point of contact for this type of help (such as a field engineer from a distributor like Nu Horizons)? Where would I find good points of contact to ask questions and get advice on potential platforms / development tools, etc. to begin determining the best selections for a "path 2" platform? I wish I could provide more specifics on exactly what specific functionality is desired from the microprocessor, microcontroller, or DSP that this part will implement... As I said, that is currently a frustration of mine, and I know that makes it tough to provide insight on the best development path. I am hoping that as the process of specifying appropriate development platforms progresses, the performance and other characteristics of the platforms specified will help the folks here work towards more clarity on the specifics of what they need. I would very much appreciate any insights anyone could provide - particularly affirmation if my current thoughts on "paths" are reasonable, or thoughts on re-direction / pointers towards good references for changing my thought paths if my current thoughts are way off base! :^) Thank you for "listening" for this long, and thank you for any insight you can provide. Anne anne.l.atkinson@nasa.gov - or - anneatkinson@yahoo.comArticle: 119303
Anne, Email me directly to discuss the US Air Force program for a Soft error Immune Radiation-hardened FPGA (SIRF). I will email you back my phone number. AustinArticle: 119304
Regenerate the linker script and try again. ---Matthew Hicks > Hi, > > Is there any constraint regarding the number of Ethernet MAC that you > can place on the OPB Bus? I have attempting to put 2 MACs on the Bus, > but as soon as a instantiate the second MAC and attempt to generate > bitstream, I get the following error: address space overlap! This > error is generated by PlatGen > > I am certain address overlap that this is not the problem , because I > have gone through the entire address map of my system. No two > peripherals are assigned the same address space. > > When I had only a single MAC in the system , with address 40c0_0000 to > 40c0_ffff , things were working perfectly . But as soon as instantiate > the second MAC with address 42c0_0000 to 42c0_ffff, this problem > creeps up. > > The PLB2OPB Bridge is from 0x00000000 to 0x7FFFFFFF, so that entire > range can be used by peripherals on the OPB Bus. > > Thanks > VenuArticle: 119305
Anne wrote:
> An ultimate goal of this sub-project is to reduce the total number of
> spare parts that must be flown on a mission by having spares that are
> reconfigurable such that, for example, they could function as a DSP or
> microprocessor or microcontroller at any given time (just one specific
> application at any given time). (And one obvious question here is --
> exactly what specific functionality is desired from the
> microprocessor, microcontroller, or DSP that this part will implement?
> - that does not seem to be entirely clear yet on this project - when I
> pose those questions, I don't get answers. That's a bit frustrating
> (to me anyhow), but for now, that is just how it is!)
I would pick two or three historical or made-up applications
for the purpose of refining the idea. Sometimes the only
way to get input is with a quick jump from general to specific.
Also if my grand plan fails to accommodate the simplest of
examples, I know I am on the wrong path. Good luck.
-- Mike Treseler
Article: 119306Hi I would like to ask you guys about a cyclone II power-up problems. I read all datasheets from altera concerning all the steps to enter finally in USER mode with the FPGA properly configured. I have an EPCS1 memory loader, and i can program it without problems under Quartus 7. Thing that seems to happen is the memory is not able to program the FPGA, and the FPGA itself is not able to leave POR mode. When i watch the nstatus signal with an oscilloscope, i can see that the signal is trying to power up to VCC, with the pull up resistor i put to enter configuration mode, but once it's reach VCC, it's get to ground immediatly, wait remaining grounded, and try to power up again, and same thing happen again and again. What do you think the problem can be ? I checked my voltage, sometimes i have 3,1V for 3,3V, sometimes i have 1,1V for 1,2V core voltage. I rarely get 3,3V and 1,2V. This can be a problem ? Thank you for your time.Article: 119307
HI everybody, I am trying to configure a cyclone II with EPCS1 boot loader. the EPCS1 program perfectly with quartus and byteblaster II cable. But when at the nstatus pin on the FPGA, it's like it's try to go to VCC during 2 us, then once it's almost reach VCC, it's get down to ground immediatly, and repeat the phenomena again. the FPGA can't leave POR mode. Anybody have an Idea ? Thank you for your time.Article: 119308
This is another case of an incomplete or imprecise question: If (for whatever strange reason) a 20 ns delay is needed, the only realistic way to do that is to run the signal out of the chip and back into it, with a low-pass filter in-between, like 1 kilohm resistor and 20 pF capacitor to ground, or 510 Ohm and 47 pF. Why anybody wants to do this remains a mystery... Peter Alfke On May 16, 8:50 am, "MM" <m...@yahoo.com> wrote: > <michel.ta...@gmail.com> wrote in message > > news:1179318713.590015.313450@k79g2000hse.googlegroups.com... > > > First, thank for all your answers, > > in facts, I'm designing an emulator for an hardware microcontroler. So > > I've to embed microcontroler sources ( originaly coded for hardware IC > > design ) in my virtex FPGA. > > One of the goal of the project is to preserve microcontroleur > > functionality and mechanisms ( to obtain a real emulation ), this why > > I can't use a clock to delay my signal. > > This signal must be delayed by about 50ns. I know this is a large time > > without use of clock, and that's all my problem.. > > Sounds like you are on a totally wrong path if you are trying to emulate > datasheet timing this way... What is it so special about this signal that it > can't be clocked out? > > /MikhailArticle: 119309
Maybe this is a homework question, but I took it as a challenge. I can solve it with one 4-input LUT driving a flip-flop, clocked in the slow domain. The LUT inputs are: the incoming pulse, the slow clock, the LUT output, and the flip-flop output. What happens with metastability? If the rising edge of the incoming pulse coincides with the rising slow-clock edge (within a bulls-eye expressed in a fraction of a femtosecond), the flip-flop output might go metastable, i.e. undefined for a few ns, but statistically only for max 3 ns ever during the lifetime of the universe. The (hopefully synchronous) slow-clock domain should easily be able to live with that (and much more), but If you are paranoid, cascade a second flip-flop. Peter Alfke On May 16, 7:09 am, Paul <pauljbenn...@gmail.com> wrote: > General rule of thumb is that you want 2 registers to cross between > clock domains, follow that rule to deal with any metastability > issues. Now you just have the problem that your first clock domain is > faster and you might not catch it with the slower domain. > > Personally, my approach here would be to "hold" the signal in your > CLK_FAST with an enabled register until you receive some sort of feed > back that you've grabbed it in CLK_SLOW, bearing in mind that those > feedback / feedforward signals should all be double registered to > prevent metastability. Also keep in mind that an enabled register > does NOT count as one of your two "synchronization" registers, because > an enabled register is actually implemented as a register with a mux > in front of it - only direct D-to-Q connections with NO combinational > logic count for clock domain crossing issues. Now, depending upon the > timing of it all, this could end you up with more than 1 clock pulse > width. Assuming that you know your input pulses are spaced far enough > apart that you KNOW it's not ACTUALLY multiple pulses, then a simple > edge detect will fix this problem for ya. > > The ideal behind the metastability stuff is that if you clock a signal > exactly at the transisition the output of the flop has some > probability of floating somewhere between 0 and 1 for some amount of > time. Adding any combinatorial logic extends that amount of time. > The idea of having 2 registers is that you reduce your probability of > a metastable event because even if you hit that .01% chance of it > remaining metastable for long enough to create a problem at the first > register, you got another .01% on your side at the second register. > (Note: .01% is much higher than it really is.. but remember, if you're > clocking signals in the MHz range, those tiny probabilities add up > REAL quick!) > > On May 16, 1:35 am, himassk <hima...@gmail.com> wrote: > > > Hi, > > > Please suggest me how to transfer a single clockwide pulse from high > > frequency clock domain and create a single clockwide pulse in a slow > > clock domain? > > What are different methods available? > > > Thanks in advance. > > > Regards, > > Himassk.Article: 119310
Well, according to my measurements, same applies to the interrupt dispatching capabilities of both OPB & DCR. Eventually I hooked up my high-speed ADC & DAC to PLB instead though I'm kinda overloading my PLB with memory accesses as well (some off-chip SRAMs). It seems that your design should be centered around minimizing memory transactions in general. So eventually everything has to go through buffers and transactions should be bursty. Though it's kinda disappointing as it defeats the purpose of having a powerful 32-bit uP core and reduces it to supervisory tasks.Article: 119311
On May 16, 8:07 am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Tue, 15 May 2007 16:57:50 -0600, Kevin Neilson
>
> <kevin_neil...@removethiscomcast.net> wrote:
> >kousta...@gmail.com wrote:
> >> Hello,
>
> >> I am graduate student in the Dept. of Computer Sc. & Engg. in
> >> USF.
> >> We are using a Digilent XUP2vpPro board for one of our research
> >> projects. I am trying to interface a Kingston 512 MB DDR RAM in DIMM
> >> to Xilinx virtex 2 Pro FPGA.
>
> >You can see what parts are on the DIMM (e.g., Micron, Infineon) and then
> > figure out what the row size is from that. You can also get good HDL
> >simulation models from Micron. They are somewhat slow, but accurate.
> >You instantiate one DRAM model for each DRAM chip on the DIMM.
> >-Kevin
>
> Following up to second the recommendation on the Micron datasheets and
> models, though they seem to omit VHDL models for some newer devices.
> Hynix cover that base though.
>
> If you can't find the info you need from Kingston, why not go to
> Micron/Crucial for the DIMM itself? Micron fully specify them, and
> Crucial sell them online ... I have seen DIMMs with a Micron label on
> one side and a Crucial label on the other...
>
> - Brian
Hello Brian,
We are trying to figure ot whether we should go for a
EDK based ucontroller (PPC acting as a memory controller and
interfacing with the other ASIC on FPGA) or generate it with the MIG
based tool. But in any ways I would need simulation libraries/ RTL
models for the DIMM and the DRAMs. As you suggested micron/crucial
libraries would be useful. Can you provide some more information on
these? (links etc). I would appreciate some docs on the DIMM
architecture as well. I have e-mailed Kingston for some specification
docs which lists bank #, column/row address #, and rank organization.
I think I have to get into these details first as well.
Eagerly awaiting a reply.
Thanks,
Koustav
Article: 119312Well, I got nearly the same results for interrupt dispatching both over OPB & DCR. Eventually I hooked up my high-speed ADC & DAC drivers to PLB though I'm kinda already overloading my PLB (got some off-chip SRAM). It seems that every design should be centered around minimizing memory transactions which implies using buffers intensively and later communicate results in a bursty manner. Still I think---in some circumstances---this kinda defeats the purpose of having a powerful 32- bit uP core at your disposal and reduces it to mere supervisory tasks!Article: 119313
Hello Andreas,
I would be grateful if you could provide me with
your DDR controller and I can tailor it to my needs. I guess since you
have done it this way I would try to give it a shot by going your way.
Also any ideas about simulation libraries for DIMM and DRAMs ? How did
you simulate ur design using DDR controllers? I am using a Kingston
512 MB for the DIMM.
Thanks again for your reply,
Koustav
On May 16, 3:01 am, Andreas Ehliar <ehl...@lysator.liu.se> wrote:
> On 2007-05-15, kousta...@gmail.com <kousta...@gmail.com> wrote:
>
> > If any reference designs are avialable for the memory
> > controllers for DDR
> > RAMs for interfacing to Xilinx V2P, that would be greatly helpful as
> > well.
>
> I think you generally have two decent options here. The cheapest
> is to get hold of the EDK. (Since you are associated with a university
> you should be able to get it very cheap. Or you might already have it.)
> That is by far the easiest method to get the DDR ram interface up
> and running on that board.
>
> Otherwise you could take a look at the Memory interface generator
> at xilinx.com (aka MIG). This doesn't look to be nearly as easy to
> get up and running but might be an idea if you don't have the EDK or
> if you really cannot use the OPB or PLB bus protocol.
>
> Finally, you could roll your own, I wouldn't recommend it though since
> it will probably take you a lot of time to get right. There are some
> open source DDR controllers available which you might be able to modify,
> like the one at opencores. However, at least the opencores one hasn't
> worked very well for me unfortunately.
>
> Anyway, unless your purpose is to do research on the memory controller,
> my advice is to use the EDK's memory controller. You will be able to
> get the board up and running with an example running in about an hour
> if you have a tutorial to follow.
>
> /Andreas
Article: 119314Historically, anti-fuse technology was the major player in RHESE applications but can't offer in-field reconfigurability. It might be worthwhile to check out the very recent FLASH-based FPGAs from Actel. Though significantly sparser than their SRAM counterparts (no built-in special function ASIC blocks e.g. DSP MACs), if you'r willing to compromise on this by having a reconfigurable DSP loosely coupled with FLASH FPGA accelerator, you might be able to pull off a decent match to what you seek. Still this means that you guys have to develop the whole reconfigurable platform with its supporting tools; a non-trivial task I reckon.Article: 119315
Hi > The ordering in EDK caused me quite a headache too. Me too :) > I tend to use (N downto 0) for my own HDL. Me too > The following function is very handy though: > signal dataA : std_logic_vector(0 to 31); > signal dataB : std_logic_vector(31 to 0); > ... I use only B <= A. In the case of EDK: signal Bus2IP_ArData_i, Bus2IP_Addr_i, IP_Bus_ArData_i : std_logic_vector(31 downto 0); Bus2IP_ArData_i <= Bus2IP_ArData; Bus2IP_Addr_i <= Bus2IP_Addr; IP2Bus_ArData <= IP2Bus_ArData_i; I do this because Bit31 (for example. Bus2IP_Addr(31)) is the LEAST significant Bit in the vector. I map it to Bus2IP_Addr_i(0), which sounds more least significant to me. If I would map it to ...(31) by reversing the vector, my bitorder would be wrong. My Custom Peripheral works fine using those only "declaration-inverted" signals.Article: 119316
On May 9, 10:17 pm, AlbertCo <aco...@applica.com> wrote: > hello > > I need to design DVI over FIBER > my idea to do as follow > > DVI to data then to FPGA > the FPGA will use memory sunc SDRAM or DDRAM > will send info via phy > > and the same on RX side > > I need help with FPGA > please help > > i am on msn or skype avcohen or applicau2 > Albert > 818 2558700 Hi Albert 1. Which DVI display modes you need to support? 2. Is the application price sensitive? 3. Which FPGA are you planning to use (with Serdes?) MotiArticle: 119317
On 7 Mag, 23:59, Jim Granville <no.s...@designtools.maps.co.nz> wrote:
> interrogativo wrote:
> > I'm trying to code an 'enhanced' binary-to-7segments display decoder
> > with ATF750CL and WinCUPL.
>
> > I'm experiencing problems using the truth table CUPL construct , so I
> > wrote these test code lines:
>
> > Name ATF750CL;
> > Partno XXXX;
> > Date Apr 2007;
> > Revision 0.0 GEAT Floor Display Decoder;
> > Designer mf;
> > Company c companyname snc, 2007;
> > Assembly Custom;
> > Location Naples;
> > Device v750c;
>
> > /* Input pins */
> > PIN [1..11] = [in1, in2, in3, in4, in5, in6, in7, in8, in9, in10,
> > in11];
> > PIN 13 = in12;
>
> > /* Output pins */
> > PIN [14..23] = [o1, o2, o3, o4, o5, o6, o7, o8, o9, o10];
>
> > FIELD input = [in4, in3, in2, in1] ;
>
> > FIELD output = [o7, o8, o9, o10] ;
> > FIELD output2 = [o3, o4, o5, o6] ;
>
> > /* Basically the output is a copy of the input */
> > TABLE input => output {
> > 'b'0000 => 'b'0000;
> > 'b'0001 => 'b'0001;
> > 'b'0010 => 'b'0010;
> > 'b'0011 => 'b'0011;
> > 'b'0100 => 'b'0100;
> > 'b'0101 => 'b'0101;
> > 'b'0110 => 'b'0110;
> > 'b'0111 => 'b'0111;
> > 'b'1000 => 'b'1000;
> > 'b'1001 => 'b'1001;
> > 'b'1010 => 'b'1010;
> > 'b'1011 => 'b'1011;
> > 'b'1100 => 'b'1100;
> > 'b'1101 => 'b'1101;
> > 'b'1110 => 'b'1110;
> > 'b'1111 => 'b'1111;
> > }
>
> > /* And this also, but on different output pins */
> > output2 = input;
>
> > Well, 'output2' behaves correctly, while 'output' pins are always at 0
> > level.
>
> > Do you know why?!?!?!?!?!
>
> Yes.
> This is a result of CUPLs internal handling of numeric suffixes.
> In Cupl IF the VALUE of the suffix is NUMERIC, it matters in TABLE
> statements. That value is used for the COLUMN alignment
> ( In most languages, once a variable is named, usage does not care how
> it is composed. )
>
> So, you have two choices :
>
> Choice A:
> Remove the trailing numeric, for example, by using an underscore, or a
> letter.
> CUPL now uses the Field order, to assign the Table mapping
>
> FIELD input = [in4_..in1_] ;
> FIELD output = [o10_..o7_] ;
>
> Choice B:
> Keep the trailing numeric, but align the Table to column match.
> Note, CUPL starts Table indexes from Zero, and allows X padding, so
> the column aligned table, for 4..1 and 10..7 suffixes, looks like the
> one below.
>
> PIN = [in4..in1] ;
> FIELD input = [in4..in1] ;
> FIELD output = [o10..o7] ;
> FIELD output2 = [o6..o3] ;
>
> TABLE input => output {
> /* 43210 A9876543210 */
> 'b'0000x => 'b'0000xxxxxxx;
> 'b'0001x => 'b'0001xxxxxxx;
> 'b'0010x => 'b'0010xxxxxxx;
> 'b'0011x => 'b'0011xxxxxxx;
> 'b'0100x => 'b'0100xxxxxxx;
> 'b'0101x => 'b'0101xxxxxxx;
> 'b'0110x => 'b'0110xxxxxxx;
> 'b'0111x => 'b'0111xxxxxxx;
> 'b'1000x => 'b'1000xxxxxxx;
> 'b'1001x => 'b'1001xxxxxxx;
> 'b'1010x => 'b'1010xxxxxxx;
> 'b'1011x => 'b'1011xxxxxxx;
> 'b'1100x => 'b'1100xxxxxxx;
> 'b'1101x => 'b'1101xxxxxxx;
> 'b'1110x => 'b'1110xxxxxxx;
> 'b'1111x => 'b'1111xxxxxxx;
>
> }
>
> Compiles to what you are seeking,
> o7 =>in1 o8 =>in2 o9 =>in3 o10 =>in4- Nascondi testo tra virgolette -
>
> - Mostra testo tra virgolette -
Wow! I'll try this as soon as possible.
The funny thing is I wrote to pldsupport@atmel for help on this and
they wrote me a couple emails saying they are still working on the
problem... !!!
Thankyou by now...
Article: 119318Are you using this for a source synchronous application? Thanks. CPArticle: 119319
Hello, I have recently bought a Virtex-4 LX25 evaluation board from Avnet. It has Cypress FX2 chip for USB 2.0 communication support. The generic USB driver provided by Cypress is of no use to me. Whenever I connect the USB of the board with the PC, the immediate message is "Unknown USB device". This happens because the VID and PID of the device received at the host is 0. I have tried installing the driver with EZUSBw2k.inf as well as CyUSB.inf but none has worked. Is there any body out there who has used the FX2 with Cypress provide generic USB driver? If someone has used USB with an Avnet board, that will prove very helpful to me. Looking forward to a sound advice. Thanks. - Javed RabbaniArticle: 119320
Hello, Is thery anyone who has worked with Avnet Virtex-4 LX25 evaluation board. I am trying to communicate with the board through the provide USB interface in the form of Cypress USB Fx2 chip. The driver installation is troubling me. The immedaite message that I receive upon connecying the board is "Unknown Device" as the VID and PID received is 0. Can anybody help me in this regard ? Thanks. - Javed Rabbani ShahArticle: 119321
austin wrote: > DO NOT let the smoke out. > You can not put the smoke back in. Yes, it's really difficult to get the smoke into a chip. Putting the smoke in at the factory requires a a fab costing upwards of a billion dollars!Article: 119322
motiwe@gmail.com writes: > I need to design DVI over FIBER > my idea to do as follow > > DVI to data then to FPGA > the FPGA will use memory sunc SDRAM or DDRAM > will send info via phy Assuminng that you can get more bandwidth out of the fiber than the DVI, you should be able to do it without any external RAM, and using only a very small amount of RAM in the FPGA for FIFO buffering. Design one block that receives the data from DVI into a FIFO, and a second that pulss data from the FIFO and transmits it on the fiber. When the FIFO is empty (or low), send a fill pattern on the fiber. At the receiving end, non-fill data from the fiber goes into a FIFO. There's a potential problem with rate mismatch between your DVI clocks at the two ends. If the transmitter derives the fiber clock frequency from the DVI using a PLL or DLL, the receivinng end can derive the DVI frequency from the fiber frequency, avoiding the problem.Article: 119323
Jim Granville wrote: > Kevin Neilson wrote: >> I know that an FPGA's power consumption is basically linear with clock >> frequency, but does anybody know what happens when the maximum clock >> frequency for the design is approached? Does power consumption remain >> linear in this region where failures and setup violations begin to >> occur, or would it then be expected to go up or down? Or is it >> totally design-dependent? > > It would depend. If (eg) counters start skipping clocks, then power > consumption would be expected to decrease, but only for the cells that > were hitting their thresholds. ( so a small % of total Icc ) > However, if something like a state engine starts short-cycling, then > power consumption could increase, again slighty. > > Why the question - are you thinking of using changes in Icc to flag > timing failures ? > > -jg > We had a design for which power consumption was linear up to near (but less than) the max rated frequency, and then the power consumption went down. I don't know if it's because of a timing failure--the design being tested has no self-checking mechanism--but I wondered if that were a possibility. -KevinArticle: 119324
Eric, Yes, to get the right amount of smoke into each transistor is incredibly difficult! With 65nm, the entire area of a FET is less than one square micron squared, so in a chip that is 10mm X 10mm (100 square mm), there are potentially a billion or more devices! Each device requires just the right amount, color, and smell of smoke. So, releasing all the smoke at once, well, they blew it! Austin
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