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On Feb 27, 9:15 pm, n...@puntnl.niks (Nico Coesel) wrote: > > I got a quote for a small quantity XC3S400-5PQ208C from Avnet a while > ago and they said the devices could be delivered from stock... > Good to know !! I'll forward this to the purchasing deparment. I'm afraid -5PQ208 is not ROHS compliant. (Not that it matters for in- house prototipes) Regards.Article: 116076
Austin Lesea wrote: > Tim, Uwe, > > I am told that parts were shipped to distributors, so they would be on > hand on the day of the introduction. Why else would we be so fussy > about the strict adherence to the release of information? Parts, > software, documentation, cores -- it all has to come together. One item > missing is unacceptable. > > The X-Store is another matter, and as you well know, Peter and I both > continue to spend time to try to improve that situation. > > The real good news is that the 3AN hits the streets today with ES parts > on the shelves of distributors. The lead times are stated at 2 to 4 > weeks in all the paperwork I have seen (probably just to make sure we do > not disappoint anyone, anywhere). > > Remember, we are changing how we introduce new products, and hope to > regain the trust of our customers. > > Austin > > If the xilinx store does not want to carry regular parts and the distributors do not want to carry ES parts, why not have the xilinx store carry the ES parts? That way something would be available to those who are willing to use ES parts. Since virtex 5 (non ES) is still not avaliable and virtex 4 is scarce, I am not expecting to see the 3AN in less than a year from now for us small folks. Of course, since versions 8 and 9 of ise are broken fatally for my designs, that may not be such an issue. I am still hoping that xilinx makes the software work with schematics while I am converting the projects to vhdl.Article: 116077
FYI : http://video.google.com/videoplay?docid=-4969729965240981475Article: 116078
look in grlib from gaisler research : www.gaisler.com On Mar 1, 5:39 am, raju.pe...@gmail.com wrote: > Hi, > > I am going through the net to download CAN VHDL core. > HurriCANe is removed from the ESA site, and the link in opencores site > for VHDL CAN core is going to some odd page. > > can you please guide me on where i can download this or if anyone does > have these free versions can you mail me ? > > Thank you for your time > > rajuArticle: 116079
On Thu, 28 Feb 2007, raju.penum@gmail.com wrote: "I am going through the net to download CAN VHDL core. HurriCANe is removed from the ESA site, [..] [..] or if anyone does have these free versions can you mail me ?" HurriCANe is not free. "and the link in opencores site for VHDL CAN core is going to some odd page. can you please guide me on where i can download this [..]" I shall attach it in a followup to this post, but you may have difficulty getting it to work. Xilinx ISE could not manage to fit it onto a Virtex2 nor a QPro Virtex Rad Hard xqvr300cb228-4 for me during the few minutes I tried, but it might be possible to get ISE to get it working for a VirtexE if ISE's warnings are surmountable.Article: 116080
I created a peripheral named o2p, it is a bridge to communicate the PLB Bus with a On Chip Bus(developed in my company). Using the BFM simulation, I was able to see that it works, afterthat I imported the peripheral and I tried to generate the netlist of the system with the new peripheral. I found the following error: ###################################################################### o2p_0_wrapper (o2p_0) - /home/ferorcue/my_work/project/xps/xps_200_5/system.mhs:122 - Running XST synthesis Running NGCBUILD ... ERROR:MDT - o2p_0_wrapper (o2p_0) - /home/ferorcue/my_work/project/xps/xps_200_5/system.mhs:122 - failed to copy to implementation ERROR:MDT - platgen failed with errors! make: *** [implementation/o2p_0_wrapper.ngc] Error 2 ###################################################################### the file o2p_0_wrapper_xst.srp shows the following information: ###################################################################### Analyzing generic Entity <xilinx_fifo> (Architecture <rtl>). DATA_W = 64 LOG2_LENGTH = 4 WARNING:Xst:821 - "/home/ferorcue/my_work/project/xps/xps_200_5/pcores/ o2p_v1_00_a/hdl/vhdl/xilinx_fifo.vhd" line 59: Loop body will iterate zero times WARNING:Xst:1994 - "/home/ferorcue/my_work/project/xps/xps_200_5/ pcores/o2p_v1_00_a/hdl/vhdl/xilinx_fifo.vhd" line 140: Null range in type of signal <dip_bram>. WARNING:Xst:1994 - "/home/ferorcue/my_work/project/xps/xps_200_5/ pcores/o2p_v1_00_a/hdl/vhdl/xilinx_fifo.vhd" line 141: Null range in type of signal <dop_bram>. WARNING:Xst:1995 - "/home/ferorcue/my_work/project/xps/xps_200_5/ pcores/o2p_v1_00_a/hdl/vhdl/xilinx_fifo.vhd" line 474: Use of null array on signal <dop_bram> is not supported. INTERNAL_ERROR:Xst:cmain.c:3068:1.158.10.1 - To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com ###################################################################### xilinxs_fifo.vhd is a FIFO, this file and all the files of my peripheral o2p are synthesiable, I checked with synplify_pro( any errors and also any important warnings). My system is a PowerPC, and I run the XPS in windows and in Linux with the same results. The edk directory does not contains any spaces: /home/ferorcue/simlib/EDK8.1.02_mti_se_linux/EDK_Lib/ /home/ferorcue/simlib/EDK8.1.02_mti_se_linux/ISE_Lib/ I did not find any appropriate information in the Answers Database of xilinxs.com. Any clue? Thank very much.Article: 116081
"Patrick Dubois" <prdubois@gmail.com> writes: > Hello, > > I have been using batch files to handle the build process with a > Xilinx flow for a while. Now I want to move to a more sophisticated > approach to handle dependencies better. > This has just reminded me of something I discovered recently: Neither PAR nor TRCE return an error if the design fails timing, so any script/makefile which relies on the return code being non-zero as an error (like... well... just about anything sane!) will carry on through it's script as if everything is OK! You have to parse the PAR logfile for "No timing errors found" if you want to be sure. I have a change request in to fix this, please add your weight to the request (unless you think I'm bonkers for thinking that failing timing is an error!) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 116082
On Feb 28, 11:12 pm, "Brandon Jasionowski" <killerhe...@gmail.com> wrote: > Hello, > > I'm getting usual results from my BUFR network in Timing Analyzer: > > <SNIP> > -------------------------------------------------------------------------------- > Hold Violations: TS_adc1_dclk_p = PERIOD TIMEGRP "TG_adc1_dclk_p" 4 ns > HIGH 50%; > -------------------------------------------------------------------------------- > Hold Violation: -0.974ns (requirement - (clock path skew + > uncertainty - data path)) > Source: adc1_reg_inst/nshifts_gen[1].dff_ins/d_r_7 > (FF) > Destination: adc1_reg_inst/nshifts_gen[2].dff_ins/d_r_7 > (FF) > Requirement: 0.000ns > Data Path Delay: 1.275ns (Levels of Logic = 0) > Positive Clock Path Skew: 2.249ns > Source Clock: adc1_dclk rising at 0.000ns > Destination Clock: adc1_dclk rising at 4.000ns > Clock Uncertainty: 0.000ns > Timing Improvement Wizard > Data Path: adc1_reg_inst/nshifts_gen[1].dff_ins/d_r_7 to > adc1_reg_inst/nshifts_gen[2].dff_ins/d_r_7 > Delay type Delay(ns) Logical Resource(s) > ---------------------------- ------------------- > Tcko 0.268 adc1_reg_inst/nshifts_gen[1].dff_ins/ > d_r_7 > net (fanout=1) 1.065 adc1_reg_inst/d_array<2><7> > Tckdi (-Th) 0.058 adc1_reg_inst/nshifts_gen[2].dff_ins/ > d_r_7 > ---------------------------- --------------------------- > Total 1.275ns (0.210ns logic, 1.065ns route) > (16.5% logic, 83.5% route) > </SNIP> > > 2.25 ns positive clock path skew? Omg!? So, then I looked at the > partially PAR'ed output on this SX55 FPGA. Turns out the stupid tools > are expanding the BUFR network across multiple BUFR regions, including > horizontally (x direction). I have an 8k FIFO (necessary) to > transition from this BUFR clock to a slower BUFG clock. Looks like the > tools are placing the FIFO on the left side of the FPGA and the top- > right BUFR is using non BUFR resources (I assume) to route the clock > across. > > Is this what's causing my enormous clock path skew? I will try to > apply some area_group slice/bram constraints to my FIFOs, but I find > this to be an extreme pain in the butt... I'm using a COTS board, > which is configured with 4 ADC data channels and 4 ADC clocks. The ADC > data is about 180 degrees out of phase w/ the clock (fine). Is there a > way to constrain nets/instances/etc. to a regional clock region? > That'd be really sweet... > > Is there a better way to transition from the regional clock to a > global clock other than using a FIFO? This is giving me a headache b/c > my design takes forever to PAR and I can't meet timing :( > > Thanks, > -B When we first started using the regional clock buffer in our designs, the tools did not automatically place the logic that used that clock into the three clock regions that the clock could reach. In my case, it just failed to route. Our solution was to put an area group constraint on the logic that used that clock, and that fixed the problem. This was with a 7.x version of EDK/ISE. That little inconvenience aside, the BUFIOs and BUFRs are very nice. The BUFR is what makes it possible for us to meet timing for 66 MHz PCI on a V4FX60. As the FPGAs get bigger, the BUFG delays get longer. On PCI, you should not use a DCM to tune out the clock delay because the clock speed is allowed to vary, but I don't know how many system do that. Regards, John McCaskill www.fastertechnology.comArticle: 116083
Hey Guys, It's a been a while since we had a bypass capacitor religious war, so I thought I'd stir things up a bit! Seriously, I've been reading about X2Y capacitors, and a search of the newsgroup revealed that these very interesting parts have only been mentioned once or twice in passing. (By Austin, natch!) Check out :- http://www.teraspeed.com/publications.html Where they ask you to register for :- http://www.teraspeed.com/papers/cap_considerations_fpga_pds.pdf Steve Weir does a great job of showing why X2Y caps give you more bang for your buck. As these parts have exceptionally low inductance, they can substantially reduce the number of capacitors AND vias you need, and they quote that :- "Can replace from three to six+ regular caps depending on via and plane geometries" "Vias at $0.005/hole / $0.01 / capacitor typical, often COST MORE than the capacitors they connect!" Here's another interesting article:- http://www.x2y.com/bypass/mount/backside_cap.pdf They recommend using small 'puddles' of copper to connect all the bypass elements together so you can use fewer capacitors but keep the same bypass network performance. Check out http://www.x2y.com/bypass.htm for more articles. AFAICS, the main drawback is that X2Y caps are available in a range of values. This means nutters will use several different values in their bypass networks to create 'resonances' and the like. :-) Anyway, I hope this is of interest, Syms.Article: 116084
On Feb 28, 9:14 pm, Tim <t...@nooospam.roockyloogic.com> wrote: > mtsuka...@gmail.com wrote: > > on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding > > information on this. Using Impact. > > It reads back the program from the device and checks that the device is > blank. That used to mean checking that all the bits were set to '1'. No > doubt devices are more complicated now. I guess what I'm particularly asking is, on a 'blank check' do the signals and/or pins in the CPLD get set to 0 or 1? or what? I'm trying to find out because the particular design i'm working on, 'works' if I do a 'blank check' on the CPLD.Article: 116085
Daniel S. wrote:
> Assigning a value to a signal from within a synchronous process will
> always infer FFs. Results with variables may vary wildly from one
> synthesis/simulation tool to another and how they get interpreted is
> also highly dependent on how the code is arranged.
Synthesis results will match simulation.
Simulation will match the LRM.
Nothing varies wildly.
> Using signals
> exclusively avoids introducing unnecessary confusion.
As does using variables exclusively.
Some examples:
http://home.comcast.net/~mike_treseler/
-- Mike Treseler
Article: 116086> This has just reminded me of something I discovered recently: > > Neither PAR nor TRCE return an error if the design fails timing, so > any script/makefile which relies on the return code being non-zero as > an error (like... well... just about anything sane!) will carry on > through it's script as if everything is OK! > > You have to parse the PAR logfile for "No timing errors found" if you > want to be sure. > > I have a change request in to fix this, please add your weight to the > request (unless you think I'm bonkers for thinking that failing timing > is an error!) > > Cheers, > Martin Very good point. I always try to remind new engineers here to always remember to check the timing report part of the PAR log to make sure that there are no timing errors. I'll try to open a webcase on the issue. Do you have a CR number I can refer to? PatrickArticle: 116087
mtsukanov@gmail.com wrote: > On Feb 28, 9:14 pm, Tim <t...@nooospam.roockyloogic.com> wrote: >> mtsuka...@gmail.com wrote: >>> on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding >>> information on this. Using Impact. >> It reads back the program from the device and checks that the device is >> blank. That used to mean checking that all the bits were set to '1'. No >> doubt devices are more complicated now. > > > I guess what I'm particularly asking is, on a 'blank check' do the > signals and/or pins in the CPLD get set to 0 or 1? or what? > > I'm trying to find out because the particular design i'm working on, > 'works' if I do a 'blank check' on the CPLD. You should have the option to "erase part." If you do that, then program the device without the "blank check" your design will still work. If the check box is the difference between working and not working, then the software apparently notices the previously programmed device *isn't* blank and performs the erasure, setting all bits to the same polarity through the bulk erase process, allowing the programmed bits - and only the programmed bits - to be the opposite polarity. If you're programming a bunch of new parts, it's convenient to skip the check for a blank device to save time. If parts were never in the erased state, the device would always be erased first and there would be no need for that check box.Article: 116088
Hello, I have a problem with the latest Xilinx ISE webpack software (9.1, service pack 2). Nice thing is that the design (24bit CORDIC rotator written in VHDL) seems to run faster (181MHz) compared to version 8.2 of ISE webpack (164MHz). Not so nice thing is that the RTL viewer seems to screw up (or sort in a *very strange* way) the compiled design. In 8.2 everything looks quite nice (3 n-bit adders, three n-bit FFs per stage drawn vertically), the structure is clearly visible. Other in 9.1. RTL viewer sorts the parts (first all n-bit FFs, then all adders, all drawn in a vertical chain). This completely clutters up the generated schematic. Additionally some blocks are even drawn wrong. Is this a known problem or does my VHDL code probably compile different in different versions? Regards Robert -- dnn engineering Robert M. Ganter Belchenring 63 Tel: +41(0)61 301 9538 4123 Allschwil Fax: +41(0)61 301 9537 Schweiz Mobile: +41(0)76 376 6078Article: 116089
Hello, I am just looking for the Jpeg 2000 source in VHDL, can anyone help me? thanx many! fredArticle: 116090
On 1 Mrz., 01:21, lb....@telenet.be wrote: > Hi, > > If you know how to write your framing and encoding for SONET you might > get there with V4, otherwise look for other solutions - better > documented, proven technology, etc... Actually, we are not doing SONET, we are only using the same sync pattern. We have confirmed in simulation and with chipscope that the byte aligner does not "hold alignment mux position" when ENxCOMMAALIGN='0': We have 20 prototypes in production so moving to another vendor or moving to Virtex-5 is not an option at this moment. KoljaArticle: 116091
"TC" <noone@nowhere.com> wrote in message news:u0oFh.7044$_73.434@newsread2.news.pas.earthlink.net... > > "Fred" <fred@n0spam.com> wrote in message > news:1172664477.23596.0@proxy00.news.clara.net... >> I'm writing the initial state machine for a PCI-Express card and am stuck >> at the very first hurdle. I'm using a Philips PX1011 PHY and I'm able >> detect the receiver on the motherboard. >> >> I then send it TS1s with pad characters in the Link and Lane numbers but >> the motherboard transmitter doesn't transmit TS2 but instead goes into >> idle state. I'm convinced that correct serial data is coming out of the >> PHY. There's no need for speed negotiation since both are advertising the >> slowest speed. >> >> I would be grateful if anyone here could help. >> >> > > If you designed/developed the board are you sure that you didn't simply > swap Rx and Tx? You wouldn't be the first to do that! The signal naming convention is perhaps ambiguous but the signals are definitely the correct way round. > > How are you debugging this? Do you have equipment connected (oscilliscopes > or logic analyzers) that let you directly observer the link (differential > pairs) or are you inferring what is going on? > > You didn't say if the motheboard transmitted TS1s, or not. > > If the motherboard DID NOT transmit TS1's then the motheboard probably > didn't succesfully "detect" your board (i.e. never exited the detect state > and never entered the polling state). > > If the motherboard did transmit TS1s and then eventually went back to > electical-idle then it probably isn't receiving your TS1s correctly (and > it is configured to NOT go into "compliance mode"). > Many thanks - this is presently this is my conclusion. Unfortunately, while PHYs have a loopback mode they don't have a simple means of connecting RX input to TX output to ensue that anything transmitted isn't garbage! Many thanks again.Article: 116092
Symon, Another interesting alternative (playstation uses four per big ASIC, and no other caps at all) is: http://www.nec-tokin.com/english/product/cap/proadlizer/index.html AustinArticle: 116093
On Mar 1, 9:27 am, John_H <newsgr...@johnhandwork.com> wrote: > mtsuka...@gmail.com wrote: > > On Feb 28, 9:14 pm, Tim <t...@nooospam.roockyloogic.com> wrote: > >> mtsuka...@gmail.com wrote: > >>> on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding > >>> information on this. Using Impact. > >> It reads back the program from the device and checks that the device is > >> blank. That used to mean checking that all the bits were set to '1'. No > >> doubt devices are more complicated now. > > > I guess what I'm particularly asking is, on a 'blank check' do the > > signals and/or pins in the CPLD get set to 0 or 1? or what? > > > I'm trying to find out because the particular design i'm working on, > > 'works' if I do a 'blank check' on the CPLD. > > You should have the option to "erase part." If you do that, then > program the device without the "blank check" your design will still work. > > If the check box is the difference between working and not working, then > the software apparently notices the previously programmed device *isn't* > blank and performs the erasure, setting all bits to the same polarity > through the bulk erase process, allowing the programmed bits - and only > the programmed bits - to be the opposite polarity. > > If you're programming a bunch of new parts, it's convenient to skip the > check for a blank device to save time. If parts were never in the > erased state, the device would always be erased first and there would be > no need for that check box. Hmm... I'm not completely sure I understand what u said, but let me clarify a little more on what's happening: The CPLD is connected to a xcf32 PROM and to a Xilinx V4 FPGA. All the CPLD is doing is connecting the signals going from the PROM to the FPGA - primarily the 'done' and 'd_in' pins. So, when I program the CPLD, it works right away, and the FPGA gets programmed from the PROM. If I turn off the POWER to the whole system, turn it back on - nothing happens. The FPGA does'nt get programmed from the PROM. *IF at that point I right click on the CPLD in Impact, and select 'blank check', the CPLD starts 'working' and the FPGA gets programmed. The V4 is working in 'master' mode, and I checked the CCLK and it runs just fine after board powerup, thought the d_in has garbage on it. The d_in turns good when i do the 'blank check' on the CPLD or when I reprogram the CPLD. That's why I'm wondering if the 'blank check' drives the CPLD's pins to 0 or 1 during the 'blank check' operation, something funky like that thanks again, any help is much appreciatedArticle: 116094
Here is some more detail, in case someone has any suggestions. We transmit some random data and then insert this sequence: 6F6F6F6F 6F6F6F6F 14141414 14141414 E220BBDE 9620DD9A 90392A84 AAB44413 72642AF0 DF353E5C 16888F7F 52AAF5E6 2A4D4995 4EC21316 E399DB7C 6A4C770D from the the receiver we get a one clock cycle pulse of RXCOMMADET and RXREALIGN. As a consequence we immediately negate ENMCOMMAALIGN and ENPCOMMAALIGN. There is some pipeline delay and after seven clock cycles the receiver outputs: EDEDEDED 6F6F6F6F (byte alignment took place) 14141414 14141414 E220BBDE 9620DD9A 90392A84 AAB44413 72642AF0 DF353E5C 16888F7F 52AAF5E6 2A4D4995 4EC21316 (everything fine till here) 6F1CCEDB (new alignment took place to first 6F) 9B5263B8 (data is no longer aligned correctly) Clearly the byte aligner ist still operating 21 clock cycles after it has been disabled. Or is there any other part of the MGT that could affect the output data stream in the way described? RXCOMMADET and RXREALIGN are not asserted by the receiver again. We see exactly the same behaviour in simulation and with chipscope. Kolja SulimmaArticle: 116095
On Mar 1, 10:41 am, mtsuka...@gmail.com wrote: > The CPLD is connected to a xcf32 PROM and to a Xilinx V4 FPGA. All the > CPLD is doing is connecting the signals going from the PROM to the > FPGA - primarily the 'done' and 'd_in' pins. So, when I program the > CPLD, it works right away, and the FPGA gets programmed from the PROM. > If I turn off the POWER to the whole system, turn it back on - nothing > happens. The FPGA does'nt get programmed from the PROM. *IF at that > point I right click on the CPLD in Impact, and select 'blank check', > the CPLD starts 'working' and the FPGA gets programmed. Try some other non-destructive operations - the most trivial would be read idcode It may be that the CPLD's jtag stage machine is waking up in a state that keeps the CPLD from running; executing one of these operations probably finished by putting it back into operational state. As a guess, when it's in programming state, the ordinary I/O's would all be high-Z. Depending on pullup resistors, it's possible that exiting from programming state to operating state could be producing a clock edge necessary to start the process of loading your FPGA...Article: 116096
Symon - On Thu, 1 Mar 2007 13:17:04 -0000, "Symon" <symon_brewer@hotmail.com> wrote: >Hey Guys, >It's a been a while since we had a bypass capacitor religious war, so I >thought I'd stir things up a bit! >Seriously, I've been reading about X2Y capacitors, and a search of the >newsgroup revealed that these very interesting parts have only been >mentioned once or twice in passing. (By Austin, natch!) > >Check out :- >http://www.teraspeed.com/publications.html >Where they ask you to register for :- >http://www.teraspeed.com/papers/cap_considerations_fpga_pds.pdf > >Steve Weir does a great job of showing why X2Y caps give you more bang for >your buck. As these parts have exceptionally low inductance, they can >substantially reduce the number of capacitors AND vias you need, and they >quote that :- >"Can replace from three to six+ regular caps depending on via and plane >geometries" >"Vias at $0.005/hole / $0.01 / capacitor typical, often COST MORE than the >capacitors they connect!" I saw Steve Weir's presentation on this very subject at an IEEE Santa Clara Valley EMC meeting a year or two ago. Good stuff. You raise an interesting point about costs. We often add up the costs of those things that are easy to tally--parts costs, for example--then forget to account for other things that may be just as significant or more so, such as vias. Another cost that's often poorly accounted for is component placement. Some years ago I worked with an analog designer who was trying to figure out how much it cost an assembly house to place a small discrete component on a board. He asked our assembly house, which declined to give us a precise--or even semi-precise--answer. (Some assembly houses seem to treat their formula for calculating board assembly costs as a trade secret; I guess they're afraid the customers will use the formula to sanity-check future quotes.) This analog designer, a very bright fellow, was not to be deterred by this, and proceeded to create his own formula based on a number of assemblies we'd built (if you try this, it helps when you have some assemblies with only ICs, and other assemblies with ICs plus about 5,000 analog parts). He concluded that while we were paying a penny for a capacitor or resistor, we paid the assembly house 8 or 9 cents to place the part on the board. Maybe this is the correct number and maybe it isn't, but it bolsters your point that reducing total component cost may not lead to the lowest overall assembly cost. Bob Perlman Cambrian Design Works http://www.cambriandesign.com >Here's another interesting article:- >http://www.x2y.com/bypass/mount/backside_cap.pdf > >They recommend using small 'puddles' of copper to connect all the bypass >elements together so you can use fewer capacitors but keep the same bypass >network performance. > >Check out http://www.x2y.com/bypass.htm for more articles. > >AFAICS, the main drawback is that X2Y caps are available in a range of >values. This means nutters will use several different values in their bypass >networks to create 'resonances' and the like. :-) > >Anyway, I hope this is of interest, Syms. >Article: 116097
Hi
Since Version 7.x xilinx xst is able to infer block ram out of appropriate
vhdl statements. Unfortunately it is not working in the example given
below. Does anybody have an idea why the code below gives the following
warning:
WARNING:Xst:1440 - Cannot use block RAM resources. Please check that the RAM
contents is read synchronously.
Thanks
ST
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity BRAM_test is
port (CLOCK : in std_logic;
reset : in std_logic;
di : in std_logic_vector(15 downto 0);
do : out std_logic_vector(15 downto 0));
end BRAM_test;
architecture syn of BRAM_test is
type ram_type is array (1023 downto 0) of std_logic_vector (15 downto 0);
signal RAM : ram_type;
attribute ram_style : string;
attribute ram_style of RAM: signal is "block";
type STATE_TYPE is (P1, P2, P3);
signal STATE : STATE_TYPE;
signal addr : std_logic_vector(9 downto 0);
begin
main : process (CLOCK, RESET)
begin
if (RESET = '1') then
STATE <= P1;
addr <= (others => '0');
elsif (CLOCK'event and CLOCK = '1') then
case STATE is
when P1 =>
RAM(conv_integer(addr)) <= di;
STATE <= P2;
when P2 =>
do <= RAM(conv_integer(addr));
STATE <= P3;
when P3 =>
addr <= addr + '1';
STATE <= P1;
end case;
end if;
end process main;
end syn;
Article: 116098On Mar 1, 10:56 am, cs_post...@hotmail.com wrote: > On Mar 1, 10:41 am, mtsuka...@gmail.com wrote: > > > The CPLD is connected to a xcf32 PROM and to a Xilinx V4 FPGA. All the > > CPLD is doing is connecting the signals going from the PROM to the > > FPGA - primarily the 'done' and 'd_in' pins. So, when I program the > > CPLD, it works right away, and the FPGA gets programmed from the PROM. > > If I turn off the POWER to the whole system, turn it back on - nothing > > happens. The FPGA does'nt get programmed from the PROM. *IF at that > > point I right click on the CPLD in Impact, and select 'blank check', > > the CPLD starts 'working' and the FPGA gets programmed. > > Try some other non-destructive operations - the most trivial would be > read idcode > > It may be that the CPLD's jtag stage machine is waking up in a state > that keeps the CPLD from running; executing one of these operations > probably finished by putting it back into operational state. > > As a guess, when it's in programming state, the ordinary I/O's would > all be high-Z. Depending on pullup resistors, it's possible that > exiting from programming state to operating state could be producing a > clock edge necessary to start the process of loading your FPGA... Yea I actually tried doing 'id code' read, it didn't do anything, didn't produce the same results as doing a 'blank check' or reprogramming.Article: 116099
On Mar 1, 5:54 am, "ferorcue" <le_m...@hotmail.com> wrote:
> I created a peripheral named o2p, it is a bridge to communicate the
> PLB Bus with a On Chip Bus(developed in my company). Using the BFM
> simulation, I was able to see that it works, afterthat I imported the
> peripheral and I tried to generate the netlist of the system with the
> new peripheral. I found the following error:
>
> ######################################################################
> o2p_0_wrapper (o2p_0) -
> /home/ferorcue/my_work/project/xps/xps_200_5/system.mhs:122 - Running
> XST
> synthesis
>
> Running NGCBUILD ...
>
> ERROR:MDT - o2p_0_wrapper (o2p_0) -
> /home/ferorcue/my_work/project/xps/xps_200_5/system.mhs:122 -
> failed to copy
> to implementation
> ERROR:MDT - platgen failed with errors!
>
> make: *** [implementation/o2p_0_wrapper.ngc] Error 2
>
> ######################################################################
>
> the file o2p_0_wrapper_xst.srp shows the following information:
>
> ######################################################################
> Analyzing generic Entity <xilinx_fifo> (Architecture <rtl>).
> DATA_W = 64
>
> LOG2_LENGTH = 4
>
> WARNING:Xst:821 - "/home/ferorcue/my_work/project/xps/xps_200_5/pcores/
> o2p_v1_00_a/hdl/vhdl/xilinx_fifo.vhd" line 59: Loop body will iterate
> zero times
> WARNING:Xst:1994 - "/home/ferorcue/my_work/project/xps/xps_200_5/
> pcores/o2p_v1_00_a/hdl/vhdl/xilinx_fifo.vhd" line 140: Null range in
> type of signal <dip_bram>.
> WARNING:Xst:1994 - "/home/ferorcue/my_work/project/xps/xps_200_5/
> pcores/o2p_v1_00_a/hdl/vhdl/xilinx_fifo.vhd" line 141: Null range in
> type of signal <dop_bram>.
> WARNING:Xst:1995 - "/home/ferorcue/my_work/project/xps/xps_200_5/
> pcores/o2p_v1_00_a/hdl/vhdl/xilinx_fifo.vhd" line 474: Use of null
> array on signal <dop_bram> is not supported.
> INTERNAL_ERROR:Xst:cmain.c:3068:1.158.10.1 - To resolve this error,
> please consult the Answers Database and other online resources athttp://support.xilinx.com
> ######################################################################
>
> xilinxs_fifo.vhd is a FIFO, this file and all the files of my
> peripheral o2p are synthesiable, I checked with synplify_pro( any
> errors and also any important warnings).
>
> My system is a PowerPC, and I run the XPS in windows and in Linux with
> the same results. The edk directory does not contains any spaces:
> /home/ferorcue/simlib/EDK8.1.02_mti_se_linux/EDK_Lib/
> /home/ferorcue/simlib/EDK8.1.02_mti_se_linux/ISE_Lib/
>
> I did not find any appropriate information in the Answers Database of
> xilinxs.com. Any clue? Thank very much.
You said that you checked that this was synthesizable with synplify
pro, but the EDK report file shows that it is using XST for
synthesis.
I would guess from these lines that XST does not support what you are
trying to do:
> WARNING:Xst:1995 - "/home/ferorcue/my_work/project/xps/xps_200_5/
> pcores/o2p_v1_00_a/hdl/vhdl/xilinx_fifo.vhd" line 474: Use of null
> array on signal <dop_bram> is not supported.
^^^^^^^^^^^^^^^^^
> INTERNAL_ERROR:Xst:cmain.c:3068:1.158.10.1 - To resolve this error,
> please consult the Answers Database and other online resources athttp://support.xilinx.com
Either change your EDK setup to use synplify pro for synthesis, or
recode what XST is complaining about.
Regards,
John McCaskill
www.fastertechnology.com
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