Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Mar 3, 8:25 am, Sean Durkin <news_ma...@durkin.de> wrote: > Brandon Jasionowski wrote: > > It's really bothering me that the instance is maintained in the ngc, > > but not after Translate. What is going on exactly? Is there anything > > else I can do? > > Unused logic is not removed until translate or par (can't remember now). > In the schematic view even those things show up that get optimized away > later. > > If your instance is not there after translate/map, then it was probably > removed completely for some reason. Maybe because it was never used, > produces only constant outputs or something. > > -- > My email address is only valid until the end of the month. > Try figuring out what the address is going to be after that... Well, I dont' believe the the logic is being removed because the input and output registers of that instance still persists in floorplanner under "Primitives", not under it's instance name. There's some other LUTs that have those jibberish names like "_and00001", "Mcompar__cmp_gt0001_lut", etc. The i/o net names of these primitives sometimes correspond to the internal net names of the entity in question, which further leads me to believe the logic is still all there. I'm not sure if this is common or not, because I wouldn't normally care about instances being dissolved, as I rarely put constraints on INSTances. Now that I'm working with BUFRs, I'm finding I need to assign AREA_GROUP constraints to anything clocked by them, this instance being one of them... Thanks.Article: 116176
On Mar 3, 12:55 am, kaosnan...@gmail.com wrote: > I am using these programs in my digital class but do not know how to > link modelsim to ISE. In our school lab, after I make my schematic, I > can run model sim to simulate it from inside ISE. Does someone know > how I would set this up? Open up ISE. Edit > Preferences > ISE General > Integrated Tools Browse to modelsim.exe. If you change the Sources pulldown to Behavioral Simulation in your project, you can select a test-bench, right-click > properties on the ModelSim icon to change some properties.Article: 116177
Hi every body ,
i hope that you can help me , i want to do this operation:
s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1
when i check the syntax , i have these errors
ERROR:HDLParsers:808 - "C:/Xilinx/projet/operation.vhd" Line 44. *
can
not have such operands in this context.
----------------------------------------------------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity operation is
Port ( clk : in STD_LOGIC;
c1 : in STD_LOGIC_VECTOR (7 downto 0);
c2 : in STD_LOGIC_VECTOR (7 downto 0);
c 3: in STD_LOGIC_VECTOR (7 downto 0);
s: out STD_LOGIC_VECTOR (7 downto 0);
end operation;
architecture Behavioral of operation is
begin
s <=c1 * 0.2 + c2 * 0.6 + c3 * 0.1 ;
end Behavioral;
----------------------------------------------------------------------------------------------------------------------------------------------------------
and thanks for your help
Article: 116178On Feb 19, 7:00 pm, "Aaron" <weiro...@gmail.com> wrote: > Hi all, > > I want to evaluate the area and time cost of an intermediate product > on Xilinx FPGA. But the number of > output ports exceed number of I/O pins. (Actually there will be much > less outputs in the final product. ) > > But currently, I need test the intermediate product by using Xilinx > ISE. Can I add some ISE specific declaration to avoid the fully IO > mapping while I can still get the area and time cost reports? > > Thanks a lot. > > Sincerely, > Aaron In addition to the suggestions others have already given you, you can also define an area group for the logic you want to evaluate, and the MAP and PAR reports will give you a resource utilization report for each area group that you have defined within your design. Regards, John McCaskill www.fastertechnology.comArticle: 116179
VHDL_HELP wrote: > Hi every body , > i hope that you can help me , i want to do this operation: > s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1 > when i check the syntax , i have these errors > ERROR:HDLParsers:808 - "C:/Xilinx/projet/operation.vhd" Line 44. * > can > not have such operands in this context. > > ---------------------------------------------------------------------------------------------------------------------------------------------------------------- > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity operation is > Port ( clk : in STD_LOGIC; > c1 : in STD_LOGIC_VECTOR (7 downto 0); > c2 : in STD_LOGIC_VECTOR (7 downto 0); > c 3: in STD_LOGIC_VECTOR (7 downto 0); > s: out STD_LOGIC_VECTOR (7 downto 0); > > end operation; > > architecture Behavioral of operation is > > begin > > s <=c1 * 0.2 + c2 * 0.6 + c3 * 0.1 ; > > end Behavioral; > > ---------------------------------------------------------------------------------------------------------------------------------------------------------- > and thanks for your help Can you tell me how the synthesizer will format your floating point result in s so it maps to silicon? Use scaled integers. Use the precision available in the hardware multipliers to get a rather precise approximation of s. The digital realm is binary, after all, not decimal. Please read up on how the hardware multipliers perform and how best to utilize them. It's insanely sad to see someone trying to "program" an FPGA rather than design it.Article: 116180
i. I'm trying to to put uClinux on my Spartan 3 Starter Board (it hasn't flash memory and it has only 1MB RAM). Finally I've made an uClinux < 1MB (986 KB :-P ). Now I've downloaded Microblaze on SP3 using XPS, but I want to know, do I need bootloader to startup uClinux from RAM? How to download image.bin on it and startup it? (I'm using XPS for Win XP). ThanksArticle: 116181
On Mar 3, 8:27 am, "Brandon Jasionowski" <killerhe...@gmail.com> wrote: > On Mar 3, 8:25 am, Sean Durkin <news_ma...@durkin.de> wrote: > > > > > Brandon Jasionowski wrote: > > > It's really bothering me that the instance is maintained in the ngc, > > > but not after Translate. What is going on exactly? Is there anything > > > else I can do? > > > Unused logic is not removed until translate or par (can't remember now). > > In the schematic view even those things show up that get optimized away > > later. > > > If your instance is not there after translate/map, then it was probably > > removed completely for some reason. Maybe because it was never used, > > produces only constant outputs or something. > > > -- > > My email address is only valid until the end of the month. > > Try figuring out what the address is going to be after that... > > Well, I dont' believe the the logic is being removed because the input > and output registers of that instance still persists in floorplanner > under "Primitives", not under it's instance name. There's some other > LUTs that have those jibberish names like "_and00001", > "Mcompar__cmp_gt0001_lut", etc. The i/o net names of these primitives > sometimes correspond to the internal net names of the entity in > question, which further leads me to believe the logic is still all > there. > > I'm not sure if this is common or not, because I wouldn't normally > care about instances being dissolved, as I rarely put constraints on > INSTances. Now that I'm working with BUFRs, I'm finding I need to > assign AREA_GROUP constraints to anything clocked by them, this > instance being one of them... > > Thanks. What I have done on my designs that use BUFRs is to put an HU_SET attribute on the module that contains the BUFR clock domain, then use that to create the area group. Another way that you can constrain the logic that uses the BUFR clock is to form a timing group from the clock net, then create an area group from the timing group. Take a look at the area group section of the constraints guide. Here is an example from page 104 of the 8.2 version of the constraints guide: For example, assume you have the following UCF constraints: NET "clk" TNM_NET="clock"; TIMESPEC "TS_clk" = PERIOD "clock" 10 MHz; TIMEGRP "clock" AREA_GROUP="clock_area"; I have not tried doing it this way yet. It would be nice if the tools would just do this for you automatically. Regards, John McCaskill www.fastertechnology.comArticle: 116182
John_H wrote: > VHDL_HELP wrote: >> Hi every body , >> i hope that you can help me , i want to do this operation: >> s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1 >> when i check the syntax , i have these errors >> ERROR:HDLParsers:808 - "C:/Xilinx/projet/operation.vhd" Line 44. * >> can >> not have such operands in this context. >> >> ---------------------------------------------------------------------------------------------------------------------------------------------------------------- >> >> library IEEE; >> use IEEE.STD_LOGIC_1164.ALL; >> use IEEE.STD_LOGIC_ARITH.ALL; >> use IEEE.STD_LOGIC_UNSIGNED.ALL; >> >> entity operation is >> Port ( clk : in STD_LOGIC; >> c1 : in STD_LOGIC_VECTOR (7 downto 0); >> c2 : in STD_LOGIC_VECTOR (7 downto 0); >> c 3: in STD_LOGIC_VECTOR (7 downto 0); >> s: out STD_LOGIC_VECTOR (7 downto 0); >> >> end operation; >> >> architecture Behavioral of operation is >> >> begin >> >> s <=c1 * 0.2 + c2 * 0.6 + c3 * 0.1 ; >> >> end Behavioral; >> >> ---------------------------------------------------------------------------------------------------------------------------------------------------------- >> >> and thanks for your help > > Can you tell me how the synthesizer will format your floating point > result in s so it maps to silicon? > > Use scaled integers. Use the precision available in the hardware > multipliers to get a rather precise approximation of s. The digital > realm is binary, after all, not decimal. > > Please read up on how the hardware multipliers perform and how best to > utilize them. It's insanely sad to see someone trying to "program" an > FPGA rather than design it. I had a nice, well considered reply that got lost because my newsreader crashed when I was posting the reply. Attempts to cut-and-paste the crashing program failed. Please respond to the newsgroup rather than directly in order to keep an open conversation and allow others to learn and to help. I didn't mean to come across as "angry" or "sad" and you shouldn't be sorry about asking the question. What I wanted you to do is look more closely at how the synthesizer might try to build hardware out of your statement. Condensing what I lost into a few short comments: looking at c1*0.2, you can instead use the 18-bit signed multipliers in the Xilinx FPGA (17-bit unsigned) to provide a result that is 2^n too large by using 0.2*2^n instead of 0.2 and dividing the result by 2^n (shifting it by n bits) to get the same approximate result with integer arithmetic. In Verilog, the 17-bit hex number (from 0.2*2^19) and right shift operator could look like (c1 * 17'h1999a) >> 19 This intermediate value is a good approximation of c1*0.2 but will not necessarily provide "exact" results depending on your expectations. You could also make the intermediate values compatible with each other so the addition doesn't lose any precision. Rather than losing 19 bits of remainder to get a 6-bit result from your 8-bit c1 value, you could keep more or all of those bits and add the integers and remainders to get less error overall. You may also benefit by pipelining your operation where you register the c1*17"h1999a intermediate result and add it with the other multiplies on the following clock, producing a result one clock later than with everything performed in parallel. Read up on the Xilinx multipliers in your target device to understand their implementation, limits, and capabilities. There are those who believe the first rule in public speaking is to "know your audience" so you can communicate your thoughts most effectively. I believe the first rule in RTL design should be to "know your silicon" so you can communicate your intents to the synthesizer most effectively. Hardware design is great fun but the end result is always silicon. - John_HArticle: 116183
aholtzma@gmail.com wrote: > On Mar 2, 3:34 am, Steve Battazzo <thesteveman_i...@yahoo.co.jp> > wrote: >> Hello, guys... another question. >> >> I've started playing around with this software a bit and when I tried to >> use floorplanner I got this error: >> >> error while loading shared libraries: libXm.so.3: cannot open shared >> object file: no such file or directory >> >> Do I need to find this file and get it into the appropriate directory, >> or is it there and I just need to point the program to it? >> >> Thanks, >> >> Steve > > You need the openMotif libraries installed. These were removed from > Fedora due to being unfree in some fashion. I'm not sure if you can > get them on Ubuntu. Also, I've tried Lesstif and it didn't work > (crashed I believe). > > cheers, > aaron > I was able to get the packages on Ubuntu.. to do so, I had to add the non-free repository to apt-get, because it wasn't there by default. I've installed the thing, but I don't know if floorplanner works yet.Since we just got the development kit in the other day and I'm going to play with this on windows to start out (since the digilent boards come with that USB interface that only works with their software... I'll try to get this down before I figure out how to get the parallel JTAG running on linux). Thanks again! SteveArticle: 116184
On Mar 3, 6:32 am, "Brandon Jasionowski" <killerhe...@gmail.com> wrote: > On Mar 3, 12:55 am, kaosnan...@gmail.com wrote: > > > I am using these programs in my digital class but do not know how to > > link modelsim to ISE. In our school lab, after I make my schematic, I > > can run model sim to simulate it from inside ISE. Does someone know > > how I would set this up? > > Open up ISE. > > Edit > Preferences > ISE General > Integrated Tools > > Browse to modelsim.exe. > > If you change the Sources pulldown to Behavioral Simulation in your > project, you can select a test-bench, right-click > properties on the > ModelSim icon to change some properties. The ModelSim icom is not available.Article: 116185
Hi all I am working on partial reconfiguration and I need to use the cudd package for the programming part of it. I am trying to permute a function for various input orders. by using the cudd_Permute() function, but I think the function is not doing wat it is supposed to do. Has anyone come across the same problem???? If so do let me know. Thanks in advance. Mr.BArticle: 116186
On Mar 3, 7:43 pm, "Mr B" <bharadwaj...@gmail.com> wrote: > Hi all > > I am working on partial reconfiguration and I need to use the cudd > package for the programming part of it. I am trying to permute a > function for various input orders. > by using the cudd_Permute() function, but I think the function is not > doing wat it is supposed to do. > > Has anyone come across the same problem???? If so do let me know. > > Thanks in advance. > > Mr.B hey...it works fine.....so dont worry...i was having the ordering wrong... Mr.BArticle: 116187
I have some doubts
1)consider FPGA cyclone device with
I/O voltage 3.3 V,
core Voltage 1.5 V,.
output current set to 24mA or 4 mA
I/O standard set to LVTTL or SSTL-3 or etc
The operating frequency of core inside FPGA is 2 MHz
Whether it depends on how many pins of FPGA we used
for
The logic gates used for core inside is 10000 LEs
If any data is wrong,sorry for that
Incase of Xilinx FPGA ,does it depends on auxiliary
voltages
If we my doubt seems to be silly so.
How to calculate the power consumption..
Kindly clarify
2) I have a board with FPGA core 2 MHz.MCU(its an asic ) operating at
24 MHz.If anyone asks how much frequency does this board operates
at.How to find out overall set up time and holdtime(if it is
applicable).
Article: 116188Hi, I am using EDK 8.1i. I am trying add a port into a component. I know how to do it on EDK 6.3i but I don't know how to do it on EDK 8.1i. Exactly is add the port OPB_CLK on the OPB_GPIO. Thank you so much. Thang NguyenArticle: 116189
Hi, I tried to use the Add External Port button on the toolbar but it does not work. Should I add the port manually? Thanks, Thang NguyenArticle: 116190
Hi, Actually I don't think that the button Add External Port is the command to add a port to an IP. After looking in MPD file, I find the port OPB_CLK already, but I don't understand why it is not displayed in the Port Tab of EDK? Thank you, Thang NguyenArticle: 116191
I know the decoupling topic is a recurrent one but when I looked at the following page, mentioned in another thread, I noticed that they have put slits in the power plane around the FPGA: http://www.nec-tokin.com/english/product/cap/proadlizer/test1.html Is this a common practice? AFAIK larger planes have a higher capacitance, but lower frequency resonances, than smaller power islands so does this kind of slits around the FPGA avoid the lower frequency resonances while keeping the plane capacitance? Anybody has some feedback/papers/urls on this subject (large planes vs. islands vs. slits)? And BTW what do you think of these capacitors? Thanks, MarcArticle: 116192
Marc Battyani wrote: > I know the decoupling topic is a recurrent one but when I looked at the > following page, mentioned in another thread, I noticed that they have put > slits in the power plane around the FPGA: > http://www.nec-tokin.com/english/product/cap/proadlizer/test1.html > > Is this a common practice? AFAIK larger planes have a higher capacitance, > but lower frequency resonances, than smaller power islands so does this kind > of slits around the FPGA avoid the lower frequency resonances while keeping > the plane capacitance? > > Anybody has some feedback/papers/urls on this subject (large planes vs. > islands vs. slits)? > > And BTW what do you think of these capacitors? The NEC-Tokin pages you point to seems to have been written by someone who was instructed to fill pages while conveying the minimum amount of information. As far as I can tell, these devices (4-terminal networks) are not simple capacitors in the usual sense. I would be truly grateful if a c.a.f. guru could post a few lines on how they work. On the plane-splitting point, you can read app notes advocating this practice and app notes claiming that plane splitting is a discredited practice from an earlier era. I get the sense that the current (sic) best practice is that ground plane splitting is rarely a good idea and a degree of VCC plane splitting may help on a noisy board, but much better would be to find out why VCC is noisy and fix it. Again, gurus will set me straight... Also, see Symon's recent posts on puddles. TimArticle: 116193
Marc, Other than their odd name, they are extremely low impedance t-lines. As such, they are basically falt at 1200 uF from DC to daylinght. So, if you put a power supply at one end, and isolate the ground (in other words, that is what the slit is for) you transfer power to the other end (hot and ground) with a .001 ohm t-line (looks like that very low impedance at frequencies up to a few hundred MHz). So, now you see a AC short, looking either way: from the power asupply to the load, or from the load to the power supply. The Playstation 3 uses 8 of them, they isolate each huge ASIC from the other huge ASICs, and there are3 NO OTHER CAPS on the pcb.... Yes, that is right. Whereas the Wii has > 300 little caps, PS3 has these 8 "magic" t-line structures. Do they work? Well, millions of PS3 aren't chunking away happily for no reason at all. We are looking at these seriously to reduce the bypassing requirements down to the PS3 limit: a few of these, and NOTHING else (no other bypass caps whatsoever). So, it seems the NEC-TOKIN part is the first really new invention in bypassing in many many long years of people who just like to ignore that power distribution is a real issue, and one that needs some creativity. My hat is off to the engineers who created this wonder. AustinArticle: 116194
Austin wrote: > > We are looking at these seriously to reduce the bypassing requirements > down to the PS3 limit: a few of these, and NOTHING else (no other > bypass caps whatsoever). How do you handle the multiple voltages? Are they expensive?Article: 116195
Tim wrote: > Marc Battyani wrote: > >> I know the decoupling topic is a recurrent one but when I looked at >> the following page, mentioned in another thread, I noticed that they >> have put slits in the power plane around the FPGA: >> http://www.nec-tokin.com/english/product/cap/proadlizer/test1.html >> >> Is this a common practice? AFAIK larger planes have a higher >> capacitance, but lower frequency resonances, than smaller power >> islands so does this kind of slits around the FPGA avoid the lower >> frequency resonances while keeping the plane capacitance? >> >> Anybody has some feedback/papers/urls on this subject (large planes >> vs. islands vs. slits)? >> >> And BTW what do you think of these capacitors? > > > The NEC-Tokin pages you point to seems to have been written by someone > who was instructed to fill pages while conveying the minimum amount of > information. > > As far as I can tell, these devices (4-terminal networks) are not simple > capacitors in the usual sense. I would be truly grateful if a c.a.f. > guru could post a few lines on how they work. > > On the plane-splitting point, you can read app notes advocating this > practice and app notes claiming that plane splitting is a discredited > practice from an earlier era. I get the sense that the current (sic) > best practice is that ground plane splitting is rarely a good idea and a > degree of VCC plane splitting may help on a noisy board, but much better > would be to find out why VCC is noisy and fix it. Again, gurus will set > me straight... Also, see Symon's recent posts on puddles. Slits in the plane would make sense only if you were trying to keep FPGA noise out of adjacent areas of the plane. So, it will not help the FPGA, but it may help something else, which could be far less tolerant of millivolts of noise, than the FPGA. -jgArticle: 116196
Hi, In the EDK 6.3i, there is the parameter tab to change the parameter of the IP, but I can not find it in the EDK 8.1i. I try to find the .MPD file to change it manually, but I can not find it in the project. Form EDK I can right click to view MPD file, but I can not change it's content. About the add the port, the OPB_CLK actually already exit in the MPD and VHDL. I modified in the .MHS file and when I open the project again, I can see the port OPB_Clk. Anyone can give me any idea about how to find .MPD, and how to modified it? THank you, Thang NguyenArticle: 116197
First, to address the question, you're not really doing multiplication but performing division through multiplication with decimals. ISE doesn't do division either way. Like John_H said, scale your numbers up (refer to fixed point numbers) so multiplication is done with integers. When done, just scale the result down by the same amount for the final answer. A hint is to scale the numbers by a power of 2 so you just have to do bit shifts. Second, I would like to give my two cents on John_H's 1990's attitude. You shouldn't tell someone to read up on vendor specific blocks when it is clear that they are just starting out, doesn't need an optimal implementation, and don't have a firm grasp on the basics. You should give them a very simple and concise explanation at their level and a fix at their level. The synthesizer is more than capable of handling the * symbol, the OP doesn't need to worry about what Xilinx puts on the hood. If Xilinx were smart and had good programmers, which it seems they are trying to work towards, no one would need to know of any of the blocks under the hood. People should be able to "program" the hardware. The synthesis program should be smart enough to use the blocks under the hood to provide a near optimal implementation of the "program". There is a reason why people use high level programming languages not assembly. For everyone's sake, "designing" a system on an FPGA shouldn't be hard. ---Matthew Hicks > VHDL_HELP wrote: > >> Hi every body , >> i hope that you can help me , i want to do this operation: >> s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1 >> when i check the syntax , i have these errors >> ERROR:HDLParsers:808 - "C:/Xilinx/projet/operation.vhd" Line 44. * >> can >> not have such operands in this context. >> --------------------------------------------------------------------- >> --------------------------------------------------------------------- >> ---------------------- >> >> library IEEE; >> >> use IEEE.STD_LOGIC_1164.ALL; >> >> use IEEE.STD_LOGIC_ARITH.ALL; >> >> use IEEE.STD_LOGIC_UNSIGNED.ALL; >> >> entity operation is >> Port ( clk : in STD_LOGIC; >> c1 : in STD_LOGIC_VECTOR (7 downto 0); >> c2 : in STD_LOGIC_VECTOR (7 downto 0); >> c 3: in STD_LOGIC_VECTOR (7 downto 0); >> s: out STD_LOGIC_VECTOR (7 downto 0); >> end operation; >> >> architecture Behavioral of operation is >> >> begin >> >> s <=c1 * 0.2 + c2 * 0.6 + c3 * 0.1 ; >> >> end Behavioral; >> >> --------------------------------------------------------------------- >> --------------------------------------------------------------------- >> ---------------- >> >> and thanks for your help >> > Can you tell me how the synthesizer will format your floating point > result in s so it maps to silicon? > > Use scaled integers. Use the precision available in the hardware > multipliers to get a rather precise approximation of s. The digital > realm is binary, after all, not decimal. > > Please read up on how the hardware multipliers perform and how best to > utilize them. It's insanely sad to see someone trying to "program" an > FPGA rather than design it. >Article: 116198
On 4 mar, 21:12, Matthew Hicks <mdhic...@uiuc.edu> wrote:
> First, to address the question, you're not really doing multiplication but
> performing division through multiplication with decimals. ISE doesn't do
> division either way. Like John_H said, scale your numbers up (refer to fixed
> point numbers) so multiplication is done with integers. When done, just
> scale the result down by the same amount for the final answer. A hint is
> to scale the numbers by a power of 2 so you just have to do bit shifts.
>
> Second, I would like to give my two cents on John_H's 1990's attitude. You
> shouldn't tell someone to read up on vendor specific blocks when it is clear
> that they are just starting out, doesn't need an optimal implementation,
> and don't have a firm grasp on the basics. You should give them a very simple
> and concise explanation at their level and a fix at their level. The synthesizer
> is more than capable of handling the * symbol, the OP doesn't need to worry
> about what Xilinx puts on the hood. If Xilinx were smart and had good programmers,
> which it seems they are trying to work towards, no one would need to know
> of any of the blocks under the hood. People should be able to "program"
> the hardware. The synthesis program should be smart enough to use the blocks
> under the hood to provide a near optimal implementation of the "program".
> There is a reason why people use high level programming languages not assembly.
> For everyone's sake, "designing" a system on an FPGA shouldn't be hard.
>
> ---Matthew Hicks
>
> > VHDL_HELP wrote:
>
> >> Hi every body ,
> >> i hope that you can help me , i want to do this operation:
> >> s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1
> >> when i check the syntax , i have these errors
> >> ERROR:HDLParsers:808 - "C:/Xilinx/projet/operation.vhd" Line 44. *
> >> can
> >> not have such operands in this context.
> >> ---------------------------------------------------------------------
> >> ---------------------------------------------------------------------
> >> ----------------------
>
> >> library IEEE;
>
> >> use IEEE.STD_LOGIC_1164.ALL;
>
> >> use IEEE.STD_LOGIC_ARITH.ALL;
>
> >> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> >> entity operation is
> >> Port ( clk : in STD_LOGIC;
> >> c1 : in STD_LOGIC_VECTOR (7 downto 0);
> >> c2 : in STD_LOGIC_VECTOR (7 downto 0);
> >> c 3: in STD_LOGIC_VECTOR (7 downto 0);
> >> s: out STD_LOGIC_VECTOR (7 downto 0);
> >> end operation;
>
> >> architecture Behavioral of operation is
>
> >> begin
>
> >> s <=c1 * 0.2 + c2 * 0.6 + c3 * 0.1 ;
>
> >> end Behavioral;
>
> >> ---------------------------------------------------------------------
> >> ---------------------------------------------------------------------
> >> ----------------
>
> >> and thanks for your help
>
> > Can you tell me how the synthesizer will format your floating point
> > result in s so it maps to silicon?
>
> > Use scaled integers. Use the precision available in the hardware
> > multipliers to get a rather precise approximation of s. The digital
> > realm is binary, after all, not decimal.
>
> > Please read up on how the hardware multipliers perform and how best to
> > utilize them. It's insanely sad to see someone trying to "program" an
> > FPGA rather than design it.
hi , thank you for your advices first of all ,
then my equation to resolv is :
y=0.299 * R + 0.587 *G + 0.114 * B
for me what i tried to do is:
--------------------------------------------------------------------------------------------------------------------
entity rgb is
Port ( clk : in STD_LOGIC;
R : in STD_LOGIC_VECTOR (7 downto 0);
G : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC_VECTOR (31 downto 0);
Cr : out STD_LOGIC_VECTOR (31 downto 0);
Cb : out STD_LOGIC_VECTOR (31 downto 0));
end rgb;
architecture arch_rgb of rgb is
signal yreg : STD_LOGIC_VECTOR (31 downto 0);
begin
process (clk)
begin
if clk='1' and clk'event then
yreg <= "00111110100110010001011010000111" * R +
"00111111000101100100010110100001"* G +
"00111101111010010111100011010100"* B;
Y <= yreg;
end if;
end process;
end arch_rgb;
---------------------------------------------------------------------------------------------
Article: 116199On 4 mar, 21:12, Matthew Hicks <mdhic...@uiuc.edu> wrote: > First, to address the question, you're not really doing multiplication but > performing division through multiplication with decimals. ISE doesn't do > division either way. Like John_H said, scale your numbers up (refer to fixed > point numbers) so multiplication is done with integers. When done, just > scale the result down by the same amount for the final answer. A hint is > to scale the numbers by a power of 2 so you just have to do bit shifts. > > Second, I would like to give my two cents on John_H's 1990's attitude. You > shouldn't tell someone to read up on vendor specific blocks when it is clear > that they are just starting out, doesn't need an optimal implementation, > and don't have a firm grasp on the basics. You should give them a very simple > and concise explanation at their level and a fix at their level. The synthesizer > is more than capable of handling the * symbol, the OP doesn't need to worry > about what Xilinx puts on the hood. If Xilinx were smart and had good programmers, > which it seems they are trying to work towards, no one would need to know > of any of the blocks under the hood. People should be able to "program" > the hardware. The synthesis program should be smart enough to use the blocks > under the hood to provide a near optimal implementation of the "program". > There is a reason why people use high level programming languages not assembly. > For everyone's sake, "designing" a system on an FPGA shouldn't be hard. > > ---Matthew Hicks > > > VHDL_HELP wrote: > > >> Hi every body , > >> i hope that you can help me , i want to do this operation: > >> s = c1 * 0.2+ c2 * 0.6 + c3 * 0.1 > >> when i check the syntax , i have these errors > >> ERROR:HDLParsers:808 - "C:/Xilinx/projet/operation.vhd" Line 44. * > >> can > >> not have such operands in this context. > >> --------------------------------------------------------------------- > >> --------------------------------------------------------------------- > >> ---------------------- > > >> library IEEE; > > >> use IEEE.STD_LOGIC_1164.ALL; > > >> use IEEE.STD_LOGIC_ARITH.ALL; > > >> use IEEE.STD_LOGIC_UNSIGNED.ALL; > > >> entity operation is > >> Port ( clk : in STD_LOGIC; > >> c1 : in STD_LOGIC_VECTOR (7 downto 0); > >> c2 : in STD_LOGIC_VECTOR (7 downto 0); > >> c 3: in STD_LOGIC_VECTOR (7 downto 0); > >> s: out STD_LOGIC_VECTOR (7 downto 0); > >> end operation; > > >> architecture Behavioral of operation is > > >> begin > > >> s <=c1 * 0.2 + c2 * 0.6 + c3 * 0.1 ; > > >> end Behavioral; > > >> --------------------------------------------------------------------- > >> --------------------------------------------------------------------- > >> ---------------- > > >> and thanks for your help > > > Can you tell me how the synthesizer will format your floating point > > result in s so it maps to silicon? > > > Use scaled integers. Use the precision available in the hardware > > multipliers to get a rather precise approximation of s. The digital > > realm is binary, after all, not decimal. > > > Please read up on how the hardware multipliers perform and how best to > > utilize them. It's insanely sad to see someone trying to "program" an > > FPGA rather than design it. this program is with syntax correct but not synthetisable , what i tried to d ois to convert the reals with binary ones
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z