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On Wed, 28 Feb 2007 02:59:36 GMT, "Rob" <robnstef@frontiernet.net> wrote: >Does anyone know if there is a Spartan based uBlaze development board that >has SRAM on it? > Take a look at: http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=SEB3-400&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=BOARDS Best regards, zaraArticle: 116026
cs_posting@hotmail.com writes: > I believe that one option is to use the Xilinx cable, but download > your own firmware to it rather than the firmware the Xilinx tools > download. Since the firmware defines the interface, you can then use > it anyway you like... Yes, you can do that. You have to download your own CPLD configuration too, unless someone reverse-engineers the one that Xilinx uses. So every time you switch between using the cable for Xilinx software vs. for your own software, you have to wait while the CPLD is reprogrammed. Sigh.Article: 116027
On 2007-02-28, Eric Smith <eric@brouhaha.com> wrote: > MotM wrote: >> Is there a way to access the platform cable USB from a user program >> (i.e., from outside the Xilinx toolchain) ? What I'd like to do is >> access a BSCAN module inside my design from a custom win32 >> application. > > Andreas Ehliar wrote: >> Take a look at the following URLs: >> http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag53.htm >> and http://www.s3group.com/system_ic/gnat/ > > Those articles show how to acess the JTAG interface from logic inside > the FPGA. What MotM wants is to access the JTAG chain from the PC. > > Unfortunately Xilinx does not provide any API to do this, and believes > that the interface to their PC4 and Platform USB cables is some kind > of super-valuable trade secret, so the answer is that you can't do > it with the Xilinx cable. You have to use a third party JTAG interface, > and swap JTAG cables back and forth. :-( > > There *must* be some kind of API that Xilinx uses in their own software > to do this. C'mon, guys, open it up for customer use! If you read the article thoroughly you can see that they include some TCL scripts that use Xilinx' drivers to access the JTAG interface from the PC. I haven't tried this myself but my impression is that you will have an easier time doing that if you have access to chipscope but it should be doable without. The following is a paragraph taken from the first link I posted above: Software Support ---------------- Xilinx provides all of the tools required for you to write simple scripts to access the USER registers through the JTAG interface. ISE tools provide a custom TCL shell (xtclsh), while the Xilinx ChipScope Pro tools provide a TCL script (Figure 5) (tcljtag.tcl) that creates a number of high-level TCL commands to control the JTAG interface. /AndreasArticle: 116028
Hi Eric, On 28 Feb., 05:38, Eric Smith <e...@brouhaha.com> wrote: > it with the Xilinx cable. You have to use a third party JTAG interface, > and swap JTAG cables back and forth. :-( > > There *must* be some kind of API that Xilinx uses in their own software > to do this. C'mon, guys, open it up for customer use! I really wonder why they are keeping it a secret as I don't think that a JTAG adaptor is so hard to build. Perhaps it was developed by a third party and Xilinx has no way to open it? Greetings, TorstenArticle: 116029
Hello. To improve the speed, I want to implement pipeline.But variables make me sad... For example -- input: IN1,IN2 , output:OUT signal A,B,C; process(clk) variable V_1,V_2,V_3; begin V_1 := IN1 A <= V_1 V_2 := A B <= IN2 V_3 := B+V_2 C <= V_3 OUT <= C end process; Is there anyone who can break down above process?Article: 116030
In order to improve the performance, I try to implement the pipeline. But variables make me sad. For example. -- Input: IN1, IN2 / output : OUT signal S1,S2,S3 process(clk) variable V1,V2,V3 begin V1 := IN1 S1 <= V1 V2 <= S1 S2<=IN2 V3:= S2+V2 S3 <= V3 OUT<= S3 end process; is there anyone with idea about this?Article: 116031
lkjrsy@gmail.com writes: > In order to improve the performance, I try to implement the pipeline. > But variables make me sad. > It might help us to help you if you tell us what function you are trying to pipeline, rather than us having to figure out what you think you might be trying to do from your code :-) Which seems to be posted three times, differently! Try posting your un-pipelined original code... As a general point, you can pipeline using variables by writing the pipeline stages "bottom up" (ie the first stage at the bottom of the process). This will infer flipflops for each variable. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 116032
Rob schrieb: > Hello, > > Does anyone know if there is a Spartan based uBlaze development board that > has SRAM on it? Take a look at the Digilent StarterBoard: http://www.digilentinc.com/Products/Detail.cfm?Nav1=Products&Nav2=Programmable&Prod=S3BOARD Best regards AndreasArticle: 116033
Andreas Ehliar wrote: > On 2007-02-28, Eric Smith <eric@brouhaha.com> wrote: >> MotM wrote: >>> Is there a way to access the platform cable USB from a user program >>> (i.e., from outside the Xilinx toolchain) ? What I'd like to do is >>> access a BSCAN module inside my design from a custom win32 >>> application. >> Andreas Ehliar wrote: >>> Take a look at the following URLs: >>> http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag53.htm >>> and http://www.s3group.com/system_ic/gnat/ >> Those articles show how to acess the JTAG interface from logic inside >> the FPGA. What MotM wants is to access the JTAG chain from the PC. >> >> Unfortunately Xilinx does not provide any API to do this, and believes >> that the interface to their PC4 and Platform USB cables is some kind >> of super-valuable trade secret, so the answer is that you can't do >> it with the Xilinx cable. You have to use a third party JTAG interface, >> and swap JTAG cables back and forth. :-( >> >> There *must* be some kind of API that Xilinx uses in their own software >> to do this. C'mon, guys, open it up for customer use! > > If you read the article thoroughly you can see that they include some > TCL scripts that use Xilinx' drivers to access the JTAG interface from > the PC. > > I haven't tried this myself but my impression is that you will have > an easier time doing that if you have access to chipscope but it > should be doable without. The following is a paragraph taken from the > first link I posted above: I have tried it and it works. I use it quite often to put "debug" modules that I can control easly via my PC without the need for another interface. (And also you don't have to bring the signals to your top level ;) It's not very fast though ... IIRC, it takes me almost 30 min to grab 16Mbytes of data ... The wider your User register is, the faster in my experience. The interface has changed in 9.1, I haven't tried the new one yet. Sylvain From fred@n0spam.com Wed Feb 28 04:07:44 2007 Path: newssvr12.news.prodigy.net!newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newsfeed.telusplanet.net!newsfeed2.telusplanet.net!newsfeed.telus.net!news-feed01.roc.ny.frontiernet.net!nntp.frontiernet.net!newshosting.com.MISMATCH!nx02.iad01.newshosting.com!newshosting.com!198.186.194.251.MISMATCH!news-out.readnews.com!transit4.readnews.com!newspeer1.nwr.nac.net!colt.net!feeder.news-service.com!feeder4.cambrium.nl!feed.tweaknews.nl!212.27.60.9.MISMATCH!proxad.net!news.clara.net!wagner.news.clara.net!monkeydust.news.clara.net!proxy00.news.clara.net From: "Fred" <fred@n0spam.com> Newsgroups: comp.arch.fpga Subject: PCI-E TS1s Date: Wed, 28 Feb 2007 12:07:44 -0000 Lines: 13 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3028 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3028 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 6171552aee21853e49130c1003332c082722371033d1032369e0144a45e5709d NNTP-Posting-Date: Wed, 28 Feb 2007 12:07:57 +0000 Message-Id: <1172664477.23596.0@proxy00.news.clara.net> Xref: prodigy.net comp.arch.fpga:127513 I'm writing the initial state machine for a PCI-Express card and am stuck at the very first hurdle. I'm using a Philips PX1011 PHY and I'm able detect the receiver on the motherboard. I then send it TS1s with pad characters in the Link and Lane numbers but the motherboard transmitter doesn't transmit TS2 but instead goes into idle state. I'm convinced that correct serial data is coming out of the PHY. There's no need for speed negotiation since both are advertising the slowest speed. I would be grateful if anyone here could help.Article: 116034
Is there anybody in this group who has experience with V4FX MGT Sonet Alignment? The documentation is rather short on details. The interaction of the two alignment stages is not clear to me at all. What we see is that we get a comma detect signaled and the output data stream is correctly aligned. As a reaction on that we turn off ENPCOMMAALIGN and ENMCOMMAALIGN. But nevertheless the MGT keeps realigning on any new occurence of the comma pattern. (only the bits are shifted around, there is no new comma detect signaled.) What am I missing? Kolja SulimmaArticle: 116035
Hello, I have been using batch files to handle the build process with a Xilinx flow for a while. Now I want to move to a more sophisticated approach to handle dependencies better. I don't really want to use makefiles, I find find them too arcane and hard to write. That's where SCons comes in. It seems like a great alternative to make (plus it's written in Python and I've been wanting to learn that language for a while now). Does anyone have any experience with SCons and ideally, scripts they would like to share? Example scripts for a fpga flow would certainly help with the learning curve. Thanks. Patrick DuboisArticle: 116036
"Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message news:es0ue8$9g5$1@lnx107.hrz.tu-darmstadt.de... > "Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> > wrote: > ... >> Hi Uwe, > >> Thanks for bringing this to our attention. I've passed this on to our >> distribution manager and he's working to remedy the situation. Both >> the XC3S400 and the XC3S500E FPGAs are most definitely available. The >> working theory is that the PQ208 package option is not the highest >> running product combinations. Consequently, our distributors aren't >> stocking them. I fully understand the attraction of the QFP package, >> however. > > As explained in the XC3SAN thread, the availability of big PQ208 parts may > not lead itself to big demand on the "many-pin" PQ parts. But the ease of > prototyping may lead to more design wins and so for demand for > "not-so-many" PQ and for BGA parts... > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > Hi Uwe, I think this is one of those few times where I'm tending to disagree with you. IMHO, the SI properties of the PQ208 package are so terrible that any prototype made using a PQ208 containing a die capable of sub-ns rise times is not going to accurately reflect what would happen when you build it with a decent FBGA package. Sure the internal logic will work ok, but that's what simulators are good at. It might be time to bite the bullet and invest in a toaster oven! I know Philip posted not too long ago about his set up, perhaps it might be of interest to you. The other choice that I can think of is to use an interposer to connect the FPGA to the board. I read recently about magic elastomer materials to connect BGA to PCBs with excellent SI properties. Best regards, Syms.Article: 116037
On Feb 26, 5:25 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > self wrote: > > Hello All, > > > I have a Xilinx ML501 board and I want to use the Xilinx XCF32P > > platform flash to configure the XC5VLX50. > > > I can program the LX50 directly accross the JTAG chain and the design > > runs correctly (flashing LED's). > > > Also the XCF32P does show up on the chain and Impact lets me program > > it. Unfortunately, when I hit the program button my design does not > > come up. The done LED goes true after a delay as if the part is > > programming from some other source. > > > There is a 8 position dip switch on the board, SW15, that apparently > > controls the configuration source but the documentation is not clear > > about how to set that switch for platform flash. I have all zeros > > selected now. > > > Can anyone just tell me how to set SW15 to configure from the platform > > flash on the ML501? > > This is documented on page 28 of the ML501 User Guide (ug226). > > Ed McGettigan > -- > Xilinx Inc.- Hide quoted text - > > - Show quoted text - Ed, Do you have a ML501 board? If you have been able to program the FPGA from the platform flash please tell me what setting you used for SW15. Thanks, Pete DudleyArticle: 116038
The question I have is can you use the platform flash as a means to hold your MicroBlaze code and have a boot loader grab from it? On Feb 28, 5:04 am, Andreas Hofmann <ahofm...@ti.cs.uni-frankfurt.de> wrote: > Rob schrieb: > > > Hello, > > > Does anyone know if there is a Spartan based uBlaze development board that > > has SRAM on it? > > Take a look at the Digilent StarterBoard:http://www.digilentinc.com/Products/Detail.cfm?Nav1=Products&Nav2=Pro... > > Best regards > AndreasArticle: 116039
Symon wrote: > The other choice that I can think of is to use an interposer to connect the > FPGA to the board. I read recently about magic elastomer materials to > connect BGA to PCBs with excellent SI properties. Is that the Samtec stuff? Wasn't in their catalog last time I looked.Article: 116040
On Feb 27, 1:47 am, robquig...@gmail.com wrote: > Hey all. > > I dont know whats happened my Modelsim but anytime I try and do > anything with it like open/close/create a project I get this error: > > # ** Error: (vsim-7) Failed to open ini file "tmpfile" in write mode. > # No space left on device. (errno = ENOSPC) > > There is almost 3Gb of free space on my harddrive so I dont understand > the "No space left on device" line. > > Has anyone seen this before? > > Any suggestions? > > Cheers, > > Rob Rog, 1. Please check if the directory is Read-Only. By right-clicking the directory name in Explore window, you may see 'Properties' in the last item of popped menu and left click it, then you can check its Attribute: Read-only. If the directory is in read-only status, Modelsim fails to write its files back into the directory. 2. Check the file if it is read-only as above. WengArticle: 116041
Hello,
I have a ComBlock 1200 (comblock.com) FPGA board with a Analog Devices
AD9860 MxFE interface. I'm trying to get the SPI interface up and
running to configure it.
Right now, I can write to any register. I've tested this by writing
ramping levels to the aux DACs and watching the output on a scope. I
also have the entire SPI bus on a scope, and everything looks good.
The problem is reads. Everything reads back 0. I've looked at the MISO
signal on a scope, and it's there, and properly aligned. I've brought
it out from the FPGA on a separate test point to verify that I didn't
mess up the UCF - the signal is making it into the device. I even
looked in FPGA editor, and the signal is getting all the way to the
opb_spi block.
Note, I am using the manual select option. The MxFE doesn't like the
SS line going high between bytes, so I have to wrap each transfer with
a slaveselect call. This is the jist of what I'm doing:
Status = XSpi_SetOptions( &MxFE_SPI, XSP_MANUAL_SSELECT_OPTION |
XSP_MASTER_OPTION);
Status = XSpi_Start( &MxFE_SPI );
if( Status != XST_SUCCESS ){
xil_printf("->Error! Failed to configure MxFE SPI Interrupts.\n
\r");
return XST_FAILURE;
}
Status = XSpi_SetSlaveSelect( &MxFE_SPI, 0x1 );
Status = XSpi_Transfer( &MxFE_SPI, SPI_TxBuffer, SPI_RxBuffer, 2 );
if( Status != XST_SUCCESS ){
xil_printf("Whoops! SPI Failure.\n\r");
return XST_FAILURE;
}
Status = XSpi_SetSlaveSelect( &MxFE_SPI, 0x0 );
Note, both SPI_TxBuffer and SPI_RxBuffer are the same length as the
FIFO depth, but most transfers are only 2 bytes (address & data). ADC
reads (if they worked) would be three bytes (1 Address, 2 Data) When I
try to raed, the entire SPI_RxBuffer is empty. (all values the same as
their initialized values)
Also, the ISR does appear to be working. (Writes work fine, and I can
see the interrupt signal on the scope)
What could I be doing wrong?
Article: 116042I've just ordered couple of these cables. To make them works with my JTAG connector, I built a little 10 inches thong adapter, one end connects to the existing Xilinx 2.5 mm ribbon connector, the other end fits to my JTAG connector. The total legnth of the Xilinx ribbon and the thong is about 16 inches. Now comes the mistery, whenever I try to program the devices (proms) iMPACT 9.1i reported bla.. bla.. bla.. the device ID doesn't match bsld, It's really a headache, trying upgrade drivers, service packs, bsld,...nothing helped at all, I also ran all available speeds from slowest to max, result were the same As my last trial I made the thong a half legnth as before, total legnth now about 11 inches, as you guess, it worked Is there any doc/manual that specify the max legnth for this cable? Thanks allArticle: 116043
comp.arch.fpga wrote: > Is there anybody in this group who has experience with V4FX MGT Sonet > Alignment? > > The documentation is rather short on details. The interaction of the > two alignment stages is not clear to me at all. > What we see is that we get a comma detect signaled and the output data > stream is correctly aligned. > As a reaction on that we turn off ENPCOMMAALIGN and ENMCOMMAALIGN. > > But nevertheless the MGT keeps realigning on any new occurence of the > comma pattern. > (only the bits are shifted around, there is no new comma detect > signaled.) The ENPCOMMAALIGN and ENMCOMMAALIGN are for 8b10b encoded steams which are not used by SONET. Ed McGettigan -- Xilinx Inc.Article: 116044
On 28 Feb., 18:52, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > comp.arch.fpga wrote: > > Is there anybody in this group who has experience with V4FX MGT Sonet > > Alignment? > > > The documentation is rather short on details. The interaction of the > > two alignment stages is not clear to me at all. > > What we see is that we get a comma detect signaled and the output data > > stream is correctly aligned. > > As a reaction on that we turn offENPCOMMAALIGNand ENMCOMMAALIGN. > > > But nevertheless the MGT keeps realigning on any new occurence of the > > comma pattern. > > (only the bits are shifted around, there is no new comma detect > > signaled.) > > TheENPCOMMAALIGNand ENMCOMMAALIGN are for 8b10b encoded steams > which are not used by SONET. > > Ed McGettigan > -- > Xilinx Inc. According to Table 3-18 in ug076 the attribute ENMCOMMAALIGN controls the byte aligner and ENPCOMMAALIGN controls both the byte aligner and the SONET aligner. According to that table when ENxCOMMAALIGN = '1' the byte aligner should "realign byte alignment mux when the A1 symbol is found on a non-byte aligned boundary". That is exactly what we see happening even tens of clock cycles after we set ENxCOMMAALIGN = '0'. Instead we require it to "hold alignement mux position" as it should according to documentation. Kolja SulimmaArticle: 116045
On Feb 28, 12:31 pm, "Marlboro" <cco...@netscape.net> wrote: > Is there any doc/manual that specify the max legnth for this cable? Yes. The official specification is "short"Article: 116046
I'm trying to use the Altera USB Byte Blaster Cable on Linux (Scientific Linux 4.4, i.e. RHEL 4). The Programmer application sees the cable, however it says there are insufficient privileges on the port. I've tried running Quartus as root, that didn't fix the problem. There is no Firewall and Secure Linux is disabled. Anyone have any suggestions?Article: 116047
Signal Integrity is the big problem with specifying a maximum length for the ribbon cable. We have built a ribbon cable 30 ft long (using the same materials as listed in the PC4 Users Guide) and it worked just fine. We have also built a 12 inch cable and it didn't work. For this reason a maximum ribbon cable length is not specified. The ribbon cable that is shipped with the USB/PC4 cable has been tested and was designed with signal intergity in mind and will properly isolate the configuration signals. I don't really follow the 'thong' implementation, but would recommend two alternatives. Build a single ribbon cable the length you need using the materials specified in the Users Guide (do not connect two individual cables together trying to increase the length) or use a longer USB cable (from the PC/Linux box to the cable pod). -David <cs_posting@hotmail.com> wrote in message news:1172688676.682714.125880@s48g2000cws.googlegroups.com... > On Feb 28, 12:31 pm, "Marlboro" <cco...@netscape.net> wrote: > >> Is there any doc/manual that specify the max legnth for this cable? > > Yes. The official specification is "short" > >Article: 116048
Hi Davide, Sorry for my English, I meant it a "dongle" not a thong :))) Looks like I'm missing you something here. You have a 30ft ribbon cable working just fine and couldn't make it works at 1ft ? I know signal integrity is length depedency, but those numbers (30, 1) just building up my fuzziness Regard,Article: 116049
On Feb 28, 1:54 pm, "B. Joshua Rosen" <bjro...@polybusPleaseDontSpamMe.com> wrote: > I'm trying to use the Altera USB Byte Blaster Cable on Linux (Scientific > Linux 4.4, i.e. RHEL 4). The Programmer application sees the cable, > however it says there are insufficient privileges on the port. I've tried > running Quartus as root, that didn't fix the problem. There is no Firewall > and Secure Linux is disabled. Anyone have any suggestions? Yes, the program needs to call ioperm() on the printer port address before trying to talk to it. Being root (or an setuid root executable) just means you have the right to make that function call; it doesn't mean it's necessarily been done.
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z